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986d1dfb | 1 | /** @file\r |
53b1dd10 | 2 | Timer Architectural Protocol module using High Precision Event Timer (HPET)\r |
986d1dfb | 3 | \r |
5a702acd | 4 | Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r |
e1d302e5 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
986d1dfb | 6 | \r |
7 | **/\r | |
8 | \r | |
9 | #include <PiDxe.h>\r | |
10 | \r | |
11 | #include <Protocol/Cpu.h>\r | |
12 | #include <Protocol/Timer.h>\r | |
13 | \r | |
14 | #include <Library/IoLib.h>\r | |
15 | #include <Library/PcdLib.h>\r | |
16 | #include <Library/BaseLib.h>\r | |
17 | #include <Library/DebugLib.h>\r | |
18 | #include <Library/UefiBootServicesTableLib.h>\r | |
19 | #include <Library/LocalApicLib.h>\r | |
20 | #include <Library/IoApicLib.h>\r | |
21 | \r | |
22 | #include <Register/LocalApic.h>\r | |
23 | #include <Register/IoApic.h>\r | |
24 | #include <Register/Hpet.h>\r | |
25 | \r | |
26 | ///\r | |
27 | /// Define value for an invalid HPET Timer index.\r | |
28 | ///\r | |
29 | #define HPET_INVALID_TIMER_INDEX 0xff\r | |
30 | \r | |
31 | ///\r | |
32 | /// Timer Architectural Protocol function prototypes.\r | |
33 | ///\r | |
34 | \r | |
35 | /**\r | |
36 | This function registers the handler NotifyFunction so it is called every time\r | |
37 | the timer interrupt fires. It also passes the amount of time since the last\r | |
38 | handler call to the NotifyFunction. If NotifyFunction is NULL, then the\r | |
39 | handler is unregistered. If the handler is registered, then EFI_SUCCESS is\r | |
40 | returned. If the CPU does not support registering a timer interrupt handler,\r | |
41 | then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler\r | |
42 | when a handler is already registered, then EFI_ALREADY_STARTED is returned.\r | |
43 | If an attempt is made to unregister a handler when a handler is not registered,\r | |
44 | then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to\r | |
45 | register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR\r | |
46 | is returned.\r | |
47 | \r | |
48 | @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r | |
5a702acd LG |
49 | @param NotifyFunction The function to call when a timer interrupt fires.\r |
50 | This function executes at TPL_HIGH_LEVEL. The DXE\r | |
51 | Core will register a handler for the timer interrupt,\r | |
52 | so it can know how much time has passed. This\r | |
53 | information is used to signal timer based events.\r | |
986d1dfb | 54 | NULL will unregister the handler.\r |
55 | \r | |
56 | @retval EFI_SUCCESS The timer handler was registered.\r | |
57 | @retval EFI_UNSUPPORTED The platform does not support timer interrupts.\r | |
58 | @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already\r | |
59 | registered.\r | |
60 | @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not\r | |
61 | previously registered.\r | |
62 | @retval EFI_DEVICE_ERROR The timer handler could not be registered.\r | |
63 | \r | |
64 | **/\r | |
65 | EFI_STATUS\r | |
66 | EFIAPI\r | |
67 | TimerDriverRegisterHandler (\r | |
68 | IN EFI_TIMER_ARCH_PROTOCOL *This,\r | |
69 | IN EFI_TIMER_NOTIFY NotifyFunction\r | |
70 | );\r | |
71 | \r | |
72 | /**\r | |
73 | This function adjusts the period of timer interrupts to the value specified\r | |
74 | by TimerPeriod. If the timer period is updated, then the selected timer\r | |
75 | period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If\r | |
76 | the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.\r | |
77 | If an error occurs while attempting to update the timer period, then the\r | |
78 | timer hardware will be put back in its state prior to this call, and\r | |
79 | EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt\r | |
80 | is disabled. This is not the same as disabling the CPU's interrupts.\r | |
81 | Instead, it must either turn off the timer hardware, or it must adjust the\r | |
82 | interrupt controller so that a CPU interrupt is not generated when the timer\r | |
83 | interrupt fires.\r | |
84 | \r | |
85 | @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r | |
86 | @param TimerPeriod The rate to program the timer interrupt in 100 nS units.\r | |
5a702acd LG |
87 | If the timer hardware is not programmable, then\r |
88 | EFI_UNSUPPORTED is returned. If the timer is programmable,\r | |
89 | then the timer period will be rounded up to the nearest\r | |
90 | timer period that is supported by the timer hardware.\r | |
91 | If TimerPeriod is set to 0, then the timer interrupts\r | |
986d1dfb | 92 | will be disabled.\r |
93 | \r | |
94 | @retval EFI_SUCCESS The timer period was changed.\r | |
95 | @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.\r | |
96 | @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.\r | |
97 | \r | |
98 | **/\r | |
99 | EFI_STATUS\r | |
100 | EFIAPI\r | |
101 | TimerDriverSetTimerPeriod (\r | |
102 | IN EFI_TIMER_ARCH_PROTOCOL *This,\r | |
103 | IN UINT64 TimerPeriod\r | |
104 | );\r | |
105 | \r | |
106 | /**\r | |
107 | This function retrieves the period of timer interrupts in 100 ns units,\r | |
108 | returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod\r | |
109 | is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is\r | |
110 | returned, then the timer is currently disabled.\r | |
111 | \r | |
112 | @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r | |
113 | @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units.\r | |
114 | If 0 is returned, then the timer is currently disabled.\r | |
115 | \r | |
116 | @retval EFI_SUCCESS The timer period was returned in TimerPeriod.\r | |
117 | @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.\r | |
118 | \r | |
119 | **/\r | |
120 | EFI_STATUS\r | |
121 | EFIAPI\r | |
122 | TimerDriverGetTimerPeriod (\r | |
123 | IN EFI_TIMER_ARCH_PROTOCOL *This,\r | |
124 | OUT UINT64 *TimerPeriod\r | |
125 | );\r | |
126 | \r | |
127 | /**\r | |
128 | This function generates a soft timer interrupt. If the platform does not support soft\r | |
129 | timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.\r | |
130 | If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()\r | |
131 | service, then a soft timer interrupt will be generated. If the timer interrupt is\r | |
132 | enabled when this service is called, then the registered handler will be invoked. The\r | |
133 | registered handler should not be able to distinguish a hardware-generated timer\r | |
134 | interrupt from a software-generated timer interrupt.\r | |
135 | \r | |
136 | @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r | |
137 | \r | |
138 | @retval EFI_SUCCESS The soft timer interrupt was generated.\r | |
9349c2e6 | 139 | @retval EFI_UNSUPPORTED The platform does not support the generation of soft\r |
986d1dfb | 140 | timer interrupts.\r |
141 | \r | |
142 | **/\r | |
143 | EFI_STATUS\r | |
144 | EFIAPI\r | |
145 | TimerDriverGenerateSoftInterrupt (\r | |
146 | IN EFI_TIMER_ARCH_PROTOCOL *This\r | |
147 | );\r | |
5a702acd | 148 | \r |
986d1dfb | 149 | ///\r |
150 | /// The handle onto which the Timer Architectural Protocol will be installed.\r | |
151 | ///\r | |
152 | EFI_HANDLE mTimerHandle = NULL;\r | |
153 | \r | |
154 | ///\r | |
155 | /// The Timer Architectural Protocol that this driver produces.\r | |
156 | ///\r | |
157 | EFI_TIMER_ARCH_PROTOCOL mTimer = {\r | |
158 | TimerDriverRegisterHandler,\r | |
159 | TimerDriverSetTimerPeriod,\r | |
160 | TimerDriverGetTimerPeriod,\r | |
161 | TimerDriverGenerateSoftInterrupt\r | |
162 | };\r | |
163 | \r | |
164 | ///\r | |
165 | /// Pointer to the CPU Architectural Protocol instance.\r | |
166 | ///\r | |
167 | EFI_CPU_ARCH_PROTOCOL *mCpu = NULL;\r | |
168 | \r | |
169 | ///\r | |
170 | /// The notification function to call on every timer interrupt.\r | |
171 | ///\r | |
172 | EFI_TIMER_NOTIFY mTimerNotifyFunction = NULL;\r | |
173 | \r | |
174 | ///\r | |
175 | /// The current period of the HPET timer interrupt in 100 ns units.\r | |
176 | ///\r | |
177 | UINT64 mTimerPeriod = 0;\r | |
178 | \r | |
179 | ///\r | |
22fde64e | 180 | /// The number of HPET timer ticks required for the current HPET rate specified by mTimerPeriod.\r |
986d1dfb | 181 | ///\r |
22fde64e | 182 | UINT64 mTimerCount;\r |
183 | \r | |
184 | ///\r | |
185 | /// Mask used for counter and comparator calculations to adjust for a 32-bit or 64-bit counter.\r | |
186 | ///\r | |
187 | UINT64 mCounterMask;\r | |
188 | \r | |
189 | ///\r | |
190 | /// The HPET main counter value from the most recent HPET timer interrupt.\r | |
191 | ///\r | |
192 | volatile UINT64 mPreviousMainCounter;\r | |
193 | \r | |
194 | volatile UINT64 mPreviousComparator;\r | |
986d1dfb | 195 | \r |
196 | ///\r | |
197 | /// The index of the HPET timer being managed by this driver.\r | |
198 | ///\r | |
199 | UINTN mTimerIndex;\r | |
200 | \r | |
201 | ///\r | |
202 | /// The I/O APIC IRQ that the HPET Timer is mapped if I/O APIC mode is used.\r | |
203 | ///\r | |
204 | UINT32 mTimerIrq;\r | |
205 | \r | |
206 | ///\r | |
207 | /// Cached state of the HPET General Capabilities register managed by this driver.\r | |
208 | /// Caching the state reduces the number of times the configuration register is read.\r | |
209 | ///\r | |
210 | HPET_GENERAL_CAPABILITIES_ID_REGISTER mHpetGeneralCapabilities;\r | |
211 | \r | |
212 | ///\r | |
213 | /// Cached state of the HPET General Configuration register managed by this driver.\r | |
214 | /// Caching the state reduces the number of times the configuration register is read.\r | |
215 | ///\r | |
216 | HPET_GENERAL_CONFIGURATION_REGISTER mHpetGeneralConfiguration;\r | |
217 | \r | |
218 | ///\r | |
5a702acd | 219 | /// Cached state of the Configuration register for the HPET Timer managed by\r |
986d1dfb | 220 | /// this driver. Caching the state reduces the number of times the configuration\r |
221 | /// register is read.\r | |
222 | ///\r | |
223 | HPET_TIMER_CONFIGURATION_REGISTER mTimerConfiguration;\r | |
224 | \r | |
225 | ///\r | |
226 | /// Counts the number of HPET Timer interrupts processed by this driver.\r | |
227 | /// Only required for debug.\r | |
228 | ///\r | |
229 | volatile UINTN mNumTicks;\r | |
230 | \r | |
231 | /**\r | |
232 | Read a 64-bit register from the HPET\r | |
233 | \r | |
234 | @param Offset Specifies the offset of the HPET register to read.\r | |
235 | \r | |
236 | @return The 64-bit value read from the HPET register specified by Offset.\r | |
237 | **/\r | |
238 | UINT64\r | |
239 | HpetRead (\r | |
240 | IN UINTN Offset\r | |
241 | )\r | |
242 | {\r | |
243 | return MmioRead64 (PcdGet32 (PcdHpetBaseAddress) + Offset);\r | |
244 | }\r | |
245 | \r | |
246 | /**\r | |
247 | Write a 64-bit HPET register.\r | |
248 | \r | |
53b1dd10 | 249 | @param Offset Specifies the offset of the HPET register to write.\r |
986d1dfb | 250 | @param Value Specifies the value to write to the HPET register specified by Offset.\r |
251 | \r | |
252 | @return The 64-bit value written to HPET register specified by Offset.\r | |
253 | **/\r | |
254 | UINT64\r | |
255 | HpetWrite (\r | |
256 | IN UINTN Offset,\r | |
257 | IN UINT64 Value\r | |
258 | )\r | |
259 | {\r | |
260 | return MmioWrite64 (PcdGet32 (PcdHpetBaseAddress) + Offset, Value);\r | |
261 | }\r | |
262 | \r | |
263 | /**\r | |
264 | Enable or disable the main counter in the HPET Timer.\r | |
265 | \r | |
266 | @param Enable If TRUE, then enable the main counter in the HPET Timer.\r | |
267 | If FALSE, then disable the main counter in the HPET Timer.\r | |
268 | **/\r | |
269 | VOID\r | |
270 | HpetEnable (\r | |
271 | IN BOOLEAN Enable\r | |
272 | )\r | |
273 | {\r | |
5a702acd | 274 | mHpetGeneralConfiguration.Bits.MainCounterEnable = Enable ? 1 : 0;\r |
986d1dfb | 275 | HpetWrite (HPET_GENERAL_CONFIGURATION_OFFSET, mHpetGeneralConfiguration.Uint64);\r |
276 | }\r | |
277 | \r | |
278 | /**\r | |
279 | The interrupt handler for the HPET timer. This handler clears the HPET interrupt\r | |
280 | and computes the amount of time that has passed since the last HPET timer interrupt.\r | |
281 | If a notification function is registered, then the amount of time since the last\r | |
282 | HPET interrupt is passed to that notification function in 100 ns units. The HPET\r | |
5a702acd | 283 | time is updated to generate another interrupt in the required time period.\r |
986d1dfb | 284 | \r |
619ad10f TH |
285 | @param InterruptType The type of interrupt that occurred.\r |
286 | @param SystemContext A pointer to the system context when the interrupt occurred.\r | |
986d1dfb | 287 | **/\r |
288 | VOID\r | |
289 | EFIAPI\r | |
290 | TimerInterruptHandler (\r | |
291 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
292 | IN EFI_SYSTEM_CONTEXT SystemContext\r | |
293 | )\r | |
294 | {\r | |
22fde64e | 295 | UINT64 MainCounter;\r |
296 | UINT64 Comparator;\r | |
986d1dfb | 297 | UINT64 TimerPeriod;\r |
22fde64e | 298 | UINT64 Delta;\r |
299 | \r | |
986d1dfb | 300 | //\r |
301 | // Count number of ticks\r | |
302 | //\r | |
303 | DEBUG_CODE (mNumTicks++;);\r | |
304 | \r | |
305 | //\r | |
306 | // Clear HPET timer interrupt status\r | |
307 | //\r | |
308 | HpetWrite (HPET_GENERAL_INTERRUPT_STATUS_OFFSET, LShiftU64 (1, mTimerIndex));\r | |
309 | \r | |
310 | //\r | |
311 | // Local APIC EOI\r | |
312 | //\r | |
313 | SendApicEoi ();\r | |
314 | \r | |
315 | //\r | |
22fde64e | 316 | // Disable HPET timer when adjusting the COMPARATOR value to prevent a missed interrupt\r |
317 | //\r | |
318 | HpetEnable (FALSE);\r | |
5a702acd | 319 | \r |
22fde64e | 320 | //\r |
321 | // Capture main counter value\r | |
986d1dfb | 322 | //\r |
22fde64e | 323 | MainCounter = HpetRead (HPET_MAIN_COUNTER_OFFSET);\r |
986d1dfb | 324 | \r |
325 | //\r | |
22fde64e | 326 | // Get the previous comparator counter\r |
986d1dfb | 327 | //\r |
22fde64e | 328 | mPreviousComparator = HpetRead (HPET_TIMER_COMPARATOR_OFFSET + mTimerIndex * HPET_TIMER_STRIDE);\r |
986d1dfb | 329 | \r |
22fde64e | 330 | //\r |
331 | // Set HPET COMPARATOR to the value required for the next timer tick\r | |
332 | //\r | |
333 | Comparator = (mPreviousComparator + mTimerCount) & mCounterMask;\r | |
334 | \r | |
335 | if ((mPreviousMainCounter < MainCounter) && (mPreviousComparator > Comparator)) {\r | |
336 | //\r | |
337 | // When comparator overflows\r | |
338 | //\r | |
339 | HpetWrite (HPET_TIMER_COMPARATOR_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, Comparator);\r | |
340 | } else if ((mPreviousMainCounter > MainCounter) && (mPreviousComparator < Comparator)) {\r | |
341 | //\r | |
342 | // When main counter overflows\r | |
343 | //\r | |
344 | HpetWrite (HPET_TIMER_COMPARATOR_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, (MainCounter + mTimerCount) & mCounterMask);\r | |
345 | } else {\r | |
346 | //\r | |
347 | // When both main counter and comparator do not overflow or both do overflow\r | |
348 | //\r | |
349 | if (Comparator > MainCounter) {\r | |
350 | HpetWrite (HPET_TIMER_COMPARATOR_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, Comparator);\r | |
351 | } else {\r | |
352 | HpetWrite (HPET_TIMER_COMPARATOR_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, (MainCounter + mTimerCount) & mCounterMask);\r | |
353 | }\r | |
354 | }\r | |
355 | \r | |
356 | //\r | |
357 | // Enable the HPET counter once the new COMPARATOR value has been set.\r | |
358 | //\r | |
359 | HpetEnable (TRUE);\r | |
5a702acd | 360 | \r |
986d1dfb | 361 | //\r |
362 | // Check to see if there is a registered notification function\r | |
363 | //\r | |
364 | if (mTimerNotifyFunction != NULL) {\r | |
365 | //\r | |
5a702acd | 366 | // Compute time since last notification in 100 ns units (10 ^ -7)\r |
986d1dfb | 367 | //\r |
22fde64e | 368 | if (MainCounter > mPreviousMainCounter) {\r |
369 | //\r | |
370 | // Main counter does not overflow\r | |
371 | //\r | |
372 | Delta = MainCounter - mPreviousMainCounter;\r | |
373 | } else {\r | |
374 | //\r | |
375 | // Main counter overflows, first usb, then add\r | |
376 | //\r | |
377 | Delta = (mCounterMask - mPreviousMainCounter) + MainCounter;\r | |
378 | }\r | |
986d1dfb | 379 | TimerPeriod = DivU64x32 (\r |
380 | MultU64x32 (\r | |
22fde64e | 381 | Delta & mCounterMask,\r |
986d1dfb | 382 | mHpetGeneralCapabilities.Bits.CounterClockPeriod\r |
5a702acd | 383 | ),\r |
986d1dfb | 384 | 100000000\r |
385 | );\r | |
5a702acd | 386 | \r |
986d1dfb | 387 | //\r |
388 | // Call registered notification function passing in the time since the last\r | |
389 | // interrupt in 100 ns units.\r | |
5a702acd | 390 | //\r |
986d1dfb | 391 | mTimerNotifyFunction (TimerPeriod);\r |
392 | }\r | |
5a702acd | 393 | \r |
22fde64e | 394 | //\r |
395 | // Save main counter value\r | |
396 | //\r | |
397 | mPreviousMainCounter = MainCounter;\r | |
986d1dfb | 398 | }\r |
399 | \r | |
400 | /**\r | |
401 | This function registers the handler NotifyFunction so it is called every time\r | |
402 | the timer interrupt fires. It also passes the amount of time since the last\r | |
403 | handler call to the NotifyFunction. If NotifyFunction is NULL, then the\r | |
404 | handler is unregistered. If the handler is registered, then EFI_SUCCESS is\r | |
405 | returned. If the CPU does not support registering a timer interrupt handler,\r | |
406 | then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler\r | |
407 | when a handler is already registered, then EFI_ALREADY_STARTED is returned.\r | |
408 | If an attempt is made to unregister a handler when a handler is not registered,\r | |
409 | then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to\r | |
410 | register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR\r | |
411 | is returned.\r | |
412 | \r | |
413 | @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r | |
5a702acd LG |
414 | @param NotifyFunction The function to call when a timer interrupt fires.\r |
415 | This function executes at TPL_HIGH_LEVEL. The DXE\r | |
416 | Core will register a handler for the timer interrupt,\r | |
417 | so it can know how much time has passed. This\r | |
418 | information is used to signal timer based events.\r | |
986d1dfb | 419 | NULL will unregister the handler.\r |
420 | \r | |
421 | @retval EFI_SUCCESS The timer handler was registered.\r | |
422 | @retval EFI_UNSUPPORTED The platform does not support timer interrupts.\r | |
423 | @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already\r | |
424 | registered.\r | |
425 | @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not\r | |
426 | previously registered.\r | |
427 | @retval EFI_DEVICE_ERROR The timer handler could not be registered.\r | |
428 | \r | |
429 | **/\r | |
430 | EFI_STATUS\r | |
431 | EFIAPI\r | |
432 | TimerDriverRegisterHandler (\r | |
433 | IN EFI_TIMER_ARCH_PROTOCOL *This,\r | |
434 | IN EFI_TIMER_NOTIFY NotifyFunction\r | |
435 | )\r | |
436 | {\r | |
437 | //\r | |
438 | // Check for invalid parameters\r | |
439 | //\r | |
440 | if (NotifyFunction == NULL && mTimerNotifyFunction == NULL) {\r | |
441 | return EFI_INVALID_PARAMETER;\r | |
442 | }\r | |
443 | if (NotifyFunction != NULL && mTimerNotifyFunction != NULL) {\r | |
444 | return EFI_ALREADY_STARTED;\r | |
445 | }\r | |
446 | \r | |
447 | //\r | |
448 | // Cache the registered notification function\r | |
449 | //\r | |
450 | mTimerNotifyFunction = NotifyFunction;\r | |
451 | \r | |
452 | return EFI_SUCCESS;\r | |
453 | }\r | |
454 | \r | |
455 | /**\r | |
456 | This function adjusts the period of timer interrupts to the value specified\r | |
457 | by TimerPeriod. If the timer period is updated, then the selected timer\r | |
458 | period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If\r | |
459 | the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.\r | |
460 | If an error occurs while attempting to update the timer period, then the\r | |
461 | timer hardware will be put back in its state prior to this call, and\r | |
462 | EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt\r | |
463 | is disabled. This is not the same as disabling the CPU's interrupts.\r | |
464 | Instead, it must either turn off the timer hardware, or it must adjust the\r | |
465 | interrupt controller so that a CPU interrupt is not generated when the timer\r | |
466 | interrupt fires.\r | |
467 | \r | |
468 | @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r | |
469 | @param TimerPeriod The rate to program the timer interrupt in 100 nS units.\r | |
5a702acd LG |
470 | If the timer hardware is not programmable, then\r |
471 | EFI_UNSUPPORTED is returned. If the timer is programmable,\r | |
472 | then the timer period will be rounded up to the nearest\r | |
473 | timer period that is supported by the timer hardware.\r | |
474 | If TimerPeriod is set to 0, then the timer interrupts\r | |
986d1dfb | 475 | will be disabled.\r |
476 | \r | |
477 | @retval EFI_SUCCESS The timer period was changed.\r | |
478 | @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.\r | |
479 | @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.\r | |
480 | \r | |
481 | **/\r | |
482 | EFI_STATUS\r | |
483 | EFIAPI\r | |
484 | TimerDriverSetTimerPeriod (\r | |
485 | IN EFI_TIMER_ARCH_PROTOCOL *This,\r | |
486 | IN UINT64 TimerPeriod\r | |
487 | )\r | |
488 | {\r | |
70830df6 | 489 | EFI_TPL Tpl;\r |
9ff904b0 | 490 | UINT64 MainCounter;\r |
491 | UINT64 Delta;\r | |
492 | UINT64 CurrentComparator;\r | |
493 | HPET_TIMER_MSI_ROUTE_REGISTER HpetTimerMsiRoute;\r | |
70830df6 MK |
494 | \r |
495 | //\r | |
496 | // Disable interrupts\r | |
497 | //\r | |
498 | Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r | |
499 | \r | |
986d1dfb | 500 | //\r |
501 | // Disable HPET timer when adjusting the timer period\r | |
502 | //\r | |
503 | HpetEnable (FALSE);\r | |
5a702acd | 504 | \r |
986d1dfb | 505 | if (TimerPeriod == 0) {\r |
22fde64e | 506 | if (mTimerPeriod != 0) {\r |
507 | //\r | |
508 | // Check if there is possibly a pending interrupt\r | |
509 | //\r | |
510 | MainCounter = HpetRead (HPET_MAIN_COUNTER_OFFSET);\r | |
511 | if (MainCounter < mPreviousMainCounter) {\r | |
512 | Delta = (mCounterMask - mPreviousMainCounter) + MainCounter;\r | |
5a702acd | 513 | } else {\r |
22fde64e | 514 | Delta = MainCounter - mPreviousMainCounter;\r |
515 | }\r | |
516 | if ((Delta & mCounterMask) >= mTimerCount) {\r | |
517 | //\r | |
518 | // Interrupt still happens after disable HPET, wait to be processed\r | |
519 | // Wait until interrupt is processed and comparator is increased\r | |
520 | //\r | |
521 | CurrentComparator = HpetRead (HPET_TIMER_COMPARATOR_OFFSET + mTimerIndex * HPET_TIMER_STRIDE);\r | |
522 | while (CurrentComparator == mPreviousComparator) {\r | |
523 | CurrentComparator = HpetRead (HPET_TIMER_COMPARATOR_OFFSET + mTimerIndex * HPET_TIMER_STRIDE);\r | |
524 | CpuPause();\r | |
525 | }\r | |
526 | }\r | |
527 | }\r | |
528 | \r | |
986d1dfb | 529 | //\r |
530 | // If TimerPeriod is 0, then mask HPET Timer interrupts\r | |
531 | //\r | |
5a702acd | 532 | \r |
53b1dd10 | 533 | if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r |
986d1dfb | 534 | //\r |
535 | // Disable HPET MSI interrupt generation\r | |
536 | //\r | |
537 | mTimerConfiguration.Bits.MsiInterruptEnable = 0;\r | |
538 | } else {\r | |
539 | //\r | |
540 | // Disable I/O APIC Interrupt\r | |
541 | //\r | |
542 | IoApicEnableInterrupt (mTimerIrq, FALSE);\r | |
543 | }\r | |
5a702acd | 544 | \r |
986d1dfb | 545 | //\r |
5a702acd | 546 | // Disable HPET timer interrupt\r |
986d1dfb | 547 | //\r |
548 | mTimerConfiguration.Bits.InterruptEnable = 0;\r | |
549 | HpetWrite (HPET_TIMER_CONFIGURATION_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, mTimerConfiguration.Uint64);\r | |
550 | } else {\r | |
551 | //\r | |
5a702acd | 552 | // Convert TimerPeriod to femtoseconds and divide by the number if femtoseconds\r |
986d1dfb | 553 | // per tick of the HPET counter to determine the number of HPET counter ticks\r |
554 | // in TimerPeriod 100 ns units.\r | |
5a702acd | 555 | //\r |
22fde64e | 556 | mTimerCount = DivU64x32 (\r |
557 | MultU64x32 (TimerPeriod, 100000000),\r | |
558 | mHpetGeneralCapabilities.Bits.CounterClockPeriod\r | |
559 | );\r | |
986d1dfb | 560 | \r |
561 | //\r | |
562 | // Program the HPET Comparator with the number of ticks till the next interrupt\r | |
563 | //\r | |
22fde64e | 564 | MainCounter = HpetRead (HPET_MAIN_COUNTER_OFFSET);\r |
565 | if (MainCounter > mPreviousMainCounter) {\r | |
566 | Delta = MainCounter - mPreviousMainCounter;\r | |
5a702acd | 567 | } else {\r |
22fde64e | 568 | Delta = (mCounterMask - mPreviousMainCounter) + MainCounter;\r |
569 | }\r | |
570 | if ((Delta & mCounterMask) >= mTimerCount) {\r | |
571 | HpetWrite (HPET_TIMER_COMPARATOR_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, (MainCounter + 1) & mCounterMask);\r | |
5a702acd | 572 | } else {\r |
22fde64e | 573 | HpetWrite (HPET_TIMER_COMPARATOR_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, (mPreviousMainCounter + mTimerCount) & mCounterMask);\r |
986d1dfb | 574 | }\r |
5a702acd | 575 | \r |
986d1dfb | 576 | //\r |
577 | // Enable HPET Timer interrupt generation\r | |
578 | //\r | |
53b1dd10 | 579 | if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r |
9ff904b0 | 580 | //\r |
581 | // Program MSI Address and MSI Data values in the selected HPET Timer\r | |
582 | // Program HPET register with APIC ID of current BSP in case BSP has been switched\r | |
583 | //\r | |
584 | HpetTimerMsiRoute.Bits.Address = GetApicMsiAddress ();\r | |
585 | HpetTimerMsiRoute.Bits.Value = (UINT32)GetApicMsiValue (PcdGet8 (PcdHpetLocalApicVector), LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY, FALSE, FALSE);\r | |
586 | HpetWrite (HPET_TIMER_MSI_ROUTE_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, HpetTimerMsiRoute.Uint64);\r | |
986d1dfb | 587 | //\r |
588 | // Enable HPET MSI Interrupt\r | |
589 | //\r | |
590 | mTimerConfiguration.Bits.MsiInterruptEnable = 1;\r | |
591 | } else {\r | |
592 | //\r | |
593 | // Enable timer interrupt through I/O APIC\r | |
9ff904b0 | 594 | // Program IOAPIC register with APIC ID of current BSP in case BSP has been switched\r |
986d1dfb | 595 | //\r |
9ff904b0 | 596 | IoApicConfigureInterrupt (mTimerIrq, PcdGet8 (PcdHpetLocalApicVector), IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY, TRUE, FALSE);\r |
97be2801 | 597 | IoApicEnableInterrupt (mTimerIrq, TRUE);\r |
986d1dfb | 598 | }\r |
599 | \r | |
600 | //\r | |
601 | // Enable HPET Interrupt Generation\r | |
602 | //\r | |
603 | mTimerConfiguration.Bits.InterruptEnable = 1;\r | |
604 | HpetWrite (HPET_TIMER_CONFIGURATION_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, mTimerConfiguration.Uint64);\r | |
605 | }\r | |
5a702acd | 606 | \r |
986d1dfb | 607 | //\r |
608 | // Save the new timer period\r | |
609 | //\r | |
610 | mTimerPeriod = TimerPeriod;\r | |
611 | \r | |
612 | //\r | |
613 | // Enable the HPET counter once new timer period has been established\r | |
614 | // The HPET counter should run even if the HPET Timer interrupts are\r | |
615 | // disabled. This is used to account for time passed while the interrupt\r | |
616 | // is disabled.\r | |
617 | //\r | |
618 | HpetEnable (TRUE);\r | |
70830df6 MK |
619 | \r |
620 | //\r | |
621 | // Restore interrupts\r | |
622 | //\r | |
623 | gBS->RestoreTPL (Tpl);\r | |
624 | \r | |
986d1dfb | 625 | return EFI_SUCCESS;\r |
626 | }\r | |
627 | \r | |
628 | /**\r | |
629 | This function retrieves the period of timer interrupts in 100 ns units,\r | |
630 | returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod\r | |
631 | is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is\r | |
632 | returned, then the timer is currently disabled.\r | |
633 | \r | |
634 | @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r | |
635 | @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units.\r | |
636 | If 0 is returned, then the timer is currently disabled.\r | |
637 | \r | |
638 | @retval EFI_SUCCESS The timer period was returned in TimerPeriod.\r | |
639 | @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.\r | |
640 | \r | |
641 | **/\r | |
642 | EFI_STATUS\r | |
643 | EFIAPI\r | |
644 | TimerDriverGetTimerPeriod (\r | |
645 | IN EFI_TIMER_ARCH_PROTOCOL *This,\r | |
646 | OUT UINT64 *TimerPeriod\r | |
647 | )\r | |
648 | {\r | |
649 | if (TimerPeriod == NULL) {\r | |
650 | return EFI_INVALID_PARAMETER;\r | |
651 | }\r | |
652 | \r | |
653 | *TimerPeriod = mTimerPeriod;\r | |
654 | \r | |
655 | return EFI_SUCCESS;\r | |
656 | }\r | |
657 | \r | |
658 | /**\r | |
659 | This function generates a soft timer interrupt. If the platform does not support soft\r | |
660 | timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.\r | |
661 | If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()\r | |
662 | service, then a soft timer interrupt will be generated. If the timer interrupt is\r | |
663 | enabled when this service is called, then the registered handler will be invoked. The\r | |
664 | registered handler should not be able to distinguish a hardware-generated timer\r | |
665 | interrupt from a software-generated timer interrupt.\r | |
666 | \r | |
667 | @param This The EFI_TIMER_ARCH_PROTOCOL instance.\r | |
668 | \r | |
669 | @retval EFI_SUCCESS The soft timer interrupt was generated.\r | |
9349c2e6 | 670 | @retval EFI_UNSUPPORTED The platform does not support the generation of soft\r |
986d1dfb | 671 | timer interrupts.\r |
672 | \r | |
673 | **/\r | |
674 | EFI_STATUS\r | |
675 | EFIAPI\r | |
676 | TimerDriverGenerateSoftInterrupt (\r | |
677 | IN EFI_TIMER_ARCH_PROTOCOL *This\r | |
678 | )\r | |
679 | {\r | |
22fde64e | 680 | UINT64 MainCounter;\r |
986d1dfb | 681 | EFI_TPL Tpl;\r |
682 | UINT64 TimerPeriod;\r | |
22fde64e | 683 | UINT64 Delta;\r |
986d1dfb | 684 | \r |
685 | //\r | |
686 | // Disable interrupts\r | |
5a702acd | 687 | //\r |
986d1dfb | 688 | Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r |
5a702acd | 689 | \r |
986d1dfb | 690 | //\r |
22fde64e | 691 | // Capture main counter value\r |
986d1dfb | 692 | //\r |
22fde64e | 693 | MainCounter = HpetRead (HPET_MAIN_COUNTER_OFFSET);\r |
986d1dfb | 694 | \r |
695 | //\r | |
696 | // Check to see if there is a registered notification function\r | |
697 | //\r | |
698 | if (mTimerNotifyFunction != NULL) {\r | |
699 | //\r | |
5a702acd | 700 | // Compute time since last interrupt in 100 ns units (10 ^ -7)\r |
986d1dfb | 701 | //\r |
22fde64e | 702 | if (MainCounter > mPreviousMainCounter) {\r |
703 | //\r | |
704 | // Main counter does not overflow\r | |
705 | //\r | |
706 | Delta = MainCounter - mPreviousMainCounter;\r | |
707 | } else {\r | |
708 | //\r | |
709 | // Main counter overflows, first usb, then add\r | |
710 | //\r | |
711 | Delta = (mCounterMask - mPreviousMainCounter) + MainCounter;\r | |
712 | }\r | |
713 | \r | |
986d1dfb | 714 | TimerPeriod = DivU64x32 (\r |
715 | MultU64x32 (\r | |
22fde64e | 716 | Delta & mCounterMask,\r |
986d1dfb | 717 | mHpetGeneralCapabilities.Bits.CounterClockPeriod\r |
5a702acd | 718 | ),\r |
986d1dfb | 719 | 100000000\r |
720 | );\r | |
5a702acd | 721 | \r |
986d1dfb | 722 | //\r |
723 | // Call registered notification function passing in the time since the last\r | |
724 | // interrupt in 100 ns units.\r | |
5a702acd | 725 | //\r |
986d1dfb | 726 | mTimerNotifyFunction (TimerPeriod);\r |
727 | }\r | |
728 | \r | |
22fde64e | 729 | //\r |
730 | // Save main counter value\r | |
731 | //\r | |
732 | mPreviousMainCounter = MainCounter;\r | |
5a702acd | 733 | \r |
986d1dfb | 734 | //\r |
735 | // Restore interrupts\r | |
5a702acd | 736 | //\r |
986d1dfb | 737 | gBS->RestoreTPL (Tpl);\r |
5a702acd | 738 | \r |
986d1dfb | 739 | return EFI_SUCCESS;\r |
740 | }\r | |
741 | \r | |
742 | /**\r | |
743 | Initialize the Timer Architectural Protocol driver\r | |
744 | \r | |
745 | @param ImageHandle ImageHandle of the loaded driver\r | |
746 | @param SystemTable Pointer to the System Table\r | |
747 | \r | |
748 | @retval EFI_SUCCESS Timer Architectural Protocol created\r | |
749 | @retval EFI_OUT_OF_RESOURCES Not enough resources available to initialize driver.\r | |
619ad10f | 750 | @retval EFI_DEVICE_ERROR A device error occurred attempting to initialize the driver.\r |
986d1dfb | 751 | \r |
752 | **/\r | |
753 | EFI_STATUS\r | |
754 | EFIAPI\r | |
755 | TimerDriverInitialize (\r | |
756 | IN EFI_HANDLE ImageHandle,\r | |
757 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
758 | )\r | |
759 | {\r | |
760 | EFI_STATUS Status;\r | |
761 | UINTN TimerIndex;\r | |
762 | UINTN MsiTimerIndex;\r | |
763 | HPET_TIMER_MSI_ROUTE_REGISTER HpetTimerMsiRoute;\r | |
764 | \r | |
765 | DEBUG ((DEBUG_INFO, "Init HPET Timer Driver\n"));\r | |
766 | \r | |
767 | //\r | |
768 | // Make sure the Timer Architectural Protocol is not already installed in the system\r | |
769 | //\r | |
770 | ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiTimerArchProtocolGuid);\r | |
771 | \r | |
772 | //\r | |
773 | // Find the CPU architectural protocol.\r | |
774 | //\r | |
775 | Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **) &mCpu);\r | |
776 | ASSERT_EFI_ERROR (Status);\r | |
777 | \r | |
778 | //\r | |
779 | // Retrieve HPET Capabilities and Configuration Information\r | |
5a702acd | 780 | //\r |
986d1dfb | 781 | mHpetGeneralCapabilities.Uint64 = HpetRead (HPET_GENERAL_CAPABILITIES_ID_OFFSET);\r |
782 | mHpetGeneralConfiguration.Uint64 = HpetRead (HPET_GENERAL_CONFIGURATION_OFFSET);\r | |
5a702acd | 783 | \r |
986d1dfb | 784 | //\r |
5a702acd | 785 | // If Revision is not valid, then ASSERT() and unload the driver because the HPET\r |
986d1dfb | 786 | // device is not present.\r |
5a702acd | 787 | //\r |
986d1dfb | 788 | ASSERT (mHpetGeneralCapabilities.Uint64 != 0);\r |
789 | ASSERT (mHpetGeneralCapabilities.Uint64 != 0xFFFFFFFFFFFFFFFFULL);\r | |
790 | if (mHpetGeneralCapabilities.Uint64 == 0 || mHpetGeneralCapabilities.Uint64 == 0xFFFFFFFFFFFFFFFFULL) {\r | |
791 | DEBUG ((DEBUG_ERROR, "HPET device is not present. Unload HPET driver.\n"));\r | |
792 | return EFI_DEVICE_ERROR;\r | |
793 | }\r | |
794 | \r | |
795 | //\r | |
796 | // Force the HPET timer to be disabled while setting everything up\r | |
797 | //\r | |
798 | HpetEnable (FALSE);\r | |
799 | \r | |
800 | //\r | |
801 | // Dump HPET Configuration Information\r | |
5a702acd | 802 | //\r |
986d1dfb | 803 | DEBUG_CODE (\r |
22fde64e | 804 | DEBUG ((DEBUG_INFO, "HPET Base Address = 0x%08x\n", PcdGet32 (PcdHpetBaseAddress)));\r |
805 | DEBUG ((DEBUG_INFO, " HPET_GENERAL_CAPABILITIES_ID = 0x%016lx\n", mHpetGeneralCapabilities));\r | |
806 | DEBUG ((DEBUG_INFO, " HPET_GENERAL_CONFIGURATION = 0x%016lx\n", mHpetGeneralConfiguration.Uint64));\r | |
807 | DEBUG ((DEBUG_INFO, " HPET_GENERAL_INTERRUPT_STATUS = 0x%016lx\n", HpetRead (HPET_GENERAL_INTERRUPT_STATUS_OFFSET)));\r | |
808 | DEBUG ((DEBUG_INFO, " HPET_MAIN_COUNTER = 0x%016lx\n", HpetRead (HPET_MAIN_COUNTER_OFFSET)));\r | |
986d1dfb | 809 | DEBUG ((DEBUG_INFO, " HPET Main Counter Period = %d (fs)\n", mHpetGeneralCapabilities.Bits.CounterClockPeriod));\r |
810 | for (TimerIndex = 0; TimerIndex <= mHpetGeneralCapabilities.Bits.NumberOfTimers; TimerIndex++) {\r | |
22fde64e | 811 | DEBUG ((DEBUG_INFO, " HPET_TIMER%d_CONFIGURATION = 0x%016lx\n", TimerIndex, HpetRead (HPET_TIMER_CONFIGURATION_OFFSET + TimerIndex * HPET_TIMER_STRIDE)));\r |
812 | DEBUG ((DEBUG_INFO, " HPET_TIMER%d_COMPARATOR = 0x%016lx\n", TimerIndex, HpetRead (HPET_TIMER_COMPARATOR_OFFSET + TimerIndex * HPET_TIMER_STRIDE)));\r | |
813 | DEBUG ((DEBUG_INFO, " HPET_TIMER%d_MSI_ROUTE = 0x%016lx\n", TimerIndex, HpetRead (HPET_TIMER_MSI_ROUTE_OFFSET + TimerIndex * HPET_TIMER_STRIDE)));\r | |
986d1dfb | 814 | }\r |
815 | );\r | |
5a702acd | 816 | \r |
22fde64e | 817 | //\r |
818 | // Capture the current HPET main counter value.\r | |
819 | //\r | |
820 | mPreviousMainCounter = HpetRead (HPET_MAIN_COUNTER_OFFSET);\r | |
5a702acd | 821 | \r |
986d1dfb | 822 | //\r |
5a702acd | 823 | // Determine the interrupt mode to use for the HPET Timer.\r |
986d1dfb | 824 | // Look for MSI first, then unused PIC mode interrupt, then I/O APIC mode interrupt\r |
5a702acd | 825 | //\r |
986d1dfb | 826 | MsiTimerIndex = HPET_INVALID_TIMER_INDEX;\r |
827 | mTimerIndex = HPET_INVALID_TIMER_INDEX;\r | |
828 | for (TimerIndex = 0; TimerIndex <= mHpetGeneralCapabilities.Bits.NumberOfTimers; TimerIndex++) {\r | |
829 | //\r | |
830 | // Read the HPET Timer Capabilities and Configuration register\r | |
831 | //\r | |
832 | mTimerConfiguration.Uint64 = HpetRead (HPET_TIMER_CONFIGURATION_OFFSET + TimerIndex * HPET_TIMER_STRIDE);\r | |
5a702acd | 833 | \r |
986d1dfb | 834 | //\r |
5a702acd | 835 | // Check to see if this HPET Timer supports MSI\r |
986d1dfb | 836 | //\r |
53b1dd10 | 837 | if (mTimerConfiguration.Bits.MsiInterruptCapability != 0) {\r |
986d1dfb | 838 | //\r |
839 | // Save the index of the first HPET Timer that supports MSI interrupts\r | |
840 | //\r | |
841 | if (MsiTimerIndex == HPET_INVALID_TIMER_INDEX) {\r | |
842 | MsiTimerIndex = TimerIndex;\r | |
843 | }\r | |
844 | }\r | |
5a702acd | 845 | \r |
986d1dfb | 846 | //\r |
847 | // Check to see if this HPET Timer supports I/O APIC interrupts\r | |
848 | //\r | |
849 | if (mTimerConfiguration.Bits.InterruptRouteCapability != 0) {\r | |
850 | //\r | |
851 | // Save the index of the first HPET Timer that supports I/O APIC interrupts\r | |
852 | //\r | |
853 | if (mTimerIndex == HPET_INVALID_TIMER_INDEX) {\r | |
854 | mTimerIndex = TimerIndex;\r | |
855 | mTimerIrq = (UINT32)LowBitSet32 (mTimerConfiguration.Bits.InterruptRouteCapability);\r | |
856 | }\r | |
857 | }\r | |
858 | }\r | |
859 | \r | |
860 | if (FeaturePcdGet (PcdHpetMsiEnable) && MsiTimerIndex != HPET_INVALID_TIMER_INDEX) {\r | |
861 | //\r | |
862 | // Use MSI interrupt if supported\r | |
863 | //\r | |
864 | mTimerIndex = MsiTimerIndex;\r | |
865 | \r | |
866 | //\r | |
867 | // Program MSI Address and MSI Data values in the selected HPET Timer\r | |
868 | //\r | |
869 | HpetTimerMsiRoute.Bits.Address = GetApicMsiAddress ();\r | |
870 | HpetTimerMsiRoute.Bits.Value = (UINT32)GetApicMsiValue (PcdGet8 (PcdHpetLocalApicVector), LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY, FALSE, FALSE);\r | |
871 | HpetWrite (HPET_TIMER_MSI_ROUTE_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, HpetTimerMsiRoute.Uint64);\r | |
872 | \r | |
873 | //\r | |
874 | // Read the HPET Timer Capabilities and Configuration register and initialize for MSI mode\r | |
875 | // Clear LevelTriggeredInterrupt to use edge triggered interrupts when in MSI mode\r | |
876 | //\r | |
877 | mTimerConfiguration.Uint64 = HpetRead (HPET_TIMER_CONFIGURATION_OFFSET + mTimerIndex * HPET_TIMER_STRIDE);\r | |
878 | mTimerConfiguration.Bits.LevelTriggeredInterrupt = 0;\r | |
879 | } else {\r | |
880 | //\r | |
881 | // If no HPET timers support MSI or I/O APIC modes, then ASSERT() and unload the driver.\r | |
882 | //\r | |
883 | ASSERT (mTimerIndex != HPET_INVALID_TIMER_INDEX);\r | |
884 | if (mTimerIndex == HPET_INVALID_TIMER_INDEX) {\r | |
885 | DEBUG ((DEBUG_ERROR, "No HPET timers support MSI or I/O APIC mode. Unload HPET driver.\n"));\r | |
886 | return EFI_DEVICE_ERROR;\r | |
887 | }\r | |
5a702acd | 888 | \r |
986d1dfb | 889 | //\r |
890 | // Initialize I/O APIC entry for HPET Timer Interrupt\r | |
891 | // Fixed Delivery Mode, Level Triggered, Asserted Low\r | |
892 | //\r | |
893 | IoApicConfigureInterrupt (mTimerIrq, PcdGet8 (PcdHpetLocalApicVector), IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY, TRUE, FALSE);\r | |
894 | \r | |
895 | //\r | |
896 | // Read the HPET Timer Capabilities and Configuration register and initialize for I/O APIC mode\r | |
897 | // Clear MsiInterruptCapability to force rest of driver to use I/O APIC mode\r | |
898 | // Set LevelTriggeredInterrupt to use level triggered interrupts when in I/O APIC mode\r | |
899 | // Set InterruptRoute field based in mTimerIrq\r | |
900 | //\r | |
901 | mTimerConfiguration.Uint64 = HpetRead (HPET_TIMER_CONFIGURATION_OFFSET + mTimerIndex * HPET_TIMER_STRIDE);\r | |
986d1dfb | 902 | mTimerConfiguration.Bits.LevelTriggeredInterrupt = 1;\r |
903 | mTimerConfiguration.Bits.InterruptRoute = mTimerIrq;\r | |
904 | }\r | |
905 | \r | |
906 | //\r | |
907 | // Configure the selected HPET Timer with settings common to both MSI mode and I/O APIC mode\r | |
5a702acd LG |
908 | // Clear InterruptEnable to keep interrupts disabled until full init is complete\r |
909 | // Clear PeriodicInterruptEnable to use one-shot mode\r | |
910 | // Configure as a 32-bit counter\r | |
986d1dfb | 911 | //\r |
912 | mTimerConfiguration.Bits.InterruptEnable = 0;\r | |
913 | mTimerConfiguration.Bits.PeriodicInterruptEnable = 0;\r | |
22fde64e | 914 | mTimerConfiguration.Bits.CounterSizeEnable = 1;\r |
986d1dfb | 915 | HpetWrite (HPET_TIMER_CONFIGURATION_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, mTimerConfiguration.Uint64);\r |
5a702acd | 916 | \r |
22fde64e | 917 | //\r |
918 | // Read the HPET Timer Capabilities and Configuration register back again.\r | |
919 | // CounterSizeEnable will be read back as a 0 if it is a 32-bit only timer\r | |
920 | //\r | |
921 | mTimerConfiguration.Uint64 = HpetRead (HPET_TIMER_CONFIGURATION_OFFSET + mTimerIndex * HPET_TIMER_STRIDE);\r | |
922 | if ((mTimerConfiguration.Bits.CounterSizeEnable == 1) && (sizeof (UINTN) == sizeof (UINT64))) {\r | |
923 | DEBUG ((DEBUG_INFO, "Choose 64-bit HPET timer.\n"));\r | |
924 | //\r | |
925 | // 64-bit BIOS can use 64-bit HPET timer\r | |
926 | //\r | |
927 | mCounterMask = 0xffffffffffffffffULL;\r | |
928 | //\r | |
929 | // Set timer back to 64-bit\r | |
930 | //\r | |
931 | mTimerConfiguration.Bits.CounterSizeEnable = 0;\r | |
932 | HpetWrite (HPET_TIMER_CONFIGURATION_OFFSET + mTimerIndex * HPET_TIMER_STRIDE, mTimerConfiguration.Uint64);\r | |
933 | } else {\r | |
934 | DEBUG ((DEBUG_INFO, "Choose 32-bit HPET timer.\n"));\r | |
935 | mCounterMask = 0x00000000ffffffffULL;\r | |
936 | }\r | |
986d1dfb | 937 | \r |
938 | //\r | |
939 | // Install interrupt handler for selected HPET Timer\r | |
940 | //\r | |
941 | Status = mCpu->RegisterInterruptHandler (mCpu, PcdGet8 (PcdHpetLocalApicVector), TimerInterruptHandler);\r | |
942 | ASSERT_EFI_ERROR (Status);\r | |
943 | if (EFI_ERROR (Status)) {\r | |
944 | DEBUG ((DEBUG_ERROR, "Unable to register HPET interrupt with CPU Arch Protocol. Unload HPET driver.\n"));\r | |
945 | return EFI_DEVICE_ERROR;\r | |
946 | }\r | |
947 | \r | |
948 | //\r | |
949 | // Force the HPET Timer to be enabled at its default period\r | |
950 | //\r | |
951 | Status = TimerDriverSetTimerPeriod (&mTimer, PcdGet64 (PcdHpetDefaultTimerPeriod));\r | |
952 | ASSERT_EFI_ERROR (Status);\r | |
953 | if (EFI_ERROR (Status)) {\r | |
954 | DEBUG ((DEBUG_ERROR, "Unable to set HPET default timer rate. Unload HPET driver.\n"));\r | |
955 | return EFI_DEVICE_ERROR;\r | |
956 | }\r | |
957 | \r | |
958 | //\r | |
959 | // Show state of enabled HPET timer\r | |
960 | //\r | |
961 | DEBUG_CODE (\r | |
53b1dd10 | 962 | if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r |
986d1dfb | 963 | DEBUG ((DEBUG_INFO, "HPET Interrupt Mode MSI\n"));\r |
964 | } else {\r | |
965 | DEBUG ((DEBUG_INFO, "HPET Interrupt Mode I/O APIC\n"));\r | |
22fde64e | 966 | DEBUG ((DEBUG_INFO, "HPET I/O APIC IRQ = 0x%02x\n", mTimerIrq));\r |
5a702acd | 967 | }\r |
22fde64e | 968 | DEBUG ((DEBUG_INFO, "HPET Interrupt Vector = 0x%02x\n", PcdGet8 (PcdHpetLocalApicVector)));\r |
969 | DEBUG ((DEBUG_INFO, "HPET Counter Mask = 0x%016lx\n", mCounterMask));\r | |
970 | DEBUG ((DEBUG_INFO, "HPET Timer Period = %d\n", mTimerPeriod));\r | |
971 | DEBUG ((DEBUG_INFO, "HPET Timer Count = 0x%016lx\n", mTimerCount));\r | |
972 | DEBUG ((DEBUG_INFO, "HPET_TIMER%d_CONFIGURATION = 0x%016lx\n", mTimerIndex, HpetRead (HPET_TIMER_CONFIGURATION_OFFSET + mTimerIndex * HPET_TIMER_STRIDE)));\r | |
973 | DEBUG ((DEBUG_INFO, "HPET_TIMER%d_COMPARATOR = 0x%016lx\n", mTimerIndex, HpetRead (HPET_TIMER_COMPARATOR_OFFSET + mTimerIndex * HPET_TIMER_STRIDE)));\r | |
974 | DEBUG ((DEBUG_INFO, "HPET_TIMER%d_MSI_ROUTE = 0x%016lx\n", mTimerIndex, HpetRead (HPET_TIMER_MSI_ROUTE_OFFSET + mTimerIndex * HPET_TIMER_STRIDE)));\r | |
986d1dfb | 975 | \r |
976 | //\r | |
977 | // Wait for a few timer interrupts to fire before continuing\r | |
5a702acd | 978 | //\r |
986d1dfb | 979 | while (mNumTicks < 10);\r |
980 | );\r | |
5a702acd | 981 | \r |
986d1dfb | 982 | //\r |
983 | // Install the Timer Architectural Protocol onto a new handle\r | |
984 | //\r | |
985 | Status = gBS->InstallMultipleProtocolInterfaces (\r | |
986 | &mTimerHandle,\r | |
987 | &gEfiTimerArchProtocolGuid, &mTimer,\r | |
988 | NULL\r | |
989 | );\r | |
990 | ASSERT_EFI_ERROR (Status);\r | |
991 | \r | |
992 | return Status;\r | |
993 | }\r |