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986d1dfb | 1 | /** @file\r |
2 | Public include file for I/O APIC library.\r | |
3 | \r | |
4 | I/O APIC library assumes I/O APIC is enabled. It does not\r | |
5 | handles cases where I/O APIC is disabled.\r | |
6 | \r | |
7 | Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r | |
8 | This program and the accompanying materials\r | |
9 | are licensed and made available under the terms and conditions of the BSD License\r | |
10 | which accompanies this distribution. The full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
12 | \r | |
13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
15 | \r | |
16 | **/\r | |
8e22eab8 ED |
17 | #ifndef __IO_APIC_LIB_H__\r |
18 | #define __IO_APIC_LIB_H__\r | |
986d1dfb | 19 | \r |
20 | /**\r | |
21 | Read a 32-bit I/O APIC register.\r | |
22 | \r | |
23 | If Index is >= 0x100, then ASSERT().\r | |
24 | \r | |
25 | @param Index Specifies the I/O APIC register to read.\r | |
26 | \r | |
27 | @return The 32-bit value read from the I/O APIC register specified by Index.\r | |
28 | **/\r | |
29 | UINT32\r | |
30 | EFIAPI\r | |
31 | IoApicRead (\r | |
32 | IN UINTN Index\r | |
33 | );\r | |
34 | \r | |
35 | /**\r | |
36 | Write a 32-bit I/O APIC register.\r | |
37 | \r | |
38 | If Index is >= 0x100, then ASSERT().\r | |
39 | \r | |
40 | @param Index Specifies the I/O APIC register to write.\r | |
41 | @param Value Specifies the value to write to the I/O APIC register specified by Index.\r | |
42 | \r | |
43 | @return The 32-bit value written to I/O APIC register specified by Index.\r | |
44 | **/\r | |
45 | UINT32\r | |
46 | EFIAPI\r | |
47 | IoApicWrite (\r | |
48 | IN UINTN Index,\r | |
49 | IN UINT32 Value\r | |
50 | );\r | |
51 | \r | |
52 | /**\r | |
53 | Set the interrupt mask of an I/O APIC interrupt.\r | |
54 | \r | |
55 | If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). \r | |
56 | \r | |
57 | @param Irq Specifies the I/O APIC interrupt to enable or disable.\r | |
58 | @param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq.\r | |
59 | If FALSE, then disable the I/O APIC interrupt specified by Irq.\r | |
60 | **/\r | |
61 | VOID\r | |
62 | EFIAPI\r | |
63 | IoApicEnableInterrupt (\r | |
64 | IN UINTN Irq,\r | |
65 | IN BOOLEAN Enable\r | |
66 | );\r | |
67 | \r | |
68 | /**\r | |
69 | Configures an I/O APIC interrupt.\r | |
70 | \r | |
71 | Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical\r | |
72 | mode to the Local APIC of the currntly executing CPU. The default state of the \r | |
73 | entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must\r | |
74 | be used to enable(unmask) the I/O APIC Interrupt.\r | |
75 | \r | |
76 | If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). \r | |
77 | If Vector >= 0x100, then ASSERT().\r | |
78 | If DeliveryMode is not supported, then ASSERT().\r | |
79 | \r | |
80 | @param Irq Specifies the I/O APIC interrupt to initialize.\r | |
81 | @param Vector The 8-bit interrupt vector associated with the I/O APIC\r | |
82 | Interrupt. Must be in the range 0x10..0xFE.\r | |
83 | @param DeliveryMode A 3-bit value that specifies how the recept of the I/O APIC\r | |
84 | interrupt is handled. The only supported values are:\r | |
85 | 0: IO_APIC_DELIVERY_MODE_FIXED\r | |
86 | 1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r | |
87 | 2: IO_APIC_DELIVERY_MODE_SMI\r | |
88 | 4: IO_APIC_DELIVERY_MODE_NMI\r | |
89 | 5: IO_APIC_DELIVERY_MODE_INIT\r | |
90 | 7: IO_APIC_DELIVERY_MODE_EXTINT\r | |
91 | @param LevelTriggered TRUE specifies a level triggered interrupt.\r | |
92 | FALSE specifies an edge triggered interrupt.\r | |
93 | @param AssertionLevel TRUE specified an active high interrupt.\r | |
94 | FALSE specifies an active low interrupt.\r | |
95 | **/\r | |
96 | VOID\r | |
97 | EFIAPI\r | |
98 | IoApicConfigureInterrupt (\r | |
99 | IN UINTN Irq,\r | |
100 | IN UINTN Vector,\r | |
101 | IN UINTN DeliveryMode,\r | |
102 | IN BOOLEAN LevelTriggered,\r | |
103 | IN BOOLEAN AssertionLevel\r | |
104 | );\r | |
8e22eab8 | 105 | #endif\r |