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986d1dfb | 1 | /** @file \r |
2 | I/O APIC library.\r | |
3 | \r | |
4 | I/O APIC library assumes I/O APIC is enabled. It does not\r | |
5 | handles cases where I/O APIC is disabled.\r | |
6 | \r | |
7 | Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r | |
8 | This program and the accompanying materials\r | |
9 | are licensed and made available under the terms and conditions of the BSD License\r | |
10 | which accompanies this distribution. The full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
12 | \r | |
13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
15 | \r | |
16 | **/\r | |
17 | \r | |
18 | #include <Base.h>\r | |
19 | \r | |
20 | #include <Library/IoApicLib.h>\r | |
21 | \r | |
22 | #include <Library/DebugLib.h>\r | |
23 | #include <Library/PcdLib.h>\r | |
24 | #include <Library/IoLib.h>\r | |
25 | #include <Library/LocalApicLib.h>\r | |
26 | \r | |
27 | #include <Register/IoApic.h>\r | |
28 | \r | |
29 | /**\r | |
30 | Read a 32-bit I/O APIC register.\r | |
31 | \r | |
32 | If Index is >= 0x100, then ASSERT().\r | |
33 | \r | |
34 | @param Index Specifies the I/O APIC register to read.\r | |
35 | \r | |
36 | @return The 32-bit value read from the I/O APIC register specified by Index.\r | |
37 | **/\r | |
38 | UINT32\r | |
39 | EFIAPI\r | |
40 | IoApicRead (\r | |
41 | IN UINTN Index\r | |
42 | )\r | |
43 | {\r | |
44 | ASSERT (Index < 0x100);\r | |
45 | MmioWrite8 (PcdGet32 (PcdIoApicBaseAddress) + IOAPIC_INDEX_OFFSET, (UINT8)Index);\r | |
46 | return MmioRead32 (PcdGet32 (PcdIoApicBaseAddress) + IOAPIC_DATA_OFFSET);\r | |
47 | }\r | |
48 | \r | |
49 | /**\r | |
50 | Write a 32-bit I/O APIC register.\r | |
51 | \r | |
52 | If Index is >= 0x100, then ASSERT().\r | |
53 | \r | |
54 | @param Index Specifies the I/O APIC register to write.\r | |
55 | @param Value Specifies the value to write to the I/O APIC register specified by Index.\r | |
56 | \r | |
57 | @return The 32-bit value written to I/O APIC register specified by Index.\r | |
58 | **/\r | |
59 | UINT32\r | |
60 | EFIAPI\r | |
61 | IoApicWrite (\r | |
62 | IN UINTN Index,\r | |
63 | IN UINT32 Value\r | |
64 | )\r | |
65 | {\r | |
66 | ASSERT (Index < 0x100);\r | |
67 | MmioWrite8 (PcdGet32 (PcdIoApicBaseAddress) + IOAPIC_INDEX_OFFSET, (UINT8)Index);\r | |
68 | return MmioWrite32 (PcdGet32 (PcdIoApicBaseAddress) + IOAPIC_DATA_OFFSET, Value);\r | |
69 | }\r | |
70 | \r | |
71 | /**\r | |
72 | Set the interrupt mask of an I/O APIC interrupt.\r | |
73 | \r | |
74 | If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). \r | |
75 | \r | |
76 | @param Irq Specifies the I/O APIC interrupt to enable or disable.\r | |
77 | @param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq.\r | |
78 | If FALSE, then disable the I/O APIC interrupt specified by Irq.\r | |
79 | **/\r | |
80 | VOID\r | |
81 | EFIAPI\r | |
82 | IoApicEnableInterrupt (\r | |
83 | IN UINTN Irq,\r | |
84 | IN BOOLEAN Enable\r | |
85 | )\r | |
86 | {\r | |
87 | IO_APIC_VERSION_REGISTER Version;\r | |
88 | IO_APIC_REDIRECTION_TABLE_ENTRY Entry;\r | |
89 | \r | |
90 | Version.Uint32 = IoApicRead (IO_APIC_VERSION_REGISTER_INDEX);\r | |
91 | ASSERT (Version.Bits.MaximumRedirectionEntry < 0xF0);\r | |
92 | ASSERT (Irq <= Version.Bits.MaximumRedirectionEntry);\r | |
93 | \r | |
94 | Entry.Uint32.Low = IoApicRead (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2);\r | |
95 | Entry.Bits.Mask = Enable ? 0 : 1;\r | |
96 | IoApicWrite (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2, Entry.Uint32.Low);\r | |
97 | }\r | |
98 | \r | |
99 | /**\r | |
100 | Configures an I/O APIC interrupt.\r | |
101 | \r | |
102 | Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical\r | |
103 | mode to the Local APIC of the currntly executing CPU. The default state of the \r | |
104 | entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must\r | |
105 | be used to enable(unmask) the I/O APIC Interrupt.\r | |
106 | \r | |
107 | If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT(). \r | |
108 | If Vector >= 0x100, then ASSERT().\r | |
109 | If DeliveryMode is not supported, then ASSERT().\r | |
110 | \r | |
111 | @param Irq Specifies the I/O APIC interrupt to initialize.\r | |
112 | @param Vector The 8-bit interrupt vector associated with the I/O APIC\r | |
113 | Interrupt. Must be in the range 0x10..0xFE.\r | |
114 | @param DeliveryMode A 3-bit value that specifies how the recept of the I/O APIC\r | |
115 | interrupt is handled. The only supported values are:\r | |
116 | 0: IO_APIC_DELIVERY_MODE_FIXED\r | |
117 | 1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r | |
118 | 2: IO_APIC_DELIVERY_MODE_SMI\r | |
119 | 4: IO_APIC_DELIVERY_MODE_NMI\r | |
120 | 5: IO_APIC_DELIVERY_MODE_INIT\r | |
121 | 7: IO_APIC_DELIVERY_MODE_EXTINT\r | |
122 | @param LevelTriggered TRUE specifies a level triggered interrupt.\r | |
123 | FALSE specifies an edge triggered interrupt.\r | |
124 | @param AssertionLevel TRUE specified an active high interrupt.\r | |
125 | FALSE specifies an active low interrupt.\r | |
126 | **/\r | |
127 | VOID\r | |
128 | EFIAPI\r | |
129 | IoApicConfigureInterrupt (\r | |
130 | IN UINTN Irq,\r | |
131 | IN UINTN Vector,\r | |
132 | IN UINTN DeliveryMode,\r | |
133 | IN BOOLEAN LevelTriggered,\r | |
134 | IN BOOLEAN AssertionLevel\r | |
135 | )\r | |
136 | {\r | |
137 | IO_APIC_VERSION_REGISTER Version;\r | |
138 | IO_APIC_REDIRECTION_TABLE_ENTRY Entry;\r | |
139 | \r | |
140 | Version.Uint32 = IoApicRead (IO_APIC_VERSION_REGISTER_INDEX);\r | |
141 | ASSERT (Version.Bits.MaximumRedirectionEntry < 0xF0);\r | |
142 | ASSERT (Irq <= Version.Bits.MaximumRedirectionEntry);\r | |
143 | ASSERT (Vector <= 0xFF);\r | |
144 | ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r | |
145 | \r | |
146 | Entry.Uint32.Low = IoApicRead (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2);\r | |
147 | Entry.Bits.Vector = (UINT8)Vector;\r | |
148 | Entry.Bits.DeliveryMode = (UINT32)DeliveryMode;\r | |
149 | Entry.Bits.DestinationMode = 0; \r | |
150 | Entry.Bits.Polarity = AssertionLevel ? 0 : 1;\r | |
151 | Entry.Bits.TriggerMode = LevelTriggered ? 1 : 0;\r | |
152 | Entry.Bits.Mask = 1;\r | |
153 | IoApicWrite (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2, Entry.Uint32.Low);\r | |
154 | \r | |
155 | Entry.Uint32.High = IoApicRead (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2 + 1);\r | |
156 | Entry.Bits.DestinationID = GetApicId ();\r | |
157 | IoApicWrite (IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX + Irq * 2 + 1, Entry.Uint32.High);\r | |
158 | }\r |