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7b202cb0 | 1 | ## @file\r |
31ed75a9 | 2 | # Public definitions for PcAtChipset package.\r |
3 | #\r | |
4 | # This package is designed to public interfaces and implementation which follows\r | |
5 | # PcAt defacto standard.\r | |
6 | #\r | |
1e5fff63 | 7 | # Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r |
31ed75a9 | 8 | #\r |
95d48e82 | 9 | # This program and the accompanying materials\r |
31ed75a9 | 10 | # are licensed and made available under the terms and conditions of the BSD License\r |
11 | # which accompanies this distribution. The full text of the license may be found at\r | |
12 | # http://opensource.org/licenses/bsd-license.php\r | |
13 | #\r | |
14 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
15 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
16 | #\r | |
7b202cb0 | 17 | ##\r |
31ed75a9 | 18 | \r |
19 | [Defines]\r | |
20 | DEC_SPECIFICATION = 0x00010005\r | |
21 | PACKAGE_NAME = PcAtChipsetPkg\r | |
b414ac4d | 22 | PACKAGE_UNI_FILE = PcAtChipsetPkg.uni\r |
31ed75a9 | 23 | PACKAGE_GUID = B728689A-52D3-4b8c-AE89-2CE5514CC6DC\r |
9325f684 | 24 | PACKAGE_VERSION = 0.3\r |
31ed75a9 | 25 | \r |
986d1dfb | 26 | [Includes]\r |
27 | Include\r | |
28 | \r | |
29 | [LibraryClasses]\r | |
30 | ## @libraryclass Provides functions to manage I/O APIC Redirection Table Entries.\r | |
31 | #\r | |
32 | IoApicLib|Include/Library/IoApicLib.h\r | |
33 | \r | |
53705ed1 | 34 | [Guids]\r |
35 | gPcAtChipsetPkgTokenSpaceGuid = { 0x326ae723, 0xae32, 0x4589, { 0x98, 0xb8, 0xca, 0xc2, 0x3c, 0xdc, 0xc1, 0xb1 } }\r | |
36 | \r | |
f5f47471 RN |
37 | #\r |
38 | # [Error.gPcAtChipsetPkgTokenSpaceGuid]\r | |
39 | # 0x80000001 | Invalid value provided.\r | |
40 | #\r | |
41 | \r | |
986d1dfb | 42 | [PcdsFeatureFlag]\r |
b414ac4d QS |
43 | ## Indicates the HPET Timer will be configured to use MSI interrupts if the HPET timer supports them, or use I/O APIC interrupts.<BR><BR>\r |
44 | # TRUE - Configures the HPET Timer to use MSI interrupts if the HPET Timer supports them.<BR>\r | |
45 | # FALSE - Configures the HPET Timer to use I/O APIC interrupts.<BR>\r | |
46 | # @Prompt Configure HPET to use MSI.\r | |
986d1dfb | 47 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetMsiEnable|TRUE|BOOLEAN|0x00001000\r |
b414ac4d | 48 | \r |
856f592c | 49 | [PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule]\r |
b414ac4d | 50 | ## Pcd8259LegacyModeMask defines the default mask value for platform. This value is determined<BR><BR>\r |
31ed75a9 | 51 | # 1) If platform only support pure UEFI, value should be set to 0xFFFF or 0xFFFE;\r |
b414ac4d QS |
52 | # Because only clock interrupt is allowed in legacy mode in pure UEFI platform.<BR>\r |
53 | # 2) If platform install CSM and use thunk module:<BR>\r | |
31ed75a9 | 54 | # a) If thunk call provided by CSM binary requires some legacy interrupt support, the corresponding bit \r |
b414ac4d QS |
55 | # should be opened as 0.<BR>\r |
56 | # For example, if keyboard interfaces provided CSM binary use legacy keyboard interrupt in 8259 bit 1, then\r | |
57 | # the value should be set to 0xFFFC.<BR>\r | |
31ed75a9 | 58 | # b) If all thunk call provied by CSM binary do not require legacy interrupt support, value should be set\r |
b414ac4d | 59 | # to 0xFFFF or 0xFFFE.<BR>\r |
31ed75a9 | 60 | #\r |
31ed75a9 | 61 | # The default value of legacy mode mask could be changed by EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely\r |
62 | # need change it except some special cases such as when initializing the CSM binary, it should be set to 0xFFFF to \r | |
b414ac4d QS |
63 | # mask all legacy interrupt. Please restore the original legacy mask value if changing is made for these special case.<BR>\r |
64 | # @Prompt 8259 Legacy Mode mask.\r | |
1f44ee10 | 65 | gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x00000001\r |
e356f999 | 66 | \r |
67 | ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy mode's interrrupt controller.\r | |
b414ac4d QS |
68 | # For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.\r |
69 | # @Prompt 8259 Legacy Mode edge level.\r | |
1f44ee10 | 70 | gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x00000002\r |
e8bce4b4 | 71 | \r |
b414ac4d QS |
72 | ## Indicates if we need enable IsaAcpiCom1 device.<BR><BR>\r |
73 | # TRUE - Enables IsaAcpiCom1 device.<BR>\r | |
74 | # FALSE - Doesn't enable IsaAcpiCom1 device.<BR>\r | |
75 | # @Prompt Enable IsaAcpiCom1 device.\r | |
e8bce4b4 RN |
76 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiCom1Enable|TRUE|BOOLEAN|0x00000003\r |
77 | \r | |
b414ac4d QS |
78 | ## Indicates if we need enable IsaAcpiCom2 device.<BR><BR>\r |
79 | # TRUE - Enables IsaAcpiCom2 device.<BR>\r | |
80 | # FALSE - Doesn't enable IsaAcpiCom2 device.<BR>\r | |
81 | # @Prompt Enable IsaAcpiCom12 device.\r | |
e8bce4b4 RN |
82 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiCom2Enable|TRUE|BOOLEAN|0x00000004\r |
83 | \r | |
b414ac4d QS |
84 | ## Indicates if we need enable IsaAcpiPs2Keyboard device.<BR><BR>\r |
85 | # TRUE - Enables IsaAcpiPs2Keyboard device.<BR>\r | |
86 | # FALSE - Doesn't enable IsaAcpiPs2Keyboard device.<BR>\r | |
87 | # @Prompt Enable IsaAcpiPs2Keyboard device.\r | |
e8bce4b4 RN |
88 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiPs2KeyboardEnable|TRUE|BOOLEAN|0x00000005\r |
89 | \r | |
b414ac4d QS |
90 | ## Indicates if we need enable IsaAcpiPs2Mouse device.<BR><BR>\r |
91 | # TRUE - Enables IsaAcpiPs2Mouse device.<BR>\r | |
92 | # FALSE - Doesn't enable IsaAcpiPs2Mouse device.<BR>\r | |
93 | # @Prompt Enable IsaAcpiPs2Mouse device.\r | |
e8bce4b4 RN |
94 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiPs2MouseEnable|TRUE|BOOLEAN|0x00000006\r |
95 | \r | |
b414ac4d QS |
96 | ## Indicates if we need enable IsaAcpiFloppyA device.<BR><BR>\r |
97 | # TRUE - Enables IsaAcpiFloppyA device.<BR>\r | |
98 | # FALSE - Doesn't enable IsaAcpiFloppyA device.<BR>\r | |
99 | # @Prompt Enable IsaAcpiFloppyA device.\r | |
e8bce4b4 RN |
100 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiFloppyAEnable|TRUE|BOOLEAN|0x00000007\r |
101 | \r | |
b414ac4d QS |
102 | ## Indicates if we need enable IsaAcpiFloppyB device.<BR><BR>\r |
103 | # TRUE - Enables IsaAcpiFloppyB device.<BR>\r | |
104 | # FALSE - Doesn't enable IsaAcpiFloppyB device.<BR>\r | |
105 | # @Prompt Enable IsaAcpiFloppyB device.\r | |
e8bce4b4 | 106 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiFloppyBEnable|TRUE|BOOLEAN|0x00000008\r |
986d1dfb | 107 | \r |
108 | ## This PCD specifies the base address of the HPET timer.\r | |
b414ac4d | 109 | # @Prompt HPET base address.\r |
986d1dfb | 110 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000|UINT32|0x00000009\r |
111 | \r | |
112 | ## This PCD specifies the Local APIC Interrupt Vector for the HPET Timer.\r | |
b414ac4d | 113 | # @Prompt HPET local APIC vector.\r |
986d1dfb | 114 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetLocalApicVector|0x40|UINT8|0x0000000A\r |
115 | \r | |
116 | ## This PCD specifies the defaut period of the HPET Timer in 100 ns units.\r | |
117 | # The default value of 100000 100 ns units is the same as 10 ms.\r | |
b414ac4d | 118 | # @Prompt Default period of HPET timer.\r |
986d1dfb | 119 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetDefaultTimerPeriod|100000|UINT64|0x0000000B\r |
120 | \r | |
b414ac4d QS |
121 | ## This PCD specifies the base address of the IO APIC.\r |
122 | # @Prompt IO APIC base address.\r | |
986d1dfb | 123 | gPcAtChipsetPkgTokenSpaceGuid.PcdIoApicBaseAddress|0xFEC00000|UINT32|0x0000000C\r |
1e5fff63 EL |
124 | \r |
125 | ## This PCD specifies the minimal valid year in RTC.\r | |
126 | # @Prompt Minimal valid year in RTC.\r | |
127 | gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|1998|UINT16|0x0000000D\r | |
128 | \r | |
129 | ## This PCD specifies the maximal valid year in RTC.\r | |
130 | # @Prompt Maximal valid year in RTC.\r | |
f5f47471 | 131 | # @Expression 0x80000001 | gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear < gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear + 100\r |
fe320967 | 132 | gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2097|UINT16|0x0000000E\r |
bae5fa3b | 133 | \r |
83d1ffb9 LG |
134 | [PcdsFixedAtBuild, PcdsPatchableInModule]\r |
135 | ## Defines the ACPI register set base address.\r | |
136 | # The invalid 0xFFFF is as its default value. It must be configured to the real value. \r | |
137 | # @Prompt ACPI Timer IO Port Address\r | |
138 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |0xFFFF|UINT16|0x00000010\r | |
139 | \r | |
140 | ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r | |
141 | # @Prompt ACPI Hardware PCI Bus Number\r | |
142 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00| UINT8|0x00000011\r | |
143 | \r | |
144 | ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r | |
145 | # The invalid 0xFF is as its default value. It must be configured to the real value. \r | |
146 | # @Prompt ACPI Hardware PCI Device Number\r | |
147 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0xFF| UINT8|0x00000012\r | |
148 | \r | |
149 | ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r | |
150 | # The invalid 0xFF is as its default value. It must be configured to the real value. \r | |
151 | # @Prompt ACPI Hardware PCI Function Number\r | |
152 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0xFF| UINT8|0x00000013\r | |
153 | \r | |
154 | ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.\r | |
155 | # The invalid 0xFFFF is as its default value. It must be configured to the real value. \r | |
156 | # @Prompt ACPI Hardware PCI Register Offset\r | |
157 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0xFFFF|UINT16|0x00000014\r | |
158 | \r | |
159 | ## Defines the bit mask that must be set to enable the APIC hardware register BAR.\r | |
160 | # @Prompt ACPI Hardware PCI Bar Enable BitMask\r | |
161 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x00| UINT8|0x00000015\r | |
162 | \r | |
163 | ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.\r | |
164 | # The invalid 0xFFFF is as its default value. It must be configured to the real value. \r | |
165 | # @Prompt ACPI Hardware PCI Bar Register Offset\r | |
166 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0xFFFF|UINT16|0x00000016\r | |
167 | \r | |
168 | ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.\r | |
169 | # @Prompt Offset to 32-bit Timer register in ACPI BAR\r | |
170 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008|UINT16|0x00000017\r | |
b414ac4d | 171 | \r |
9ff926d6 LG |
172 | ## Defines the bit mask to retrieve ACPI IO Port Base Address\r |
173 | # @Prompt ACPI IO Port Base Address Mask\r | |
174 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFE|UINT16|0x00000018\r | |
175 | \r | |
a38b89c7 LG |
176 | ## Reset Control Register address in I/O space.\r |
177 | # @Prompt Reset Control Register address\r | |
178 | gPcAtChipsetPkgTokenSpaceGuid.PcdResetControlRegister|0x64|UINT64|0x00000019\r | |
179 | \r | |
180 | ## 8bit Reset Control Register value for cold reset.\r | |
181 | # @Prompt Reset Control Register value for cold reset\r | |
182 | gPcAtChipsetPkgTokenSpaceGuid.PcdResetControlValueColdReset|0xFE|UINT8|0x0000001A\r | |
183 | \r | |
b414ac4d | 184 | [UserExtensions.TianoCore."ExtraFiles"]\r |
fe320967 | 185 | PcAtChipsetPkgExtra.uni\r |