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c06ad33e | 1 | /** @file\r |
2 | A Timer Library implementation which uses the Time Stamp Counter in the processor.\r | |
3 | \r | |
4 | For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]);\r | |
5 | for Intel Core Solo and Intel Core Duo processors (family [06H], model [0EH]);\r | |
6 | for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors (family [06H], model [0FH]);\r | |
7 | for Intel Core 2 and Intel Xeon processors (family [06H], display_model [17H]);\r | |
8 | for Intel Atom processors (family [06H], display_model [1CH]):\r | |
9 | the time-stamp counter increments at a constant rate.\r | |
10 | That rate may be set by the maximum core-clock to bus-clock ratio of the processor or may be set by\r | |
11 | the maximum resolved frequency at which the processor is booted. The maximum resolved frequency may\r | |
12 | differ from the maximum qualified frequency of the processor.\r | |
13 | \r | |
14 | The specific processor configuration determines the behavior. Constant TSC behavior ensures that the\r | |
15 | duration of each clock tick is uniform and supports the use of the TSC as a wall clock timer even if\r | |
16 | the processor core changes frequency. This is the architectural behavior moving forward.\r | |
17 | \r | |
24cd83a7 | 18 | A Processor's support for invariant TSC is indicated by CPUID.0x80000007.EDX[8].\r |
c06ad33e | 19 | \r |
92ea1df8 | 20 | Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r |
c06ad33e | 21 | This program and the accompanying materials\r |
22 | are licensed and made available under the terms and conditions of the BSD License\r | |
23 | which accompanies this distribution. The full text of the license may be found at\r | |
24 | http://opensource.org/licenses/bsd-license.php\r | |
25 | \r | |
26 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
27 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
28 | \r | |
29 | **/\r | |
30 | \r | |
31 | #include <Base.h>\r | |
32 | #include <Ich/GenericIch.h>\r | |
33 | \r | |
34 | #include <Library/TimerLib.h>\r | |
35 | #include <Library/BaseLib.h>\r | |
36 | #include <Library/IoLib.h>\r | |
37 | #include <Library/PciLib.h>\r | |
38 | #include <Library/PcdLib.h>\r | |
39 | \r | |
40 | STATIC UINT64 mTscFrequency;\r | |
41 | \r | |
c06ad33e | 42 | /** The constructor function determines the actual TSC frequency.\r |
43 | \r | |
44 | The TSC counting frequency is determined by comparing how far it counts\r | |
45 | during a 1ms period as determined by the ACPI timer. The ACPI timer is\r | |
46 | used because it counts at a known frequency.\r | |
47 | If ACPI I/O space not enabled, this function will enable it. Then the\r | |
48 | TSC is sampled, followed by waiting for 3579 clocks of the ACPI timer, or 1ms.\r | |
49 | The TSC is then sampled again. The difference multiplied by 1000 is the TSC\r | |
50 | frequency. There will be a small error because of the overhead of reading\r | |
51 | the ACPI timer. An attempt is made to determine and compensate for this error.\r | |
52 | This function will always return RETURN_SUCCESS.\r | |
53 | \r | |
54 | @retval RETURN_SUCCESS The constructor always returns RETURN_SUCCESS.\r | |
55 | \r | |
56 | **/\r | |
57 | RETURN_STATUS\r | |
58 | EFIAPI\r | |
59 | TscTimerLibConstructor (\r | |
60 | VOID\r | |
61 | )\r | |
62 | {\r | |
63 | UINT64 StartTSC;\r | |
64 | UINT64 EndTSC;\r | |
65 | UINT32 TimerAddr;\r | |
66 | UINT32 Ticks;\r | |
67 | \r | |
68 | //\r | |
69 | // If ACPI I/O space is not enabled yet, program ACPI I/O base address and enable it.\r | |
70 | //\r | |
71 | if ((PciRead8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT)) & B_ICH_LPC_ACPI_CNT_ACPI_EN) == 0) {\r | |
72 | PciWrite16 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_BASE), PcdGet16 (PcdPerfPkgAcpiIoPortBaseAddress));\r | |
73 | PciOr8 (PCI_ICH_LPC_ADDRESS (R_ICH_LPC_ACPI_CNT), B_ICH_LPC_ACPI_CNT_ACPI_EN);\r | |
74 | }\r | |
75 | \r | |
76 | TimerAddr = PcdGet16 (PcdPerfPkgAcpiIoPortBaseAddress) + R_ACPI_PM1_TMR; // Locate the ACPI Timer\r | |
77 | Ticks = IoRead32( TimerAddr) + (3579); // Set Ticks to 1ms in the future\r | |
78 | StartTSC = AsmReadTsc(); // Get base value for the TSC\r | |
79 | //\r | |
80 | // Wait until the ACPI timer has counted 1ms.\r | |
81 | // Timer wrap-arounds are handled correctly by this function.\r | |
82 | // When the current ACPI timer value is greater than 'Ticks', the while loop will exit.\r | |
83 | //\r | |
84 | while (((Ticks - IoRead32( TimerAddr)) & BIT23) == 0) {\r | |
85 | CpuPause();\r | |
86 | }\r | |
87 | EndTSC = AsmReadTsc(); // TSC value 1ms later\r | |
88 | \r | |
89 | mTscFrequency = MultU64x32 (\r | |
90 | (EndTSC - StartTSC), // Number of TSC counts in 1ms\r | |
91 | 1000 // Number of ms in a second\r | |
92 | );\r | |
93 | //\r | |
94 | // mTscFrequency is now equal to the number of TSC counts per second\r | |
95 | //\r | |
96 | return RETURN_SUCCESS;\r | |
97 | }\r | |
98 | \r | |
99 | /** Stalls the CPU for at least the given number of ticks.\r | |
100 | \r | |
101 | Stalls the CPU for at least the given number of ticks. It's invoked by\r | |
102 | MicroSecondDelay() and NanoSecondDelay().\r | |
103 | \r | |
104 | @param[in] Delay A period of time to delay in ticks.\r | |
105 | \r | |
106 | **/\r | |
c06ad33e | 107 | VOID\r |
108 | InternalX86Delay (\r | |
109 | IN UINT64 Delay\r | |
110 | )\r | |
111 | {\r | |
112 | UINT64 Ticks;\r | |
113 | \r | |
114 | //\r | |
115 | // The target timer count is calculated here\r | |
116 | //\r | |
117 | Ticks = AsmReadTsc() + Delay;\r | |
118 | \r | |
119 | //\r | |
120 | // Wait until time out\r | |
121 | // Timer wrap-arounds are NOT handled correctly by this function.\r | |
122 | // Thus, this function must be called within 10 years of reset since\r | |
123 | // Intel guarantees a minimum of 10 years before the TSC wraps.\r | |
124 | //\r | |
125 | while (AsmReadTsc() <= Ticks) CpuPause();\r | |
126 | }\r | |
127 | \r | |
128 | /** Stalls the CPU for at least the specified number of MicroSeconds.\r | |
129 | \r | |
130 | @param[in] MicroSeconds The minimum number of microseconds to delay.\r | |
131 | \r | |
132 | @return The value of MicroSeconds input.\r | |
133 | \r | |
134 | **/\r | |
135 | UINTN\r | |
136 | EFIAPI\r | |
137 | MicroSecondDelay (\r | |
138 | IN UINTN MicroSeconds\r | |
139 | )\r | |
140 | {\r | |
141 | InternalX86Delay (\r | |
142 | DivU64x32 (\r | |
143 | MultU64x64 (\r | |
144 | mTscFrequency,\r | |
145 | MicroSeconds\r | |
146 | ),\r | |
147 | 1000000u\r | |
148 | )\r | |
149 | );\r | |
150 | return MicroSeconds;\r | |
151 | }\r | |
152 | \r | |
153 | /** Stalls the CPU for at least the specified number of NanoSeconds.\r | |
154 | \r | |
155 | @param[in] NanoSeconds The minimum number of nanoseconds to delay.\r | |
156 | \r | |
157 | @return The value of NanoSeconds input.\r | |
158 | \r | |
159 | **/\r | |
160 | UINTN\r | |
161 | EFIAPI\r | |
162 | NanoSecondDelay (\r | |
163 | IN UINTN NanoSeconds\r | |
164 | )\r | |
165 | {\r | |
166 | InternalX86Delay (\r | |
167 | DivU64x32 (\r | |
168 | MultU64x32 (\r | |
169 | mTscFrequency,\r | |
170 | (UINT32)NanoSeconds\r | |
171 | ),\r | |
172 | 1000000000u\r | |
173 | )\r | |
174 | );\r | |
175 | return NanoSeconds;\r | |
176 | }\r | |
177 | \r | |
178 | /** Retrieves the current value of the 64-bit free running Time-Stamp counter.\r | |
179 | \r | |
180 | The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M,\r | |
181 | Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors and\r | |
182 | later processors) is a 64-bit counter that is set to 0 following a RESET of\r | |
183 | the processor. Following a RESET, the counter increments even when the\r | |
184 | processor is halted by the HLT instruction or the external STPCLK# pin. Note\r | |
185 | that the assertion of the external DPSLP# pin may cause the time-stamp\r | |
186 | counter to stop.\r | |
187 | \r | |
188 | The properties of the counter can be retrieved by the\r | |
189 | GetPerformanceCounterProperties() function.\r | |
190 | \r | |
191 | @return The current value of the free running performance counter.\r | |
192 | \r | |
193 | **/\r | |
194 | UINT64\r | |
195 | EFIAPI\r | |
196 | GetPerformanceCounter (\r | |
197 | VOID\r | |
198 | )\r | |
199 | {\r | |
200 | return AsmReadTsc();\r | |
201 | }\r | |
202 | \r | |
203 | /** Retrieves the 64-bit frequency in Hz and the range of performance counter\r | |
204 | values.\r | |
205 | \r | |
206 | If StartValue is not NULL, then the value that the performance counter starts\r | |
207 | with, 0x0, is returned in StartValue. If EndValue is not NULL, then the value\r | |
208 | that the performance counter end with, 0xFFFFFFFFFFFFFFFF, is returned in\r | |
209 | EndValue.\r | |
210 | \r | |
211 | The 64-bit frequency of the performance counter, in Hz, is always returned.\r | |
212 | To determine average processor clock frequency, Intel recommends the use of\r | |
213 | EMON logic to count processor core clocks over the period of time for which\r | |
214 | the average is required.\r | |
215 | \r | |
216 | \r | |
217 | @param[out] StartValue Pointer to where the performance counter's starting value is saved, or NULL.\r | |
218 | @param[out] EndValue Pointer to where the performance counter's ending value is saved, or NULL.\r | |
219 | \r | |
220 | @return The frequency in Hz.\r | |
221 | \r | |
222 | **/\r | |
223 | UINT64\r | |
224 | EFIAPI\r | |
225 | GetPerformanceCounterProperties (\r | |
226 | OUT UINT64 *StartValue, OPTIONAL\r | |
227 | OUT UINT64 *EndValue OPTIONAL\r | |
228 | )\r | |
229 | {\r | |
230 | if (StartValue != NULL) {\r | |
231 | *StartValue = 0;\r | |
232 | }\r | |
233 | if (EndValue != NULL) {\r | |
234 | *EndValue = 0xFFFFFFFFFFFFFFFFull;\r | |
235 | }\r | |
236 | \r | |
237 | return mTscFrequency;\r | |
238 | }\r |