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28a7ddf0 | 1 | /** @file\r |
57d16ba1 | 2 | CPUID leaf definitions.\r |
28a7ddf0 | 3 | \r |
57d16ba1 MK |
4 | Provides defines for CPUID leaf indexes. Data structures are provided for\r |
5 | registers returned by a CPUID leaf that contain one or more bit fields.\r | |
6 | If a register returned is a single 32-bit value, then a data structure is\r | |
7 | not provided for that register.\r | |
28a7ddf0 | 8 | \r |
57d16ba1 MK |
9 | Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r |
10 | This program and the accompanying materials are licensed and made available under\r | |
11 | the terms and conditions of the BSD License which accompanies this distribution.\r | |
12 | The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
28a7ddf0 | 14 | \r |
57d16ba1 MK |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Specification Reference:\r | |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,\r | |
20 | December 2015, CPUID instruction.\r | |
28a7ddf0 MK |
21 | \r |
22 | **/\r | |
23 | \r | |
24 | #ifndef __CPUID_H__\r | |
25 | #define __CPUID_H__\r | |
26 | \r | |
57d16ba1 MK |
27 | /**\r |
28 | CPUID Signature Information\r | |
29 | \r | |
30 | @param EAX CPUID_SIGNATURE (0x00)\r | |
31 | \r | |
32 | @retval EAX Returns the highest value the CPUID instruction recognizes for\r | |
33 | returning basic processor information. The value is returned is\r | |
34 | processor specific.\r | |
35 | @retval EBX First 4 characters of a vendor identification string.\r | |
36 | @retval ECX Last 4 characters of a vendor identification string.\r | |
37 | @retval EDX Middle 4 characters of a vendor identification string.\r | |
38 | \r | |
39 | <b>Example usage</b>\r | |
40 | @code\r | |
41 | UINT32 Eax;\r | |
42 | UINT32 Ebx;\r | |
43 | UINT32 Ecx;\r | |
44 | UINT32 Edx;\r | |
45 | \r | |
46 | AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r | |
47 | @endcode\r | |
48 | **/\r | |
49 | #define CPUID_SIGNATURE 0x00\r | |
50 | \r | |
51 | ///\r | |
52 | /// @{ CPUID signature values returned by Intel processors\r | |
53 | ///\r | |
54 | #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')\r | |
55 | #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')\r | |
56 | #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')\r | |
57 | ///\r | |
58 | /// @}\r | |
59 | ///\r | |
60 | \r | |
61 | \r | |
62 | /**\r | |
63 | CPUID Version Information\r | |
64 | \r | |
65 | @param EAX CPUID_VERSION_INFO (0x01)\r | |
66 | \r | |
67 | @retval EAX Returns Model, Family, Stepping Information described by the\r | |
68 | type CPUID_VERSION_INFO_EAX.\r | |
69 | @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by\r | |
70 | the type CPUID_VERSION_INFO_EBX.\r | |
71 | @retval ECX CPU Feature Information described by the type\r | |
72 | CPUID_VERSION_INFO_ECX.\r | |
73 | @retval EDX CPU Feature Information described by the type\r | |
74 | CPUID_VERSION_INFO_EDX.\r | |
75 | \r | |
76 | <b>Example usage</b>\r | |
77 | @code\r | |
78 | CPUID_VERSION_INFO_EAX Eax;\r | |
79 | CPUID_VERSION_INFO_EBX Ebx;\r | |
80 | CPUID_VERSION_INFO_ECX Ecx;\r | |
81 | CPUID_VERSION_INFO_EDX Edx;\r | |
82 | \r | |
83 | AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
84 | @endcode\r | |
85 | **/\r | |
86 | #define CPUID_VERSION_INFO 0x01\r | |
87 | \r | |
88 | /**\r | |
89 | CPUID Version Information returned in EAX for CPUID leaf\r | |
90 | #CPUID_VERSION_INFO.\r | |
91 | **/\r | |
92 | typedef union {\r | |
93 | ///\r | |
94 | /// Individual bit fields\r | |
95 | ///\r | |
96 | struct {\r | |
97 | UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID\r | |
98 | UINT32 Model:4; ///< [Bits 7:4] Model\r | |
99 | UINT32 FamilyId:4; ///< [Bits 11:8] Family\r | |
100 | UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type\r | |
101 | UINT32 Reserved1:2; ///< [Bits 15:14] Reserved\r | |
102 | UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID\r | |
103 | UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID\r | |
104 | UINT32 Reserved2:4; ///< Reserved\r | |
105 | } Bits;\r | |
106 | ///\r | |
107 | /// All bit fields as a 32-bit value\r | |
108 | ///\r | |
109 | UINT32 Uint32;\r | |
110 | } CPUID_VERSION_INFO_EAX;\r | |
111 | \r | |
112 | ///\r | |
113 | /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType\r | |
114 | ///\r | |
115 | #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00\r | |
116 | #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01\r | |
117 | #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02\r | |
118 | ///\r | |
119 | /// @}\r | |
120 | ///\r | |
121 | \r | |
122 | /**\r | |
123 | CPUID Version Information returned in EBX for CPUID leaf\r | |
124 | #CPUID_VERSION_INFO.\r | |
125 | **/\r | |
126 | typedef union {\r | |
127 | ///\r | |
128 | /// Individual bit fields\r | |
129 | ///\r | |
130 | struct {\r | |
131 | ///\r | |
132 | /// [Bits 7:0] Provides an entry into a brand string table that contains\r | |
133 | /// brand strings for IA-32 processors.\r | |
134 | ///\r | |
135 | UINT32 BrandIndex:8;\r | |
136 | ///\r | |
137 | /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH\r | |
138 | /// and CLFLUSHOPT instructions in 8-byte increments. This field was\r | |
139 | /// introduced in the Pentium 4 processor.\r | |
140 | ///\r | |
141 | UINT32 CacheLineSize:8;\r | |
142 | ///\r | |
143 | /// [Bits 23:16] Maximum number of addressable IDs for logical processors\r | |
144 | /// in this physical package.\r | |
145 | ///\r | |
146 | /// @note\r | |
147 | /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is\r | |
148 | /// the number of unique initial APICIDs reserved for addressing different\r | |
149 | /// logical processors in a physical package. This field is only valid if\r | |
150 | /// CPUID.1.EDX.HTT[bit 28]= 1.\r | |
151 | ///\r | |
152 | UINT32 MaximumAddressableIdsForLogicalProcessors:8;\r | |
153 | ///\r | |
154 | /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the\r | |
155 | /// processor during power up. This field was introduced in the Pentium 4\r | |
156 | /// processor.\r | |
157 | ///\r | |
158 | UINT32 InitialLocalApicId:8;\r | |
159 | } Bits;\r | |
160 | ///\r | |
161 | /// All bit fields as a 32-bit value\r | |
162 | ///\r | |
163 | UINT32 Uint32;\r | |
164 | } CPUID_VERSION_INFO_EBX;\r | |
165 | \r | |
166 | /**\r | |
167 | CPUID Version Information returned in ECX for CPUID leaf\r | |
168 | #CPUID_VERSION_INFO.\r | |
169 | **/\r | |
170 | typedef union {\r | |
171 | ///\r | |
172 | /// Individual bit fields\r | |
173 | ///\r | |
174 | struct {\r | |
175 | ///\r | |
176 | /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the\r | |
177 | /// processor supports this technology\r | |
178 | ///\r | |
179 | UINT32 SSE3:1;\r | |
180 | ///\r | |
181 | /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ\r | |
182 | /// instruction. Carryless Multiplication\r | |
183 | ///\r | |
184 | UINT32 PCLMULQDQ:1;\r | |
185 | ///\r | |
186 | /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports\r | |
187 | /// DS area using 64-bit layout.\r | |
188 | ///\r | |
189 | UINT32 DTES64:1;\r | |
190 | ///\r | |
191 | /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports\r | |
192 | /// this feature.\r | |
193 | ///\r | |
194 | UINT32 MONITOR:1;\r | |
195 | ///\r | |
196 | /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor\r | |
197 | /// supports the extensions to the Debug Store feature to allow for branch\r | |
198 | /// message storage qualified by CPL\r | |
199 | ///\r | |
200 | UINT32 DS_CPL:1;\r | |
201 | ///\r | |
202 | /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the\r | |
203 | /// processor supports this technology.\r | |
204 | ///\r | |
205 | UINT32 VMX:1;\r | |
206 | ///\r | |
207 | /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor\r | |
208 | /// supports this technology\r | |
209 | ///\r | |
210 | UINT32 SMX:1;\r | |
211 | ///\r | |
212 | /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates\r | |
213 | /// that the processor supports this technology\r | |
214 | ///\r | |
215 | UINT32 EIST:1;\r | |
216 | ///\r | |
217 | /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor\r | |
218 | /// supports this technology\r | |
219 | ///\r | |
220 | UINT32 TM2:1;\r | |
221 | ///\r | |
222 | /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming\r | |
223 | /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction\r | |
224 | /// extensions are not present in the processor.\r | |
225 | ///\r | |
226 | UINT32 SSSE3:1;\r | |
227 | ///\r | |
228 | /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode\r | |
229 | /// can be set to either adaptive mode or shared mode. A value of 0 indicates\r | |
230 | /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR\r | |
231 | /// Bit 24 (L1 Data Cache Context Mode) for details\r | |
232 | ///\r | |
233 | UINT32 CNXT_ID:1;\r | |
234 | ///\r | |
235 | /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE\r | |
236 | /// MSR for silicon debug\r | |
237 | ///\r | |
238 | UINT32 SDBG:1;\r | |
239 | ///\r | |
240 | /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple\r | |
241 | /// Add) extensions using YMM state.\r | |
242 | ///\r | |
243 | UINT32 FMA:1;\r | |
244 | ///\r | |
245 | /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature\r | |
246 | /// is available.\r | |
247 | ///\r | |
248 | UINT32 CMPXCHG16B:1;\r | |
249 | ///\r | |
250 | /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor\r | |
251 | /// supports changing IA32_MISC_ENABLE[Bit 23].\r | |
252 | ///\r | |
253 | UINT32 xTPR_Update_Control:1;\r | |
254 | ///\r | |
255 | /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the\r | |
256 | /// processor supports the performance and debug feature indication MSR\r | |
257 | /// IA32_PERF_CAPABILITIES.\r | |
258 | ///\r | |
259 | UINT32 PDCM:1;\r | |
260 | UINT32 Reserved:1;\r | |
261 | ///\r | |
262 | /// [Bit 17] Process-context identifiers. A value of 1 indicates that the\r | |
263 | /// processor supports PCIDs and that software may set CR4.PCIDE to 1.\r | |
264 | ///\r | |
265 | UINT32 PCID:1;\r | |
266 | ///\r | |
267 | /// [Bit 18] A value of 1 indicates the processor supports the ability to\r | |
268 | /// prefetch data from a memory mapped device. Direct Cache Access.\r | |
269 | ///\r | |
270 | UINT32 DCA:1;\r | |
271 | ///\r | |
272 | /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.\r | |
273 | ///\r | |
274 | UINT32 SSE4_1:1;\r | |
275 | ///\r | |
276 | /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.\r | |
277 | ///\r | |
278 | UINT32 SSE4_2:1;\r | |
279 | ///\r | |
280 | /// [Bit 21] A value of 1 indicates that the processor supports x2APIC\r | |
281 | /// feature.\r | |
282 | ///\r | |
283 | UINT32 x2APIC:1;\r | |
284 | ///\r | |
285 | /// [Bit 22] A value of 1 indicates that the processor supports MOVBE\r | |
286 | /// instruction.\r | |
287 | ///\r | |
288 | UINT32 MOVBE:1;\r | |
289 | ///\r | |
290 | /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT\r | |
291 | /// instruction.\r | |
292 | ///\r | |
293 | UINT32 POPCNT:1;\r | |
294 | ///\r | |
295 | /// [Bit 24] A value of 1 indicates that the processor's local APIC timer\r | |
296 | /// supports one-shot operation using a TSC deadline value.\r | |
297 | ///\r | |
298 | UINT32 TSC_Deadline:1;\r | |
299 | ///\r | |
300 | /// [Bit 25] A value of 1 indicates that the processor supports the AESNI\r | |
301 | /// instruction extensions.\r | |
302 | ///\r | |
303 | UINT32 AESNI:1;\r | |
304 | ///\r | |
305 | /// [Bit 26] A value of 1 indicates that the processor supports the\r | |
306 | /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV\r | |
307 | /// instructions, and XCR0.\r | |
308 | ///\r | |
309 | UINT32 XSAVE:1;\r | |
310 | ///\r | |
311 | /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]\r | |
312 | /// to enable XSETBV/XGETBV instructions to access XCR0 and to support\r | |
313 | /// processor extended state management using XSAVE/XRSTOR.\r | |
314 | ///\r | |
315 | UINT32 OSXSAVE:1;\r | |
316 | ///\r | |
317 | /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction\r | |
318 | /// extensions.\r | |
319 | ///\r | |
320 | UINT32 AVX:1;\r | |
321 | ///\r | |
322 | /// [Bit 29] A value of 1 indicates that processor supports 16-bit\r | |
323 | /// floating-point conversion instructions.\r | |
324 | ///\r | |
325 | UINT32 F16C:1;\r | |
326 | ///\r | |
327 | /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.\r | |
328 | ///\r | |
329 | UINT32 RDRAND:1;\r | |
330 | ///\r | |
331 | /// [Bit 31] Always returns 0.\r | |
332 | ///\r | |
333 | UINT32 NotUsed:1;\r | |
334 | } Bits;\r | |
335 | ///\r | |
336 | /// All bit fields as a 32-bit value\r | |
337 | ///\r | |
338 | UINT32 Uint32;\r | |
339 | } CPUID_VERSION_INFO_ECX;\r | |
340 | \r | |
341 | /**\r | |
342 | CPUID Version Information returned in EDX for CPUID leaf\r | |
343 | #CPUID_VERSION_INFO.\r | |
344 | **/\r | |
345 | typedef union {\r | |
346 | ///\r | |
347 | /// Individual bit fields\r | |
348 | ///\r | |
349 | struct {\r | |
350 | ///\r | |
351 | /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.\r | |
352 | ///\r | |
353 | UINT32 FPU:1;\r | |
354 | ///\r | |
355 | /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,\r | |
356 | /// including CR4.VME for controlling the feature, CR4.PVI for protected\r | |
357 | /// mode virtual interrupts, software interrupt indirection, expansion of\r | |
358 | /// the TSS with the software indirection bitmap, and EFLAGS.VIF and\r | |
359 | /// EFLAGS.VIP flags.\r | |
360 | ///\r | |
361 | UINT32 VME:1;\r | |
362 | ///\r | |
363 | /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including\r | |
364 | /// CR4.DE for controlling the feature, and optional trapping of accesses to\r | |
365 | /// DR4 and DR5.\r | |
366 | ///\r | |
367 | UINT32 DE:1;\r | |
368 | ///\r | |
369 | /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,\r | |
370 | /// including CR4.PSE for controlling the feature, the defined dirty bit in\r | |
371 | /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,\r | |
372 | /// PDEs, and PTEs.\r | |
373 | ///\r | |
374 | UINT32 PSE:1;\r | |
375 | ///\r | |
376 | /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,\r | |
377 | /// including CR4.TSD for controlling privilege.\r | |
378 | ///\r | |
379 | UINT32 TSC:1;\r | |
380 | ///\r | |
381 | /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The\r | |
382 | /// RDMSR and WRMSR instructions are supported. Some of the MSRs are\r | |
383 | /// implementation dependent.\r | |
384 | ///\r | |
385 | UINT32 MSR:1;\r | |
386 | ///\r | |
387 | /// [Bit 6] Physical Address Extension. Physical addresses greater than 32\r | |
388 | /// bits are supported: extended page table entry formats, an extra level in\r | |
389 | /// the page translation tables is defined, 2-MByte pages are supported\r | |
390 | /// instead of 4 Mbyte pages if PAE bit is 1.\r | |
391 | ///\r | |
392 | UINT32 PAE:1;\r | |
393 | ///\r | |
394 | /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine\r | |
395 | /// Checks, including CR4.MCE for controlling the feature. This feature does\r | |
396 | /// not define the model-specific implementations of machine-check error\r | |
397 | /// logging, reporting, and processor shutdowns. Machine Check exception\r | |
398 | /// handlers may have to depend on processor version to do model specific\r | |
399 | /// processing of the exception, or test for the presence of the Machine\r | |
400 | /// Check feature.\r | |
401 | ///\r | |
402 | UINT32 MCE:1;\r | |
403 | ///\r | |
404 | /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)\r | |
405 | /// instruction is supported (implicitly locked and atomic).\r | |
406 | ///\r | |
407 | UINT32 CX8:1;\r | |
408 | ///\r | |
409 | /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable\r | |
410 | /// Interrupt Controller (APIC), responding to memory mapped commands in the\r | |
411 | /// physical address range FFFE0000H to FFFE0FFFH (by default - some\r | |
412 | /// processors permit the APIC to be relocated).\r | |
413 | ///\r | |
414 | UINT32 APIC:1;\r | |
415 | UINT32 Reserved1:1;\r | |
416 | ///\r | |
417 | /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT\r | |
418 | /// and associated MSRs are supported.\r | |
419 | ///\r | |
420 | UINT32 SEP:1;\r | |
421 | ///\r | |
422 | /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap\r | |
423 | /// MSR contains feature bits that describe what memory types are supported,\r | |
424 | /// how many variable MTRRs are supported, and whether fixed MTRRs are\r | |
425 | /// supported.\r | |
426 | ///\r | |
427 | UINT32 MTRR:1;\r | |
428 | ///\r | |
429 | /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure\r | |
430 | /// entries that map a page, indicating TLB entries that are common to\r | |
431 | /// different processes and need not be flushed. The CR4.PGE bit controls\r | |
432 | /// this feature.\r | |
433 | ///\r | |
434 | UINT32 PGE:1;\r | |
435 | ///\r | |
436 | /// [Bit 14] Machine Check Architecture. The Machine Check Architecture,\r | |
437 | /// which provides a compatible mechanism for error reporting in P6 family,\r | |
438 | /// Pentium 4, Intel Xeon processors, and future processors, is supported.\r | |
439 | /// The MCG_CAP MSR contains feature bits describing how many banks of error\r | |
440 | /// reporting MSRs are supported.\r | |
441 | ///\r | |
442 | UINT32 MCA:1;\r | |
443 | ///\r | |
444 | /// [Bit 15] Conditional Move Instructions. The conditional move instruction\r | |
445 | /// CMOV is supported. In addition, if x87 FPU is present as indicated by the\r | |
446 | /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.\r | |
447 | ///\r | |
448 | UINT32 CMOV:1;\r | |
449 | ///\r | |
450 | /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This\r | |
451 | /// feature augments the Memory Type Range Registers (MTRRs), allowing an\r | |
452 | /// operating system to specify attributes of memory accessed through a\r | |
453 | /// linear address on a 4KB granularity.\r | |
454 | ///\r | |
455 | UINT32 PAT:1;\r | |
456 | ///\r | |
457 | /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical\r | |
458 | /// memory beyond 4 GBytes are supported with 32-bit paging. This feature\r | |
459 | /// indicates that upper bits of the physical address of a 4-MByte page are\r | |
460 | /// encoded in bits 20:13 of the page-directory entry. Such physical\r | |
461 | /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.\r | |
462 | ///\r | |
463 | UINT32 PSE_36:1;\r | |
464 | ///\r | |
465 | /// [Bit 18] Processor Serial Number. The processor supports the 96-bit\r | |
466 | /// processor identification number feature and the feature is enabled.\r | |
467 | ///\r | |
468 | UINT32 PSN:1;\r | |
469 | ///\r | |
470 | /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.\r | |
471 | ///\r | |
472 | UINT32 CLFSH:1;\r | |
473 | UINT32 Reserved2:1;\r | |
474 | ///\r | |
475 | /// [Bit 21] Debug Store. The processor supports the ability to write debug\r | |
476 | /// information into a memory resident buffer. This feature is used by the\r | |
477 | /// branch trace store (BTS) and precise event-based sampling (PEBS)\r | |
478 | /// facilities.\r | |
479 | ///\r | |
480 | UINT32 DS:1;\r | |
481 | ///\r | |
482 | /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The\r | |
483 | /// processor implements internal MSRs that allow processor temperature to\r | |
484 | /// be monitored and processor performance to be modulated in predefined\r | |
485 | /// duty cycles under software control.\r | |
486 | ///\r | |
487 | UINT32 ACPI:1;\r | |
488 | ///\r | |
489 | /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX\r | |
490 | /// technology.\r | |
491 | ///\r | |
492 | UINT32 MMX:1;\r | |
493 | ///\r | |
494 | /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR\r | |
495 | /// instructions are supported for fast save and restore of the floating\r | |
496 | /// point context. Presence of this bit also indicates that CR4.OSFXSR is\r | |
497 | /// available for an operating system to indicate that it supports the\r | |
498 | /// FXSAVE and FXRSTOR instructions.\r | |
499 | ///\r | |
500 | UINT32 FXSR:1;\r | |
501 | ///\r | |
502 | /// [Bit 25] SSE. The processor supports the SSE extensions.\r | |
503 | ///\r | |
504 | UINT32 SSE:1;\r | |
505 | ///\r | |
506 | /// [Bit 26] SSE2. The processor supports the SSE2 extensions.\r | |
507 | ///\r | |
508 | UINT32 SSE2:1;\r | |
509 | ///\r | |
510 | /// [Bit 27] Self Snoop. The processor supports the management of\r | |
511 | /// conflicting memory types by performing a snoop of its own cache\r | |
512 | /// structure for transactions issued to the bus.\r | |
513 | ///\r | |
514 | UINT32 SS:1;\r | |
515 | ///\r | |
516 | /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT\r | |
517 | /// indicates there is only a single logical processor in the package and\r | |
518 | /// software should assume only a single APIC ID is reserved. A value of 1\r | |
519 | /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of\r | |
520 | /// addressable IDs for logical processors in this package) is valid for the\r | |
521 | /// package.\r | |
522 | ///\r | |
523 | UINT32 HTT:1;\r | |
524 | ///\r | |
525 | /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor\r | |
526 | /// automatic thermal control circuitry (TCC).\r | |
527 | ///\r | |
528 | UINT32 TM:1;\r | |
529 | UINT32 Reserved3:1;\r | |
530 | ///\r | |
531 | /// [Bit 31] Pending Break Enable. The processor supports the use of the\r | |
532 | /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is\r | |
533 | /// asserted) to signal the processor that an interrupt is pending and that\r | |
534 | /// the processor should return to normal operation to handle the interrupt.\r | |
535 | /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.\r | |
536 | ///\r | |
537 | UINT32 PBE:1;\r | |
538 | } Bits;\r | |
539 | ///\r | |
540 | /// All bit fields as a 32-bit value\r | |
541 | ///\r | |
542 | UINT32 Uint32;\r | |
543 | } CPUID_VERSION_INFO_EDX;\r | |
544 | \r | |
545 | \r | |
546 | /**\r | |
547 | CPUID Cache and TLB Information\r | |
548 | \r | |
549 | @param EAX CPUID_CACHE_INFO (0x02)\r | |
550 | \r | |
551 | @retval EAX Cache and TLB Information described by the type\r | |
552 | CPUID_CACHE_INFO_CACHE_TLB.\r | |
553 | CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns\r | |
554 | 0x01 and must be ignored. Only valid if\r | |
555 | CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r | |
556 | @retval EBX Cache and TLB Information described by the type\r | |
557 | CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r | |
558 | CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r | |
559 | @retval ECX Cache and TLB Information described by the type\r | |
560 | CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r | |
561 | CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r | |
562 | @retval EDX Cache and TLB Information described by the type\r | |
563 | CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r | |
564 | CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r | |
565 | \r | |
566 | <b>Example usage</b>\r | |
567 | @code\r | |
568 | CPUID_CACHE_INFO_CACHE_TLB Eax;\r | |
569 | CPUID_CACHE_INFO_CACHE_TLB Ebx;\r | |
570 | CPUID_CACHE_INFO_CACHE_TLB Ecx;\r | |
571 | CPUID_CACHE_INFO_CACHE_TLB Edx;\r | |
572 | \r | |
573 | AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
574 | @endcode\r | |
575 | \r | |
576 | <b>Cache Descriptor values</b>\r | |
577 | <table>\r | |
578 | <tr><th>Value </th><th> Type </th><th> Description </th></tr>\r | |
579 | <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>\r | |
580 | <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>\r | |
581 | <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>\r | |
582 | <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>\r | |
583 | <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>\r | |
584 | <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r | |
585 | <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,\r | |
586 | 32 byte line size</td></tr>\r | |
587 | <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,\r | |
588 | 32 byte line size</td></tr>\r | |
589 | <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,\r | |
590 | 64 byte line size</td></tr>\r | |
591 | <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>\r | |
592 | <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>\r | |
593 | <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>\r | |
594 | <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>\r | |
595 | <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>\r | |
596 | <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>\r | |
597 | <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>\r | |
598 | <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,\r | |
599 | 2 lines per sector</td></tr>\r | |
600 | <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,\r | |
601 | 2 lines per sector</td></tr>\r | |
602 | <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>\r | |
603 | <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,\r | |
604 | 2 lines per sector</td></tr>\r | |
605 | <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,\r | |
606 | 2 lines per sector</td></tr>\r | |
607 | <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,\r | |
608 | 64 byte line size</td></tr>\r | |
609 | <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,\r | |
610 | 64 byte line size</td></tr>\r | |
611 | <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,\r | |
612 | no 3rd-level cache</td></tr>\r | |
613 | <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>\r | |
614 | <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>\r | |
615 | <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>\r | |
616 | <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>\r | |
617 | <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>\r | |
618 | <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>\r | |
619 | <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>\r | |
620 | <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>\r | |
621 | <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size\r | |
622 | (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>\r | |
623 | 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>\r | |
624 | <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>\r | |
625 | <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>\r | |
626 | <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>\r | |
627 | <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>\r | |
628 | <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>\r | |
629 | <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>\r | |
630 | <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>\r | |
631 | <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>\r | |
632 | <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>\r | |
633 | <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>\r | |
634 | <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>\r | |
635 | <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>\r | |
636 | <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>\r | |
637 | <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r | |
638 | <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>\r | |
639 | <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>\r | |
640 | <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>\r | |
641 | <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>\r | |
642 | <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>\r | |
643 | <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 1 GByte pages, 4-way set associative, 4 entries</td></tr>\r | |
644 | <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>\r | |
645 | <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>\r | |
646 | <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>\r | |
647 | <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>\r | |
648 | <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>\r | |
649 | <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>\r | |
650 | <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>\r | |
651 | <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>\r | |
652 | <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>\r | |
653 | <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>\r | |
654 | <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>\r | |
655 | <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>\r | |
656 | <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,\r | |
657 | 2 lines per sector</td></tr>\r | |
658 | <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,\r | |
659 | 2 lines per sector</td></tr>\r | |
660 | <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,\r | |
661 | 2 lines per sector</td></tr>\r | |
662 | <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,\r | |
663 | 2 lines per sector</td></tr>\r | |
664 | <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>\r | |
665 | <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>\r | |
666 | <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>\r | |
667 | <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>\r | |
668 | <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>\r | |
669 | <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>\r | |
670 | <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>\r | |
671 | <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r | |
672 | <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>\r | |
673 | <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>\r | |
674 | <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>\r | |
675 | <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>\r | |
676 | <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>\r | |
677 | <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>\r | |
678 | <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>\r | |
679 | <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>\r | |
680 | <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,\r | |
681 | 128 entries</td></tr>\r | |
682 | <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>\r | |
683 | <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>\r | |
684 | <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,\r | |
685 | 1024 entries</td></tr>\r | |
686 | <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>\r | |
687 | <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,\r | |
688 | 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>\r | |
689 | <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>\r | |
690 | <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r | |
691 | <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>\r | |
692 | <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>\r | |
693 | <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>\r | |
694 | <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>\r | |
695 | <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>\r | |
696 | <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>\r | |
697 | <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>\r | |
698 | <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>\r | |
699 | <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>\r | |
700 | <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>\r | |
701 | <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>\r | |
702 | <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>\r | |
703 | <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>\r | |
704 | <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>\r | |
705 | <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>\r | |
706 | <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>\r | |
707 | <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,\r | |
708 | use CPUID leaf 4 to query cache parameters</td></tr>\r | |
709 | </table>\r | |
710 | **/\r | |
711 | #define CPUID_CACHE_INFO 0x02\r | |
712 | \r | |
713 | /**\r | |
714 | CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID\r | |
715 | leaf #CPUID_CACHE_INFO.\r | |
716 | **/\r | |
717 | typedef union {\r | |
718 | ///\r | |
719 | /// Individual bit fields\r | |
720 | ///\r | |
721 | struct {\r | |
722 | UINT32 Reserved:31;\r | |
723 | ///\r | |
724 | /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.\r | |
725 | /// if 1, then none of the cache descriptor bytes in the register are valid.\r | |
726 | ///\r | |
727 | UINT32 NotValid:1;\r | |
728 | } Bits;\r | |
729 | ///\r | |
730 | /// Array of Cache and TLB descriptor bytes\r | |
731 | ///\r | |
732 | UINT8 CacheDescriptor[4];\r | |
733 | ///\r | |
734 | /// All bit fields as a 32-bit value\r | |
735 | ///\r | |
736 | UINT32 Uint32;\r | |
737 | } CPUID_CACHE_INFO_CACHE_TLB;\r | |
738 | \r | |
739 | \r | |
740 | /**\r | |
741 | CPUID Processor Serial Number\r | |
742 | \r | |
743 | Processor serial number (PSN) is not supported in the Pentium 4 processor\r | |
744 | or later. On all models, use the PSN flag (returned using CPUID) to check\r | |
745 | for PSN support before accessing the feature.\r | |
746 | \r | |
747 | @param EAX CPUID_SERIAL_NUMBER (0x03)\r | |
748 | \r | |
749 | @retval EAX Reserved.\r | |
750 | @retval EBX Reserved.\r | |
751 | @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in\r | |
752 | Pentium III processor only; otherwise, the value in this\r | |
753 | register is reserved.)\r | |
754 | @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in\r | |
755 | Pentium III processor only; otherwise, the value in this\r | |
756 | register is reserved.)\r | |
757 | \r | |
758 | <b>Example usage</b>\r | |
759 | @code\r | |
760 | UINT32 Ecx;\r | |
761 | UINT32 Edx;\r | |
762 | \r | |
763 | AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);\r | |
764 | @endcode\r | |
765 | **/\r | |
766 | #define CPUID_SERIAL_NUMBER 0x03\r | |
767 | \r | |
768 | \r | |
769 | /**\r | |
770 | CPUID Cache Parameters\r | |
771 | \r | |
772 | @param EAX CPUID_CACHE_PARAMS (0x04)\r | |
773 | @param ECX Cache Level. Valid values start at 0. Software can enumerate\r | |
774 | the deterministic cache parameters for each level of the cache\r | |
775 | hierarchy starting with an index value of 0, until the\r | |
776 | parameters report the value associated with the CacheType\r | |
777 | field in CPUID_CACHE_PARAMS_EAX is 0.\r | |
778 | \r | |
779 | @retval EAX Returns cache type information described by the type\r | |
780 | CPUID_CACHE_PARAMS_EAX.\r | |
781 | @retval EBX Returns cache line and associativity information described by\r | |
782 | the type CPUID_CACHE_PARAMS_EBX.\r | |
783 | @retval ECX Returns the number of sets in the cache.\r | |
784 | @retval EDX Returns cache WINVD/INVD behavior described by the type\r | |
785 | CPUID_CACHE_PARAMS_EDX.\r | |
786 | \r | |
787 | <b>Example usage</b>\r | |
788 | @code\r | |
789 | UINT32 CacheLevel;\r | |
790 | CPUID_CACHE_PARAMS_EAX Eax;\r | |
791 | CPUID_CACHE_PARAMS_EBX Ebx;\r | |
792 | UINT32 Ecx;\r | |
793 | CPUID_CACHE_PARAMS_EDX Edx;\r | |
794 | \r | |
795 | CacheLevel = 0;\r | |
796 | do {\r | |
797 | AsmCpuidEx (\r | |
798 | CPUID_CACHE_PARAMS, CacheLevel,\r | |
799 | &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32\r | |
800 | );\r | |
801 | CacheLevel++;\r | |
802 | } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);\r | |
803 | @endcode\r | |
804 | **/\r | |
805 | #define CPUID_CACHE_PARAMS 0x04\r | |
806 | \r | |
807 | /**\r | |
808 | CPUID Cache Parameters Information returned in EAX for CPUID leaf\r | |
809 | #CPUID_CACHE_PARAMS.\r | |
810 | **/\r | |
811 | typedef union {\r | |
812 | ///\r | |
813 | /// Individual bit fields\r | |
814 | ///\r | |
815 | struct {\r | |
816 | ///\r | |
817 | /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,\r | |
818 | /// then there is no information for the requested cache level.\r | |
819 | ///\r | |
820 | UINT32 CacheType:5;\r | |
821 | ///\r | |
822 | /// [Bits 7:5] Cache level (Starts at 1).\r | |
823 | ///\r | |
824 | UINT32 CacheLevel:3;\r | |
825 | ///\r | |
826 | /// [Bit 8] Self Initializing cache level (does not need SW initialization).\r | |
827 | ///\r | |
828 | UINT32 SelfInitializingCache:1;\r | |
829 | ///\r | |
830 | /// [Bit 9] Fully Associative cache.\r | |
831 | ///\r | |
832 | UINT32 FullyAssociativeCache:1;\r | |
833 | ///\r | |
834 | /// [Bits 13:10] Reserved.\r | |
835 | ///\r | |
836 | UINT32 Reserved:4;\r | |
837 | ///\r | |
838 | /// [Bits 25:14] Maximum number of addressable IDs for logical processors\r | |
839 | /// sharing this cache.\r | |
840 | ///\r | |
841 | /// Add one to the return value to get the result.\r | |
842 | /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])\r | |
843 | /// is the number of unique initial APIC IDs reserved for addressing\r | |
844 | /// different logical processors sharing this cache.\r | |
845 | ///\r | |
846 | UINT32 MaximumAddressableIdsForLogicalProcessors:12;\r | |
847 | ///\r | |
848 | /// [Bits 31:26] Maximum number of addressable IDs for processor cores in\r | |
849 | /// the physical package.\r | |
850 | ///\r | |
851 | /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])\r | |
852 | /// is the number of unique Core_IDs reserved for addressing different\r | |
853 | /// processor cores in a physical package. Core ID is a subset of bits of\r | |
854 | /// the initial APIC ID.\r | |
855 | /// The returned value is constant for valid initial values in ECX. Valid\r | |
856 | /// ECX values start from 0.\r | |
857 | ///\r | |
858 | UINT32 MaximumAddressableIdsForProcessorCores:6;\r | |
859 | } Bits;\r | |
860 | ///\r | |
861 | /// All bit fields as a 32-bit value\r | |
862 | ///\r | |
863 | UINT32 Uint32;\r | |
864 | } CPUID_CACHE_PARAMS_EAX;\r | |
865 | \r | |
866 | ///\r | |
867 | /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType\r | |
868 | ///\r | |
869 | #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00\r | |
870 | #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01\r | |
871 | #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02\r | |
872 | #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03\r | |
873 | ///\r | |
874 | /// @}\r | |
875 | ///\r | |
876 | \r | |
877 | /**\r | |
878 | CPUID Cache Parameters Information returned in EBX for CPUID leaf\r | |
879 | #CPUID_CACHE_PARAMS.\r | |
880 | **/\r | |
881 | typedef union {\r | |
882 | ///\r | |
883 | /// Individual bit fields\r | |
884 | ///\r | |
885 | struct {\r | |
886 | ///\r | |
887 | /// [Bits 11:0] System Coherency Line Size. Add one to the return value to\r | |
888 | /// get the result.\r | |
889 | ///\r | |
890 | UINT32 LineSize:12;\r | |
891 | ///\r | |
892 | /// [Bits 21:12] Physical Line Partitions. Add one to the return value to\r | |
893 | /// get the result.\r | |
894 | ///\r | |
895 | UINT32 LinePartitions:10;\r | |
896 | ///\r | |
897 | /// [Bits 31:22] Ways of associativity. Add one to the return value to get\r | |
898 | /// the result.\r | |
899 | ///\r | |
900 | UINT32 Ways:10;\r | |
901 | } Bits;\r | |
902 | ///\r | |
903 | /// All bit fields as a 32-bit value\r | |
904 | ///\r | |
905 | UINT32 Uint32;\r | |
906 | } CPUID_CACHE_PARAMS_EBX;\r | |
907 | \r | |
908 | /**\r | |
909 | CPUID Cache Parameters Information returned in EDX for CPUID leaf\r | |
910 | #CPUID_CACHE_PARAMS.\r | |
911 | **/\r | |
912 | typedef union {\r | |
913 | ///\r | |
914 | /// Individual bit fields\r | |
915 | ///\r | |
916 | struct {\r | |
917 | ///\r | |
918 | /// [Bit 0] Write-Back Invalidate/Invalidate.\r | |
919 | /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level\r | |
920 | /// caches for threads sharing this cache.\r | |
921 | /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of\r | |
922 | /// non-originating threads sharing this cache.\r | |
923 | ///\r | |
924 | UINT32 Invalidate:1;\r | |
925 | ///\r | |
926 | /// [Bit 1] Cache Inclusiveness.\r | |
927 | /// 0 = Cache is not inclusive of lower cache levels.\r | |
928 | /// 1 = Cache is inclusive of lower cache levels.\r | |
929 | ///\r | |
930 | UINT32 CacheInclusiveness:1;\r | |
931 | ///\r | |
932 | /// [Bit 2] Complex Cache Indexing.\r | |
933 | /// 0 = Direct mapped cache.\r | |
934 | /// 1 = A complex function is used to index the cache, potentially using all\r | |
935 | /// address bits.\r | |
936 | ///\r | |
937 | UINT32 ComplexCacheIndexing:1;\r | |
938 | UINT32 Reserved:29;\r | |
939 | } Bits;\r | |
940 | ///\r | |
941 | /// All bit fields as a 32-bit value\r | |
942 | ///\r | |
943 | UINT32 Uint32;\r | |
944 | } CPUID_CACHE_PARAMS_EDX;\r | |
945 | \r | |
946 | \r | |
947 | /**\r | |
948 | CPUID MONITOR/MWAIT Information\r | |
949 | \r | |
950 | @param EAX CPUID_MONITOR_MWAIT (0x05)\r | |
951 | \r | |
952 | @retval EAX Smallest monitor-line size in bytes described by the type\r | |
953 | CPUID_MONITOR_MWAIT_EAX.\r | |
954 | @retval EBX Largest monitor-line size in bytes described by the type\r | |
955 | CPUID_MONITOR_MWAIT_EBX.\r | |
956 | @retval ECX Enumeration of Monitor-Mwait extensions support described by\r | |
957 | the type CPUID_MONITOR_MWAIT_ECX.\r | |
958 | @retval EDX Sub C-states supported described by the type\r | |
959 | CPUID_MONITOR_MWAIT_EDX.\r | |
960 | \r | |
961 | <b>Example usage</b>\r | |
962 | @code\r | |
963 | CPUID_MONITOR_MWAIT_EAX Eax;\r | |
964 | CPUID_MONITOR_MWAIT_EBX Ebx;\r | |
965 | CPUID_MONITOR_MWAIT_ECX Ecx;\r | |
966 | CPUID_MONITOR_MWAIT_EDX Edx;\r | |
967 | \r | |
968 | AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
969 | @endcode\r | |
970 | **/\r | |
971 | #define CPUID_MONITOR_MWAIT 0x05\r | |
972 | \r | |
973 | /**\r | |
974 | CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf\r | |
975 | #CPUID_MONITOR_MWAIT.\r | |
976 | **/\r | |
977 | typedef union {\r | |
978 | ///\r | |
979 | /// Individual bit fields\r | |
980 | ///\r | |
981 | struct {\r | |
982 | ///\r | |
983 | /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's\r | |
984 | /// monitor granularity).\r | |
985 | ///\r | |
986 | UINT32 SmallestMonitorLineSize:16;\r | |
987 | UINT32 Reserved:16;\r | |
988 | } Bits;\r | |
989 | ///\r | |
990 | /// All bit fields as a 32-bit value\r | |
991 | ///\r | |
992 | UINT32 Uint32;\r | |
993 | } CPUID_MONITOR_MWAIT_EAX;\r | |
994 | \r | |
995 | /**\r | |
996 | CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf\r | |
997 | #CPUID_MONITOR_MWAIT.\r | |
998 | **/\r | |
999 | typedef union {\r | |
1000 | ///\r | |
1001 | /// Individual bit fields\r | |
1002 | ///\r | |
1003 | struct {\r | |
1004 | ///\r | |
1005 | /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's\r | |
1006 | /// monitor granularity).\r | |
1007 | ///\r | |
1008 | UINT32 LargestMonitorLineSize:16;\r | |
1009 | UINT32 Reserved:16;\r | |
1010 | } Bits;\r | |
1011 | ///\r | |
1012 | /// All bit fields as a 32-bit value\r | |
1013 | ///\r | |
1014 | UINT32 Uint32;\r | |
1015 | } CPUID_MONITOR_MWAIT_EBX;\r | |
1016 | \r | |
1017 | /**\r | |
1018 | CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf\r | |
1019 | #CPUID_MONITOR_MWAIT.\r | |
1020 | **/\r | |
1021 | typedef union {\r | |
1022 | ///\r | |
1023 | /// Individual bit fields\r | |
1024 | ///\r | |
1025 | struct {\r | |
1026 | ///\r | |
1027 | /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,\r | |
1028 | /// and EDX are valid.\r | |
1029 | ///\r | |
1030 | UINT32 ExtensionsSupported:1;\r | |
1031 | ///\r | |
1032 | /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when\r | |
1033 | /// interrupts disabled.\r | |
1034 | ///\r | |
1035 | UINT32 InterruptAsBreak:1;\r | |
1036 | UINT32 Reserved:30;\r | |
1037 | } Bits;\r | |
1038 | ///\r | |
1039 | /// All bit fields as a 32-bit value\r | |
1040 | ///\r | |
1041 | UINT32 Uint32;\r | |
1042 | } CPUID_MONITOR_MWAIT_ECX;\r | |
1043 | \r | |
1044 | /**\r | |
1045 | CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf\r | |
1046 | #CPUID_MONITOR_MWAIT.\r | |
1047 | \r | |
1048 | @note\r | |
1049 | The definition of C0 through C7 states for MWAIT extension are\r | |
1050 | processor-specific C-states, not ACPI C-states.\r | |
1051 | **/\r | |
1052 | typedef union {\r | |
1053 | ///\r | |
1054 | /// Individual bit fields\r | |
1055 | ///\r | |
1056 | struct {\r | |
1057 | ///\r | |
1058 | /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.\r | |
1059 | ///\r | |
1060 | UINT32 C0States:4;\r | |
1061 | ///\r | |
1062 | /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.\r | |
1063 | ///\r | |
1064 | UINT32 C1States:4;\r | |
1065 | ///\r | |
1066 | /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.\r | |
1067 | ///\r | |
1068 | UINT32 C2States:4;\r | |
1069 | ///\r | |
1070 | /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.\r | |
1071 | ///\r | |
1072 | UINT32 C3States:4;\r | |
1073 | ///\r | |
1074 | /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.\r | |
1075 | ///\r | |
1076 | UINT32 C4States:4;\r | |
1077 | ///\r | |
1078 | /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.\r | |
1079 | ///\r | |
1080 | UINT32 C5States:4;\r | |
1081 | ///\r | |
1082 | /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.\r | |
1083 | ///\r | |
1084 | UINT32 C6States:4;\r | |
1085 | ///\r | |
1086 | /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.\r | |
1087 | ///\r | |
1088 | UINT32 C7States:4;\r | |
1089 | } Bits;\r | |
1090 | ///\r | |
1091 | /// All bit fields as a 32-bit value\r | |
1092 | ///\r | |
1093 | UINT32 Uint32;\r | |
1094 | } CPUID_MONITOR_MWAIT_EDX;\r | |
1095 | \r | |
1096 | \r | |
1097 | /**\r | |
1098 | CPUID Thermal and Power Management\r | |
1099 | \r | |
1100 | @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)\r | |
1101 | \r | |
1102 | @retval EAX Thermal and power management features described by the type\r | |
1103 | CPUID_THERMAL_POWER_MANAGEMENT_EAX.\r | |
1104 | @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor\r | |
1105 | described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.\r | |
1106 | @retval ECX Performance features described by the type\r | |
1107 | CPUID_THERMAL_POWER_MANAGEMENT_ECX.\r | |
1108 | @retval EDX Reserved.\r | |
1109 | \r | |
1110 | <b>Example usage</b>\r | |
1111 | @code\r | |
1112 | CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;\r | |
1113 | CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;\r | |
1114 | CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;\r | |
1115 | \r | |
1116 | AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r | |
1117 | @endcode\r | |
1118 | **/\r | |
1119 | #define CPUID_THERMAL_POWER_MANAGEMENT 0x06\r | |
1120 | \r | |
1121 | /**\r | |
1122 | CPUID Thermal and Power Management Information returned in EAX for CPUID leaf\r | |
1123 | #CPUID_THERMAL_POWER_MANAGEMENT.\r | |
1124 | **/\r | |
1125 | typedef union {\r | |
1126 | ///\r | |
1127 | /// Individual bit fields\r | |
1128 | ///\r | |
1129 | struct {\r | |
1130 | ///\r | |
1131 | /// [Bit 0] Digital temperature sensor is supported if set.\r | |
1132 | ///\r | |
1133 | UINT32 DigitalTemperatureSensor:1;\r | |
1134 | ///\r | |
1135 | /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).\r | |
1136 | ///\r | |
1137 | UINT32 TurboBoostTechnology:1;\r | |
1138 | ///\r | |
1139 | /// [Bit 2] APIC-Timer-always-running feature is supported if set.\r | |
1140 | ///\r | |
1141 | UINT32 ARAT:1;\r | |
1142 | UINT32 Reserved1:1;\r | |
1143 | ///\r | |
1144 | /// [Bit 4] Power limit notification controls are supported if set.\r | |
1145 | ///\r | |
1146 | UINT32 PLN:1;\r | |
1147 | ///\r | |
1148 | /// [Bit 5] Clock modulation duty cycle extension is supported if set.\r | |
1149 | ///\r | |
1150 | UINT32 ECMD:1;\r | |
1151 | ///\r | |
1152 | /// [Bit 6] Package thermal management is supported if set.\r | |
1153 | ///\r | |
1154 | UINT32 PTM:1;\r | |
1155 | ///\r | |
1156 | /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,\r | |
1157 | /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.\r | |
1158 | ///\r | |
1159 | UINT32 HWP:1;\r | |
1160 | ///\r | |
1161 | /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.\r | |
1162 | ///\r | |
1163 | UINT32 HWP_Notification:1;\r | |
1164 | ///\r | |
1165 | /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.\r | |
1166 | ///\r | |
1167 | UINT32 HWP_Activity_Window:1;\r | |
1168 | ///\r | |
1169 | /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.\r | |
1170 | ///\r | |
1171 | UINT32 HWP_Energy_Performance_Preference:1;\r | |
1172 | ///\r | |
1173 | /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.\r | |
1174 | ///\r | |
1175 | UINT32 HWP_Package_Level_Request:1;\r | |
1176 | UINT32 Reserved2:1;\r | |
1177 | ///\r | |
1178 | /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,\r | |
1179 | /// IA32_THREAD_STALL MSRs are supported if set.\r | |
1180 | ///\r | |
1181 | UINT32 HDC:1;\r | |
1182 | UINT32 Reserved3:18;\r | |
1183 | } Bits;\r | |
1184 | ///\r | |
1185 | /// All bit fields as a 32-bit value\r | |
1186 | ///\r | |
1187 | UINT32 Uint32;\r | |
1188 | } CPUID_THERMAL_POWER_MANAGEMENT_EAX;\r | |
1189 | \r | |
1190 | /**\r | |
1191 | CPUID Thermal and Power Management Information returned in EBX for CPUID leaf\r | |
1192 | #CPUID_THERMAL_POWER_MANAGEMENT.\r | |
1193 | **/\r | |
1194 | typedef union {\r | |
1195 | ///\r | |
1196 | /// Individual bit fields\r | |
1197 | ///\r | |
1198 | struct {\r | |
1199 | ///\r | |
1200 | /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.\r | |
1201 | ///\r | |
1202 | UINT32 InterruptThresholds:4;\r | |
1203 | UINT32 Reserved:28;\r | |
1204 | } Bits;\r | |
1205 | ///\r | |
1206 | /// All bit fields as a 32-bit value\r | |
1207 | ///\r | |
1208 | UINT32 Uint32;\r | |
1209 | } CPUID_THERMAL_POWER_MANAGEMENT_EBX;\r | |
1210 | \r | |
1211 | /**\r | |
1212 | CPUID Thermal and Power Management Information returned in ECX for CPUID leaf\r | |
1213 | #CPUID_THERMAL_POWER_MANAGEMENT.\r | |
1214 | **/\r | |
1215 | typedef union {\r | |
1216 | ///\r | |
1217 | /// Individual bit fields\r | |
1218 | ///\r | |
1219 | struct {\r | |
1220 | ///\r | |
1221 | /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF\r | |
1222 | /// and IA32_APERF). The capability to provide a measure of delivered\r | |
1223 | /// processor performance (since last reset of the counters), as a percentage\r | |
1224 | /// of the expected processor performance when running at the TSC frequency.\r | |
1225 | ///\r | |
1226 | UINT32 HardwareCoordinationFeedback:1;\r | |
1227 | UINT32 Reserved1:2;\r | |
1228 | ///\r | |
1229 | /// [Bit 3] If this bit is set, then the processor supports performance-energy\r | |
1230 | /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS\r | |
1231 | /// (1B0H).\r | |
1232 | ///\r | |
1233 | UINT32 PerformanceEnergyBias:1;\r | |
1234 | UINT32 Reserved2:28;\r | |
1235 | } Bits;\r | |
1236 | ///\r | |
1237 | /// All bit fields as a 32-bit value\r | |
1238 | ///\r | |
1239 | UINT32 Uint32;\r | |
1240 | } CPUID_THERMAL_POWER_MANAGEMENT_ECX;\r | |
1241 | \r | |
1242 | \r | |
1243 | /**\r | |
1244 | CPUID Structured Extended Feature Flags Enumeration\r | |
1245 | \r | |
1246 | @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)\r | |
1247 | @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).\r | |
1248 | \r | |
1249 | @note\r | |
1250 | If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf\r | |
1251 | index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.\r | |
1252 | \r | |
1253 | @retval EAX The maximum input value for ECX to retrieve sub-leaf information.\r | |
1254 | @retval EBX Structured Extended Feature Flags described by the type\r | |
1255 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.\r | |
1256 | @retval EBX Structured Extended Feature Flags described by the type\r | |
1257 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.\r | |
1258 | @retval EDX Reserved.\r | |
1259 | \r | |
1260 | <b>Example usage</b>\r | |
1261 | @code\r | |
1262 | UINT32 Eax;\r | |
1263 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r | |
1264 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;\r | |
1265 | UINT32 SubLeaf;\r | |
1266 | \r | |
1267 | AsmCpuidEx (\r | |
1268 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r | |
1269 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r | |
1270 | &Eax, NULL, NULL, NULL\r | |
1271 | );\r | |
1272 | for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {\r | |
1273 | AsmCpuidEx (\r | |
1274 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r | |
1275 | SubLeaf,\r | |
1276 | NULL, &Ebx.Uint32, &Ecx.Uint32, NULL\r | |
1277 | );\r | |
1278 | SubLeaf++;\r | |
1279 | } while (SubLeaf <= Eax);\r | |
1280 | @endcode\r | |
1281 | **/\r | |
1282 | #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07\r | |
1283 | \r | |
1284 | ///\r | |
1285 | /// CPUID Structured Extended Feature Flags Enumeration sub-leaf\r | |
1286 | ///\r | |
1287 | #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00\r | |
1288 | \r | |
1289 | /**\r | |
1290 | CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf\r | |
1291 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf\r | |
1292 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.\r | |
1293 | **/\r | |
1294 | typedef union {\r | |
1295 | ///\r | |
1296 | /// Individual bit fields\r | |
1297 | ///\r | |
1298 | struct {\r | |
1299 | ///\r | |
1300 | /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.\r | |
1301 | ///\r | |
1302 | UINT32 FSGSBASE:1;\r | |
1303 | ///\r | |
1304 | /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.\r | |
1305 | ///\r | |
1306 | UINT32 IA32_TSC_ADJUST:1;\r | |
c606a9a5 JF |
1307 | ///\r |
1308 | /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT\r | |
1309 | /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".\r | |
1310 | ///\r | |
1311 | UINT32 SGX:1;\r | |
57d16ba1 MK |
1312 | ///\r |
1313 | /// [Bit 3] If 1 indicates the processor supports the first group of advanced\r | |
1314 | /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)\r | |
1315 | ///\r | |
1316 | UINT32 BMI1:1;\r | |
1317 | ///\r | |
1318 | /// [Bit 4] Hardware Lock Elision\r | |
1319 | ///\r | |
1320 | UINT32 HLE:1;\r | |
1321 | ///\r | |
1322 | /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.\r | |
1323 | ///\r | |
1324 | UINT32 AVX2:1;\r | |
1325 | ///\r | |
1326 | /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.\r | |
1327 | ///\r | |
1328 | UINT32 FDP_EXCPTN_ONLY:1;\r | |
1329 | ///\r | |
1330 | /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.\r | |
1331 | ///\r | |
1332 | UINT32 SMEP:1;\r | |
1333 | ///\r | |
1334 | /// [Bit 8] If 1 indicates the processor supports the second group of\r | |
1335 | /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,\r | |
1336 | /// SARX, SHLX, SHRX)\r | |
1337 | ///\r | |
1338 | UINT32 BMI2:1;\r | |
1339 | ///\r | |
1340 | /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.\r | |
1341 | ///\r | |
1342 | UINT32 EnhancedRepMovsbStosb:1;\r | |
1343 | ///\r | |
1344 | /// [Bit 10] If 1, supports INVPCID instruction for system software that\r | |
1345 | /// manages process-context identifiers.\r | |
1346 | ///\r | |
1347 | UINT32 INVPCID:1;\r | |
1348 | ///\r | |
1349 | /// [Bit 11] Restricted Transactional Memory\r | |
1350 | ///\r | |
1351 | UINT32 RTM:1;\r | |
1352 | ///\r | |
1353 | /// [Bit 12] Supports Platform Quality of Service Monitoring (PQM)\r | |
1354 | /// capability if 1.\r | |
1355 | ///\r | |
1356 | UINT32 PQM:1;\r | |
1357 | ///\r | |
1358 | /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.\r | |
1359 | ///\r | |
1360 | UINT32 DeprecateFpuCsDs:1;\r | |
1361 | ///\r | |
1362 | /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.\r | |
1363 | ///\r | |
1364 | UINT32 MPX:1;\r | |
1365 | ///\r | |
1366 | /// [Bit 15] Supports Platform Quality of Service Enforcement (PQE)\r | |
1367 | /// capability if 1.\r | |
1368 | ///\r | |
1369 | UINT32 PQE:1;\r | |
1370 | UINT32 Reserved2:2;\r | |
1371 | ///\r | |
1372 | /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.\r | |
1373 | ///\r | |
1374 | UINT32 RDSEED:1;\r | |
1375 | ///\r | |
1376 | /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX\r | |
1377 | /// instructions.\r | |
1378 | ///\r | |
1379 | UINT32 ADX:1;\r | |
1380 | ///\r | |
1381 | /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC\r | |
1382 | /// instructions) if 1.\r | |
1383 | ///\r | |
1384 | UINT32 SMAP:1;\r | |
1385 | UINT32 Reserved3:2;\r | |
1386 | ///\r | |
1387 | /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.\r | |
1388 | ///\r | |
1389 | UINT32 CLFLUSHOPT:1;\r | |
1390 | UINT32 Reserved4:1;\r | |
1391 | ///\r | |
1392 | /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace\r | |
1393 | /// extensions.\r | |
1394 | ///\r | |
1395 | UINT32 IntelProcessorTrace:1;\r | |
1396 | UINT32 Reserved5:6;\r | |
1397 | } Bits;\r | |
1398 | ///\r | |
1399 | /// All bit fields as a 32-bit value\r | |
1400 | ///\r | |
1401 | UINT32 Uint32;\r | |
1402 | } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;\r | |
1403 | \r | |
1404 | /**\r | |
1405 | CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf\r | |
1406 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf\r | |
1407 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.\r | |
1408 | **/\r | |
1409 | typedef union {\r | |
1410 | ///\r | |
1411 | /// Individual bit fields\r | |
1412 | ///\r | |
1413 | struct {\r | |
1414 | ///\r | |
1415 | /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.\r | |
1416 | ///\r | |
1417 | UINT32 PREFETCHWT1:1;\r | |
1418 | UINT32 Reserved1:2;\r | |
1419 | ///\r | |
1420 | /// [Bit 3] Supports protection keys for user-mode pages if 1.\r | |
1421 | ///\r | |
1422 | UINT32 PKU:1;\r | |
1423 | ///\r | |
1424 | /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the\r | |
1425 | /// RDPKRU/WRPKRU instructions).\r | |
1426 | ///\r | |
1427 | UINT32 OSPKE:1;\r | |
1428 | UINT32 Reserved2:27;\r | |
1429 | } Bits;\r | |
1430 | ///\r | |
1431 | /// All bit fields as a 32-bit value\r | |
1432 | ///\r | |
1433 | UINT32 Uint32;\r | |
1434 | } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;\r | |
1435 | \r | |
1436 | \r | |
1437 | /**\r | |
1438 | CPUID Direct Cache Access Information\r | |
1439 | \r | |
1440 | @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)\r | |
1441 | \r | |
1442 | @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).\r | |
1443 | @retval EBX Reserved.\r | |
1444 | @retval ECX Reserved.\r | |
1445 | @retval EDX Reserved.\r | |
1446 | \r | |
1447 | <b>Example usage</b>\r | |
1448 | @code\r | |
1449 | UINT32 Eax;\r | |
1450 | \r | |
1451 | AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);\r | |
1452 | @endcode\r | |
1453 | **/\r | |
1454 | #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09\r | |
1455 | \r | |
1456 | \r | |
1457 | /**\r | |
1458 | CPUID Architectural Performance Monitoring\r | |
1459 | \r | |
1460 | @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)\r | |
1461 | \r | |
1462 | @retval EAX Architectural Performance Monitoring information described by\r | |
1463 | the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.\r | |
1464 | @retval EBX Architectural Performance Monitoring information described by\r | |
1465 | the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.\r | |
1466 | @retval ECX Reserved.\r | |
1467 | @retval EDX Architectural Performance Monitoring information described by\r | |
1468 | the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.\r | |
1469 | \r | |
1470 | <b>Example usage</b>\r | |
1471 | @code\r | |
1472 | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;\r | |
1473 | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;\r | |
1474 | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;\r | |
1475 | \r | |
1476 | AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);\r | |
1477 | @endcode\r | |
1478 | **/\r | |
1479 | #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A\r | |
1480 | \r | |
1481 | /**\r | |
1482 | CPUID Architectural Performance Monitoring EAX for CPUID leaf\r | |
1483 | #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r | |
1484 | **/\r | |
1485 | typedef union {\r | |
1486 | ///\r | |
1487 | /// Individual bit fields\r | |
1488 | ///\r | |
1489 | struct {\r | |
1490 | ///\r | |
1491 | /// [Bit 7:0] Version ID of architectural performance monitoring.\r | |
1492 | ///\r | |
1493 | UINT32 ArchPerfMonVerID:8;\r | |
1494 | ///\r | |
1495 | /// [Bits 15:8] Number of general-purpose performance monitoring counter\r | |
1496 | /// per logical processor.\r | |
1497 | ///\r | |
1498 | /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous\r | |
1499 | /// block of MSR address space. Each performance event select register is\r | |
1500 | /// paired with a corresponding performance counter in the 0C1H address\r | |
1501 | /// block.\r | |
1502 | ///\r | |
1503 | UINT32 PerformanceMonitorCounters:8;\r | |
1504 | ///\r | |
1505 | /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.\r | |
1506 | ///\r | |
1507 | /// The bit width of an IA32_PMCx MSR. This the number of valid bits for\r | |
1508 | /// read operation. On write operations, the lower-order 32 bits of the MSR\r | |
1509 | /// may be written with any value, and the high-order bits are sign-extended\r | |
1510 | /// from the value of bit 31.\r | |
1511 | ///\r | |
1512 | UINT32 PerformanceMonitorCounterWidth:8;\r | |
1513 | ///\r | |
1514 | /// [Bits 31:24] Length of EBX bit vector to enumerate architectural\r | |
1515 | /// performance monitoring events.\r | |
1516 | ///\r | |
1517 | UINT32 EbxBitVectorLength:8;\r | |
1518 | } Bits;\r | |
1519 | ///\r | |
1520 | /// All bit fields as a 32-bit value\r | |
1521 | ///\r | |
1522 | UINT32 Uint32;\r | |
1523 | } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;\r | |
1524 | \r | |
1525 | /**\r | |
1526 | CPUID Architectural Performance Monitoring EBX for CPUID leaf\r | |
1527 | #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r | |
1528 | **/\r | |
1529 | typedef union {\r | |
1530 | ///\r | |
1531 | /// Individual bit fields\r | |
1532 | ///\r | |
1533 | struct {\r | |
1534 | ///\r | |
1535 | /// [Bit 0] Core cycle event not available if 1.\r | |
1536 | ///\r | |
1537 | UINT32 UnhaltedCoreCycles:1;\r | |
1538 | ///\r | |
1539 | /// [Bit 1] Instruction retired event not available if 1.\r | |
1540 | ///\r | |
1541 | UINT32 InstructionsRetired:1;\r | |
1542 | ///\r | |
1543 | /// [Bit 2] Reference cycles event not available if 1.\r | |
1544 | ///\r | |
1545 | UINT32 UnhaltedReferenceCycles:1;\r | |
1546 | ///\r | |
1547 | /// [Bit 3] Last-level cache reference event not available if 1.\r | |
1548 | ///\r | |
1549 | UINT32 LastLevelCacheReferences:1;\r | |
1550 | ///\r | |
1551 | /// [Bit 4] Last-level cache misses event not available if 1.\r | |
1552 | ///\r | |
1553 | UINT32 LastLevelCacheMisses:1;\r | |
1554 | ///\r | |
1555 | /// [Bit 5] Branch instruction retired event not available if 1.\r | |
1556 | ///\r | |
1557 | UINT32 BranchInstructionsRetired:1;\r | |
1558 | ///\r | |
1559 | /// [Bit 6] Branch mispredict retired event not available if 1.\r | |
1560 | ///\r | |
1561 | UINT32 AllBranchMispredictRetired:1;\r | |
1562 | UINT32 Reserved:25;\r | |
1563 | } Bits;\r | |
1564 | ///\r | |
1565 | /// All bit fields as a 32-bit value\r | |
1566 | ///\r | |
1567 | UINT32 Uint32;\r | |
1568 | } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;\r | |
1569 | \r | |
1570 | /**\r | |
1571 | CPUID Architectural Performance Monitoring EDX for CPUID leaf\r | |
1572 | #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r | |
1573 | **/\r | |
1574 | typedef union {\r | |
1575 | ///\r | |
1576 | /// Individual bit fields\r | |
1577 | ///\r | |
1578 | struct {\r | |
1579 | ///\r | |
1580 | /// [Bits 4:0] Number of fixed-function performance counters\r | |
1581 | /// (if Version ID > 1).\r | |
1582 | ///\r | |
1583 | UINT32 FixedFunctionPerformanceCounters:5;\r | |
1584 | ///\r | |
1585 | /// [Bits 12:5] Bit width of fixed-function performance counters\r | |
1586 | /// (if Version ID > 1).\r | |
1587 | ///\r | |
1588 | UINT32 FixedFunctionPerformanceCounterWidth:8;\r | |
1589 | UINT32 Reserved:19;\r | |
1590 | } Bits;\r | |
1591 | ///\r | |
1592 | /// All bit fields as a 32-bit value\r | |
1593 | ///\r | |
1594 | UINT32 Uint32;\r | |
1595 | } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;\r | |
1596 | \r | |
1597 | \r | |
1598 | /**\r | |
1599 | CPUID Extended Topology Information\r | |
1600 | \r | |
1601 | @note\r | |
1602 | Most of Leaf 0BH output depends on the initial value in ECX. The EDX output\r | |
1603 | of leaf 0BH is always valid and does not vary with input value in ECX. Output\r | |
1604 | value in ECX[7:0] always equals input value in ECX[7:0]. For sub-leaves that\r | |
1605 | return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0. If\r | |
1606 | an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],\r | |
1607 | other input values with ECX > n also return 0 in ECX[15:8].\r | |
1608 | \r | |
1609 | @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)\r | |
1610 | @param ECX Level number\r | |
1611 | \r | |
1612 | @retval EAX Extended topology information described by the type\r | |
1613 | CPUID_EXTENDED_TOPOLOGY_EAX.\r | |
1614 | @retval EBX Extended topology information described by the type\r | |
1615 | CPUID_EXTENDED_TOPOLOGY_EBX.\r | |
1616 | @retval ECX Extended topology information described by the type\r | |
1617 | CPUID_EXTENDED_TOPOLOGY_ECX.\r | |
1618 | @retval EDX x2APIC ID the current logical processor.\r | |
1619 | \r | |
1620 | <b>Example usage</b>\r | |
1621 | @code\r | |
1622 | CPUID_EXTENDED_TOPOLOGY_EAX Eax;\r | |
1623 | CPUID_EXTENDED_TOPOLOGY_EBX Ebx;\r | |
1624 | CPUID_EXTENDED_TOPOLOGY_ECX Ecx;\r | |
1625 | UINT32 Edx;\r | |
1626 | UINT32 LevelNumber;\r | |
1627 | \r | |
1628 | LevelNumber = 0;\r | |
1629 | do {\r | |
1630 | AsmCpuidEx (\r | |
1631 | CPUID_EXTENDED_TOPOLOGY, LevelNumber,\r | |
1632 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx\r | |
1633 | );\r | |
1634 | LevelNumber++;\r | |
1635 | } while (Eax.Bits.ApicIdShift != 0);\r | |
1636 | @endcode\r | |
1637 | **/\r | |
1638 | #define CPUID_EXTENDED_TOPOLOGY 0x0B\r | |
1639 | \r | |
1640 | /**\r | |
1641 | CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r | |
1642 | **/\r | |
1643 | typedef union {\r | |
1644 | ///\r | |
1645 | /// Individual bit fields\r | |
1646 | ///\r | |
1647 | struct {\r | |
1648 | ///\r | |
1649 | /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique\r | |
1650 | /// topology ID of the next level type. All logical processors with the\r | |
1651 | /// same next level ID share current level.\r | |
1652 | ///\r | |
1653 | /// @note\r | |
1654 | /// Software should use this field (EAX[4:0]) to enumerate processor\r | |
1655 | /// topology of the system.\r | |
1656 | ///\r | |
1657 | UINT32 ApicIdShift:5;\r | |
1658 | UINT32 Reserved:27;\r | |
1659 | } Bits;\r | |
1660 | ///\r | |
1661 | /// All bit fields as a 32-bit value\r | |
1662 | ///\r | |
1663 | UINT32 Uint32;\r | |
1664 | } CPUID_EXTENDED_TOPOLOGY_EAX;\r | |
1665 | \r | |
1666 | /**\r | |
1667 | CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r | |
1668 | **/\r | |
1669 | typedef union {\r | |
1670 | ///\r | |
1671 | /// Individual bit fields\r | |
1672 | ///\r | |
1673 | struct {\r | |
1674 | ///\r | |
1675 | /// [Bits 15:0] Number of logical processors at this level type. The number\r | |
1676 | /// reflects configuration as shipped by Intel.\r | |
1677 | ///\r | |
1678 | /// @note\r | |
1679 | /// Software must not use EBX[15:0] to enumerate processor topology of the\r | |
1680 | /// system. This value in this field (EBX[15:0]) is only intended for\r | |
1681 | /// display/diagnostic purposes. The actual number of logical processors\r | |
1682 | /// available to BIOS/OS/Applications may be different from the value of\r | |
1683 | /// EBX[15:0], depending on software and platform hardware configurations.\r | |
1684 | ///\r | |
1685 | UINT32 LogicalProcessors:16;\r | |
1686 | UINT32 Reserved:16;\r | |
1687 | } Bits;\r | |
1688 | ///\r | |
1689 | /// All bit fields as a 32-bit value\r | |
1690 | ///\r | |
1691 | UINT32 Uint32;\r | |
1692 | } CPUID_EXTENDED_TOPOLOGY_EBX;\r | |
1693 | \r | |
1694 | /**\r | |
1695 | CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r | |
1696 | **/\r | |
1697 | typedef union {\r | |
1698 | ///\r | |
1699 | /// Individual bit fields\r | |
1700 | ///\r | |
1701 | struct {\r | |
1702 | ///\r | |
1703 | /// [Bits 7:0] Level number. Same value in ECX input.\r | |
1704 | ///\r | |
1705 | UINT32 LevelNumber:8;\r | |
1706 | ///\r | |
1707 | /// [Bits 15:8] Level type.\r | |
1708 | ///\r | |
1709 | /// @note\r | |
1710 | /// The value of the "level type" field is not related to level numbers in\r | |
1711 | /// any way, higher "level type" values do not mean higher levels.\r | |
1712 | ///\r | |
1713 | UINT32 LevelType:8;\r | |
1714 | UINT32 Reserved:16;\r | |
1715 | } Bits;\r | |
1716 | ///\r | |
1717 | /// All bit fields as a 32-bit value\r | |
1718 | ///\r | |
1719 | UINT32 Uint32;\r | |
1720 | } CPUID_EXTENDED_TOPOLOGY_ECX;\r | |
1721 | \r | |
1722 | ///\r | |
1723 | /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType\r | |
1724 | ///\r | |
1725 | #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00\r | |
1726 | #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01\r | |
1727 | #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02\r | |
1728 | ///\r | |
1729 | /// @}\r | |
1730 | ///\r | |
1731 | \r | |
1732 | \r | |
1733 | /**\r | |
1734 | CPUID Extended State Information\r | |
1735 | \r | |
1736 | @param EAX CPUID_EXTENDED_STATE (0x0D)\r | |
1737 | @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).\r | |
1738 | CPUID_EXTENDED_STATE_SUB_LEAF (0x01).\r | |
1739 | CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).\r | |
1740 | Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.\r | |
1741 | **/\r | |
1742 | #define CPUID_EXTENDED_STATE 0x0D\r | |
1743 | \r | |
1744 | /**\r | |
1745 | CPUID Extended State Information Main Leaf\r | |
1746 | \r | |
1747 | @param EAX CPUID_EXTENDED_STATE (0x0D)\r | |
1748 | @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)\r | |
1749 | \r | |
1750 | @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]\r | |
1751 | can be set to 1 only if EAX[n] is 1. The format of the extended\r | |
1752 | state main leaf is described by the type\r | |
1753 | CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.\r | |
1754 | @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r | |
1755 | area) required by enabled features in XCR0. May be different than\r | |
1756 | ECX if some features at the end of the XSAVE save area are not\r | |
1757 | enabled.\r | |
1758 | @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r | |
1759 | area) of the XSAVE/XRSTOR save area required by all supported\r | |
1760 | features in the processor, i.e all the valid bit fields in XCR0.\r | |
1761 | @retval EDX Reports the supported bits of the upper 32 bits of XCR0.\r | |
1762 | XCR0[n+32] can be set to 1 only if EDX[n] is 1.\r | |
1763 | \r | |
1764 | <b>Example usage</b>\r | |
1765 | @code\r | |
1766 | CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;\r | |
1767 | UINT32 Ebx;\r | |
1768 | UINT32 Ecx;\r | |
1769 | UINT32 Edx;\r | |
1770 | \r | |
1771 | AsmCpuidEx (\r | |
1772 | CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,\r | |
1773 | &Eax.Uint32, &Ebx, &Ecx, &Edx\r | |
1774 | );\r | |
1775 | @endcode\r | |
1776 | **/\r | |
1777 | #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00\r | |
1778 | \r | |
1779 | /**\r | |
1780 | CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r | |
1781 | sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.\r | |
1782 | **/\r | |
1783 | typedef union {\r | |
1784 | ///\r | |
1785 | /// Individual bit fields\r | |
1786 | ///\r | |
1787 | struct {\r | |
1788 | ///\r | |
1789 | /// [Bit 0] x87 state.\r | |
1790 | ///\r | |
1791 | UINT32 x87:1;\r | |
1792 | ///\r | |
1793 | /// [Bit 1] SSE state.\r | |
1794 | ///\r | |
1795 | UINT32 SSE:1;\r | |
1796 | ///\r | |
1797 | /// [Bit 2] AVX state.\r | |
1798 | ///\r | |
1799 | UINT32 AVX:1;\r | |
1800 | ///\r | |
1801 | /// [Bits 4:3] MPX state.\r | |
1802 | ///\r | |
1803 | UINT32 MPX:2;\r | |
1804 | ///\r | |
1805 | /// [Bits 7:5] AVX-512 state.\r | |
1806 | ///\r | |
1807 | UINT32 AVX_512:3;\r | |
1808 | ///\r | |
1809 | /// [Bit 8] Used for IA32_XSS.\r | |
1810 | ///\r | |
1811 | UINT32 IA32_XSS:1;\r | |
1812 | ///\r | |
1813 | /// [Bit 9] PKRU state.\r | |
1814 | ///\r | |
1815 | UINT32 PKRU:1;\r | |
1816 | UINT32 Reserved:22;\r | |
1817 | } Bits;\r | |
1818 | ///\r | |
1819 | /// All bit fields as a 32-bit value\r | |
1820 | ///\r | |
1821 | UINT32 Uint32;\r | |
1822 | } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;\r | |
1823 | \r | |
1824 | /**\r | |
1825 | CPUID Extended State Information Sub Leaf\r | |
1826 | \r | |
1827 | @param EAX CPUID_EXTENDED_STATE (0x0D)\r | |
1828 | @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)\r | |
1829 | \r | |
1830 | @retval EAX The format of the extended state sub-leaf is described by the\r | |
1831 | type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.\r | |
1832 | @retval EBX The size in bytes of the XSAVE area containing all states\r | |
1833 | enabled by XCRO | IA32_XSS.\r | |
1834 | @retval ECX The format of the extended state sub-leaf is described by the\r | |
1835 | type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.\r | |
1836 | @retval EDX Reports the supported bits of the upper 32 bits of the\r | |
1837 | IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.\r | |
1838 | \r | |
1839 | <b>Example usage</b>\r | |
1840 | @code\r | |
1841 | CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;\r | |
1842 | UINT32 Ebx;\r | |
1843 | CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;\r | |
1844 | UINT32 Edx;\r | |
1845 | \r | |
1846 | AsmCpuidEx (\r | |
1847 | CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,\r | |
1848 | &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx\r | |
1849 | );\r | |
1850 | @endcode\r | |
1851 | **/\r | |
1852 | #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01\r | |
1853 | \r | |
1854 | /**\r | |
1855 | CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r | |
1856 | sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.\r | |
1857 | **/\r | |
1858 | typedef union {\r | |
1859 | ///\r | |
1860 | /// Individual bit fields\r | |
1861 | ///\r | |
1862 | struct {\r | |
1863 | ///\r | |
1864 | /// [Bit 0] XSAVEOPT is available.\r | |
1865 | ///\r | |
1866 | UINT32 XSAVEOPT:1;\r | |
1867 | ///\r | |
1868 | /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.\r | |
1869 | ///\r | |
1870 | UINT32 XSAVEC:1;\r | |
1871 | ///\r | |
1872 | /// [Bit 2] Supports XGETBV with ECX = 1 if set.\r | |
1873 | ///\r | |
1874 | UINT32 XGETBV:1;\r | |
1875 | ///\r | |
1876 | /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.\r | |
1877 | ///\r | |
1878 | UINT32 XSAVES:1;\r | |
1879 | UINT32 Reserved:28;\r | |
1880 | } Bits;\r | |
1881 | ///\r | |
1882 | /// All bit fields as a 32-bit value\r | |
1883 | ///\r | |
1884 | UINT32 Uint32;\r | |
1885 | } CPUID_EXTENDED_STATE_SUB_LEAF_EAX;\r | |
1886 | \r | |
1887 | /**\r | |
1888 | CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r | |
1889 | sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.\r | |
1890 | **/\r | |
1891 | typedef union {\r | |
1892 | ///\r | |
1893 | /// Individual bit fields\r | |
1894 | ///\r | |
1895 | struct {\r | |
1896 | ///\r | |
1897 | /// [Bits 7:0] Used for XCR0.\r | |
1898 | ///\r | |
1899 | UINT32 XCR0:1;\r | |
1900 | ///\r | |
1901 | /// [Bit 8] PT STate.\r | |
1902 | ///\r | |
1903 | UINT32 PT:1;\r | |
1904 | ///\r | |
1905 | /// [Bit 9] Used for XCR0.\r | |
1906 | ///\r | |
1907 | UINT32 XCR0_1:1;\r | |
1908 | UINT32 Reserved:22;\r | |
1909 | } Bits;\r | |
1910 | ///\r | |
1911 | /// All bit fields as a 32-bit value\r | |
1912 | ///\r | |
1913 | UINT32 Uint32;\r | |
1914 | } CPUID_EXTENDED_STATE_SUB_LEAF_ECX;\r | |
1915 | \r | |
1916 | /**\r | |
1917 | CPUID Extended State Information Size and Offset Sub Leaf\r | |
1918 | \r | |
1919 | @note\r | |
1920 | Leaf 0DH output depends on the initial value in ECX.\r | |
1921 | Each sub-leaf index (starting at position 2) is supported if it corresponds to\r | |
1922 | a supported bit in either the XCR0 register or the IA32_XSS MSR.\r | |
1923 | If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf\r | |
1924 | n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1\r | |
1925 | returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0\r | |
1926 | returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].\r | |
1927 | \r | |
1928 | @param EAX CPUID_EXTENDED_STATE (0x0D)\r | |
1929 | @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based\r | |
1930 | on supported bits in XCR0 or IA32_XSS_MSR.\r | |
1931 | \r | |
1932 | @retval EAX The size in bytes (from the offset specified in EBX) of the save\r | |
1933 | area for an extended state feature associated with a valid\r | |
1934 | sub-leaf index, n.\r | |
1935 | @retval EBX The offset in bytes of this extended state component's save area\r | |
1936 | from the beginning of the XSAVE/XRSTOR area. This field reports\r | |
1937 | 0 if the sub-leaf index, n, does not map to a valid bit in the\r | |
1938 | XCR0 register.\r | |
1939 | @retval ECX The format of the extended state components's save area as\r | |
1940 | described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.\r | |
1941 | This field reports 0 if the sub-leaf index, n, is invalid.\r | |
1942 | @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;\r | |
1943 | otherwise it is reserved.\r | |
1944 | \r | |
1945 | <b>Example usage</b>\r | |
1946 | @code\r | |
1947 | UINT32 Eax;\r | |
1948 | UINT32 Ebx;\r | |
1949 | CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;\r | |
1950 | UINT32 Edx;\r | |
1951 | UINTN SubLeaf;\r | |
1952 | \r | |
1953 | for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {\r | |
1954 | AsmCpuidEx (\r | |
1955 | CPUID_EXTENDED_STATE, SubLeaf,\r | |
1956 | &Eax, &Ebx, &Ecx.Uint32, &Edx\r | |
1957 | );\r | |
1958 | }\r | |
1959 | @endcode\r | |
1960 | **/\r | |
1961 | #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02\r | |
1962 | \r | |
1963 | /**\r | |
1964 | CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r | |
1965 | sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.\r | |
1966 | **/\r | |
1967 | typedef union {\r | |
1968 | ///\r | |
1969 | /// Individual bit fields\r | |
1970 | ///\r | |
1971 | struct {\r | |
1972 | ///\r | |
1973 | /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is\r | |
1974 | /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported\r | |
1975 | /// in XCR0.\r | |
1976 | ///\r | |
1977 | UINT32 XSS:1;\r | |
1978 | ///\r | |
1979 | /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,\r | |
1980 | /// this extended state component located on the next 64-byte boundary\r | |
1981 | /// following the preceding state component (otherwise, it is located\r | |
1982 | /// immediately following the preceding state component).\r | |
1983 | ///\r | |
1984 | UINT32 Compacted:1;\r | |
1985 | UINT32 Reserved:30;\r | |
1986 | } Bits;\r | |
1987 | ///\r | |
1988 | /// All bit fields as a 32-bit value\r | |
1989 | ///\r | |
1990 | UINT32 Uint32;\r | |
1991 | } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;\r | |
1992 | \r | |
1993 | \r | |
1994 | /**\r | |
1995 | CPUID Platform QoS Monitoring Information\r | |
1996 | \r | |
1997 | @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r | |
1998 | @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00).\r | |
1999 | CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01).\r | |
2000 | \r | |
2001 | **/\r | |
2002 | #define CPUID_PLATFORM_QOS_MONITORING 0x0F\r | |
2003 | \r | |
2004 | /**\r | |
2005 | CPUID Platform QoS Monitoring Information Enumeration Sub-leaf\r | |
2006 | \r | |
2007 | @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r | |
2008 | @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00)\r | |
2009 | \r | |
2010 | @retval EAX Reserved.\r | |
2011 | @retval EBX Maximum range (zero-based) of RMID within this physical\r | |
2012 | processor of all types.\r | |
2013 | @retval ECX Reserved.\r | |
2014 | @retval EDX L3 Cache QoS Monitoring Information Enumeration described by the\r | |
2015 | type CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX.\r | |
2016 | \r | |
2017 | <b>Example usage</b>\r | |
2018 | @code\r | |
2019 | UINT32 Ebx;\r | |
2020 | CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r | |
2021 | \r | |
2022 | AsmCpuidEx (\r | |
2023 | CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,\r | |
2024 | NULL, &Ebx, NULL, &Edx.Uint32\r | |
2025 | );\r | |
2026 | @endcode\r | |
2027 | **/\r | |
2028 | #define CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF 0x00\r | |
2029 | \r | |
2030 | /**\r | |
2031 | CPUID Platform QoS Monitoring Information EDX for CPUID leaf\r | |
2032 | #CPUID_PLATFORM_QOS_MONITORING, sub-leaf\r | |
2033 | #CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF.\r | |
2034 | **/\r | |
2035 | typedef union {\r | |
2036 | ///\r | |
2037 | /// Individual bit fields\r | |
2038 | ///\r | |
2039 | struct {\r | |
2040 | UINT32 Reserved1:1;\r | |
2041 | ///\r | |
2042 | /// [Bit 1] Supports L3 Cache QoS Monitoring if 1.\r | |
2043 | ///\r | |
2044 | UINT32 L3CacheQosEnforcement:1;\r | |
2045 | UINT32 Reserved2:30;\r | |
2046 | } Bits;\r | |
2047 | ///\r | |
2048 | /// All bit fields as a 32-bit value\r | |
2049 | ///\r | |
2050 | UINT32 Uint32;\r | |
2051 | } CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r | |
2052 | \r | |
2053 | /**\r | |
2054 | CPUID Platform QoS Monitoring Information Capability Sub-leaf\r | |
2055 | \r | |
2056 | @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r | |
2057 | @param ECX CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01)\r | |
2058 | \r | |
2059 | @retval EAX Reserved.\r | |
2060 | @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).\r | |
2061 | @retval ECX Maximum range (zero-based) of RMID of this resource type.\r | |
2062 | @retval EDX L3 Cache QoS Monitoring Capability information described by the\r | |
2063 | type CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX.\r | |
2064 | \r | |
2065 | <b>Example usage</b>\r | |
2066 | @code\r | |
2067 | UINT32 Ebx;\r | |
2068 | UINT32 Ecx;\r | |
2069 | CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;\r | |
2070 | \r | |
2071 | AsmCpuidEx (\r | |
2072 | CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,\r | |
2073 | NULL, &Ebx, &Ecx, &Edx.Uint32\r | |
2074 | );\r | |
2075 | @endcode\r | |
2076 | **/\r | |
2077 | #define CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF 0x01\r | |
2078 | \r | |
2079 | /**\r | |
2080 | CPUID Platform QoS Monitoring Information Capability EDX for CPUID leaf\r | |
2081 | #CPUID_PLATFORM_QOS_MONITORING, sub-leaf\r | |
2082 | #CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF.\r | |
2083 | **/\r | |
2084 | typedef union {\r | |
2085 | ///\r | |
2086 | /// Individual bit fields\r | |
2087 | ///\r | |
2088 | struct {\r | |
2089 | ///\r | |
2090 | /// [Bit 0] Supports L3 occupancy monitoring if 1.\r | |
2091 | ///\r | |
2092 | UINT32 L3CacheOccupancyMonitoring:1;\r | |
2093 | UINT32 Reserved:31;\r | |
2094 | } Bits;\r | |
2095 | ///\r | |
2096 | /// All bit fields as a 32-bit value\r | |
2097 | ///\r | |
2098 | UINT32 Uint32;\r | |
2099 | } CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX;\r | |
2100 | \r | |
2101 | \r | |
2102 | /**\r | |
2103 | CPUID Platform QoS Enforcement Information\r | |
2104 | \r | |
2105 | @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10).\r | |
2106 | @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).\r | |
2107 | CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x01).\r | |
2108 | Additional sub leafs 1..n based in RESID from sub leaf 0x00.\r | |
2109 | **/\r | |
2110 | #define CPUID_PLATFORM_QOS_ENFORCEMENT 0x10\r | |
2111 | \r | |
2112 | /**\r | |
2113 | CPUID Platform QoS Enforcement Information\r | |
2114 | \r | |
2115 | @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)\r | |
2116 | @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).\r | |
2117 | \r | |
2118 | @retval EAX Reserved.\r | |
2119 | @retval EBX L3 Cache QoS Enforcement information described by the\r | |
2120 | type CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX.\r | |
2121 | @retval ECX Reserved.\r | |
2122 | @retval EDX Reserved.\r | |
2123 | \r | |
2124 | <b>Example usage</b>\r | |
2125 | @code\r | |
2126 | CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;\r | |
2127 | \r | |
2128 | AsmCpuidEx (\r | |
2129 | CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,\r | |
2130 | NULL, &Ebx.Uint32, NULL, NULL\r | |
2131 | );\r | |
2132 | @endcode\r | |
2133 | **/\r | |
2134 | #define CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF 0x00\r | |
2135 | \r | |
2136 | /**\r | |
2137 | CPUID Platform QoS Enforcement Information EBX for CPUID leaf\r | |
2138 | #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r | |
2139 | #CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF.\r | |
2140 | **/\r | |
2141 | typedef union {\r | |
2142 | ///\r | |
2143 | /// Individual bit fields\r | |
2144 | ///\r | |
2145 | struct {\r | |
2146 | UINT32 Reserved1:1;\r | |
2147 | ///\r | |
2148 | /// [Bit 1] Supports L3 Cache QoS Enforcement if 1.\r | |
2149 | ///\r | |
2150 | UINT32 L3CacheQosEnforcement:1;\r | |
2151 | UINT32 Reserved2:30;\r | |
2152 | } Bits;\r | |
2153 | ///\r | |
2154 | /// All bit fields as a 32-bit value\r | |
2155 | ///\r | |
2156 | UINT32 Uint32;\r | |
2157 | } CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX;\r | |
2158 | \r | |
2159 | \r | |
2160 | /**\r | |
2161 | CPUID Platform QoS Enforcement Information\r | |
2162 | \r | |
2163 | @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)\r | |
2164 | @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x00)\r | |
2165 | Additional sub leafs 1..n based in RESID from sub leaf 0x00.\r | |
2166 | \r | |
2167 | @retval EAX RESID L3 Cache3 QoS Enforcement information described by the\r | |
2168 | type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX.\r | |
2169 | @retval EBX Bit-granular map of isolation/contention of allocation units.\r | |
2170 | @retval ECX RESID L3 Cache3 QoS Enforcement information described by the\r | |
2171 | type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX.\r | |
2172 | @retval EDX RESID L3 Cache3 QoS Enforcement information described by the\r | |
2173 | type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX.\r | |
2174 | \r | |
2175 | <b>Example usage</b>\r | |
2176 | @code\r | |
2177 | CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;\r | |
2178 | UINT32 Ebx;\r | |
2179 | CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;\r | |
2180 | CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;\r | |
2181 | \r | |
2182 | AsmCpuidEx (\r | |
2183 | CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,\r | |
2184 | &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r | |
2185 | );\r | |
2186 | @endcode\r | |
2187 | **/\r | |
2188 | #define CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF 0x01\r | |
2189 | \r | |
2190 | /**\r | |
2191 | CPUID Platform QoS Enforcement Information EAX for CPUID leaf\r | |
2192 | #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r | |
2193 | #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r | |
2194 | **/\r | |
2195 | typedef union {\r | |
2196 | ///\r | |
2197 | /// Individual bit fields\r | |
2198 | ///\r | |
2199 | struct {\r | |
2200 | ///\r | |
2201 | /// [Bits 3:0] Length of the capacity bit mask for the corresponding ResID.\r | |
2202 | ///\r | |
2203 | UINT32 CapacityLength:4;\r | |
2204 | UINT32 Reserved:28;\r | |
2205 | } Bits;\r | |
2206 | ///\r | |
2207 | /// All bit fields as a 32-bit value\r | |
2208 | ///\r | |
2209 | UINT32 Uint32;\r | |
2210 | } CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX;\r | |
2211 | \r | |
2212 | /**\r | |
2213 | CPUID Platform QoS Enforcement Information ECX for CPUID leaf\r | |
2214 | #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r | |
2215 | #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r | |
2216 | **/\r | |
2217 | typedef union {\r | |
2218 | ///\r | |
2219 | /// Individual bit fields\r | |
2220 | ///\r | |
2221 | struct {\r | |
2222 | UINT32 Reserved1:1;\r | |
2223 | ///\r | |
2224 | /// [Bit 1] Updates of COS should be infrequent if 1.\r | |
2225 | ///\r | |
2226 | UINT32 CosUpdatesInfrequent:1;\r | |
2227 | ///\r | |
2228 | /// [Bit 2] Code and Data Prioritization Technology supported if 1.\r | |
2229 | ///\r | |
2230 | UINT32 CodeDataPrioritization:1;\r | |
2231 | UINT32 Reserved2:29;\r | |
2232 | } Bits;\r | |
2233 | ///\r | |
2234 | /// All bit fields as a 32-bit value\r | |
2235 | ///\r | |
2236 | UINT32 Uint32;\r | |
2237 | } CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX;\r | |
2238 | \r | |
2239 | /**\r | |
2240 | CPUID Platform QoS Enforcement Information EDX for CPUID leaf\r | |
2241 | #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r | |
2242 | #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r | |
2243 | **/\r | |
2244 | typedef union {\r | |
2245 | ///\r | |
2246 | /// Individual bit fields\r | |
2247 | ///\r | |
2248 | struct {\r | |
2249 | ///\r | |
2250 | /// [Bits 15:0] Highest COS number supported for this ResID.\r | |
2251 | ///\r | |
2252 | UINT32 HighestCosNumber:16;\r | |
2253 | UINT32 Reserved:16;\r | |
2254 | } Bits;\r | |
2255 | ///\r | |
2256 | /// All bit fields as a 32-bit value\r | |
2257 | ///\r | |
2258 | UINT32 Uint32;\r | |
2259 | } CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX;\r | |
2260 | \r | |
2261 | \r | |
c606a9a5 JF |
2262 | /**\r |
2263 | Intel SGX resource capability and configuration.\r | |
2264 | See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".\r | |
2265 | \r | |
2266 | If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying\r | |
2267 | CPUID with EAX=12H on Intel SGX resource capability and configuration.\r | |
2268 | \r | |
2269 | @param EAX CPUID_INTEL_SGX (0x12)\r | |
2270 | @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).\r | |
2271 | CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).\r | |
2272 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).\r | |
2273 | Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])\r | |
2274 | until the sub-leaf type is invalid.\r | |
2275 | \r | |
2276 | **/\r | |
2277 | #define CPUID_INTEL_SGX 0x12\r | |
2278 | \r | |
2279 | /**\r | |
2280 | Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r | |
2281 | Enumerates Intel SGX capability, including enclave instruction opcode support.\r | |
2282 | \r | |
2283 | @param EAX CPUID_INTEL_SGX (0x12)\r | |
2284 | @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)\r | |
2285 | \r | |
2286 | @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r | |
2287 | described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.\r | |
2288 | @retval EBX MISCSELECT: Reports the bit vector of supported extended features\r | |
2289 | that can be written to the MISC region of the SSA.\r | |
2290 | @retval ECX Reserved.\r | |
2291 | @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r | |
2292 | described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.\r | |
2293 | \r | |
2294 | <b>Example usage</b>\r | |
2295 | @code\r | |
2296 | CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;\r | |
2297 | UINT32 Ebx;\r | |
2298 | CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;\r | |
2299 | \r | |
2300 | AsmCpuidEx (\r | |
2301 | CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r | |
2302 | &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r | |
2303 | );\r | |
2304 | @endcode\r | |
2305 | **/\r | |
2306 | #define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00\r | |
2307 | \r | |
2308 | /**\r | |
2309 | Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,\r | |
2310 | sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r | |
2311 | **/\r | |
2312 | typedef union {\r | |
2313 | ///\r | |
2314 | /// Individual bit fields\r | |
2315 | ///\r | |
2316 | struct {\r | |
2317 | ///\r | |
2318 | /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.\r | |
2319 | ///\r | |
2320 | UINT32 SGX1:1;\r | |
2321 | ///\r | |
2322 | /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.\r | |
2323 | ///\r | |
2324 | UINT32 SGX2:1;\r | |
2325 | UINT32 Reserved:30;\r | |
2326 | } Bits;\r | |
2327 | ///\r | |
2328 | /// All bit fields as a 32-bit value\r | |
2329 | ///\r | |
2330 | UINT32 Uint32;\r | |
2331 | } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;\r | |
2332 | \r | |
2333 | /**\r | |
2334 | Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,\r | |
2335 | sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r | |
2336 | **/\r | |
2337 | typedef union {\r | |
2338 | ///\r | |
2339 | /// Individual bit fields\r | |
2340 | ///\r | |
2341 | struct {\r | |
2342 | ///\r | |
2343 | /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes\r | |
2344 | /// when not in 64-bit mode.\r | |
2345 | ///\r | |
2346 | UINT32 MaxEnclaveSize_Not64:8;\r | |
2347 | ///\r | |
2348 | /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes\r | |
2349 | /// when operating in 64-bit mode.\r | |
2350 | ///\r | |
2351 | UINT32 MaxEnclaveSize_64:8;\r | |
2352 | UINT32 Reserved:16;\r | |
2353 | } Bits;\r | |
2354 | ///\r | |
2355 | /// All bit fields as a 32-bit value\r | |
2356 | ///\r | |
2357 | UINT32 Uint32;\r | |
2358 | } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;\r | |
2359 | \r | |
2360 | \r | |
2361 | /**\r | |
2362 | Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r | |
2363 | Enumerates Intel SGX capability of processor state configuration and enclave\r | |
2364 | configuration in the SECS structure.\r | |
2365 | \r | |
2366 | @param EAX CPUID_INTEL_SGX (0x12)\r | |
2367 | @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)\r | |
2368 | \r | |
2369 | @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can\r | |
2370 | set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE\r | |
2371 | only if EAX[n] is 1, where n < 32.\r | |
2372 | @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can\r | |
2373 | set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE\r | |
2374 | only if EBX[n] is 1, where n < 32.\r | |
2375 | @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can\r | |
2376 | set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE\r | |
2377 | only if ECX[n] is 1, where n < 32.\r | |
2378 | @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can\r | |
2379 | set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE\r | |
2380 | only if EDX[n] is 1, where n < 32.\r | |
2381 | \r | |
2382 | <b>Example usage</b>\r | |
2383 | @code\r | |
2384 | UINT32 Eax;\r | |
2385 | UINT32 Ebx;\r | |
2386 | UINT32 Ecx;\r | |
2387 | UINT32 Edx;\r | |
2388 | \r | |
2389 | AsmCpuidEx (\r | |
2390 | CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r | |
2391 | &Eax, &Ebx, &Ecx, &Edx\r | |
2392 | );\r | |
2393 | @endcode\r | |
2394 | **/\r | |
2395 | #define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01\r | |
2396 | \r | |
2397 | \r | |
2398 | /**\r | |
2399 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r | |
2400 | Enumerates available EPC resources.\r | |
2401 | \r | |
2402 | @param EAX CPUID_INTEL_SGX (0x12)\r | |
2403 | @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)\r | |
2404 | \r | |
2405 | @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r | |
2406 | Resources is described by the type\r | |
2407 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.\r | |
2408 | @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r | |
2409 | Resources is described by the type\r | |
2410 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.\r | |
2411 | @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r | |
2412 | Resources is described by the type\r | |
2413 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.\r | |
2414 | @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r | |
2415 | Resources is described by the type\r | |
2416 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.\r | |
2417 | \r | |
2418 | <b>Example usage</b>\r | |
2419 | @code\r | |
2420 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;\r | |
2421 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;\r | |
2422 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;\r | |
2423 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;\r | |
2424 | \r | |
2425 | AsmCpuidEx (\r | |
2426 | CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,\r | |
2427 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r | |
2428 | );\r | |
2429 | @endcode\r | |
2430 | **/\r | |
2431 | #define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02\r | |
2432 | \r | |
2433 | /**\r | |
2434 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID\r | |
2435 | leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r | |
2436 | **/\r | |
2437 | typedef union {\r | |
2438 | ///\r | |
2439 | /// Individual bit fields\r | |
2440 | ///\r | |
2441 | struct {\r | |
2442 | ///\r | |
2443 | /// [Bit 3:0] Sub-leaf-type encoding.\r | |
2444 | /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.\r | |
2445 | /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)\r | |
2446 | /// in EBX:EAX and EDX:ECX.\r | |
2447 | /// All other encoding are reserved.\r | |
2448 | ///\r | |
2449 | UINT32 SubLeafType:4;\r | |
2450 | UINT32 Reserved:8;\r | |
2451 | ///\r | |
2452 | /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of\r | |
2453 | /// the base of the EPC section.\r | |
2454 | ///\r | |
2455 | UINT32 LowAddressOfEpcSection:20;\r | |
2456 | } Bits;\r | |
2457 | ///\r | |
2458 | /// All bit fields as a 32-bit value\r | |
2459 | ///\r | |
2460 | UINT32 Uint32;\r | |
2461 | } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;\r | |
2462 | \r | |
2463 | /**\r | |
2464 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID\r | |
2465 | leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r | |
2466 | **/\r | |
2467 | typedef union {\r | |
2468 | ///\r | |
2469 | /// Individual bit fields\r | |
2470 | ///\r | |
2471 | struct {\r | |
2472 | ///\r | |
2473 | /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of\r | |
2474 | /// the base of the EPC section.\r | |
2475 | ///\r | |
2476 | UINT32 HighAddressOfEpcSection:20;\r | |
2477 | UINT32 Reserved:12;\r | |
2478 | } Bits;\r | |
2479 | ///\r | |
2480 | /// All bit fields as a 32-bit value\r | |
2481 | ///\r | |
2482 | UINT32 Uint32;\r | |
2483 | } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;\r | |
2484 | \r | |
2485 | /**\r | |
2486 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID\r | |
2487 | leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r | |
2488 | **/\r | |
2489 | typedef union {\r | |
2490 | ///\r | |
2491 | /// Individual bit fields\r | |
2492 | ///\r | |
2493 | struct {\r | |
2494 | ///\r | |
2495 | /// [Bit 3:0] The EPC section encoding.\r | |
2496 | /// 0000b: Not valid.\r | |
2497 | /// 0001b: The EPC section is confidentiality, integrity and replay protected.\r | |
2498 | /// All other encoding are reserved.\r | |
2499 | ///\r | |
2500 | UINT32 EpcSection:4;\r | |
2501 | UINT32 Reserved:8;\r | |
2502 | ///\r | |
2503 | /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the\r | |
2504 | /// corresponding EPC section within the Processor Reserved Memory.\r | |
2505 | ///\r | |
2506 | UINT32 LowSizeOfEpcSection:20;\r | |
2507 | } Bits;\r | |
2508 | ///\r | |
2509 | /// All bit fields as a 32-bit value\r | |
2510 | ///\r | |
2511 | UINT32 Uint32;\r | |
2512 | } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;\r | |
2513 | \r | |
2514 | /**\r | |
2515 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID\r | |
2516 | leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r | |
2517 | **/\r | |
2518 | typedef union {\r | |
2519 | ///\r | |
2520 | /// Individual bit fields\r | |
2521 | ///\r | |
2522 | struct {\r | |
2523 | ///\r | |
2524 | /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the\r | |
2525 | /// corresponding EPC section within the Processor Reserved Memory.\r | |
2526 | ///\r | |
2527 | UINT32 HighSizeOfEpcSection:20;\r | |
2528 | UINT32 Reserved:12;\r | |
2529 | } Bits;\r | |
2530 | ///\r | |
2531 | /// All bit fields as a 32-bit value\r | |
2532 | ///\r | |
2533 | UINT32 Uint32;\r | |
2534 | } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;\r | |
2535 | \r | |
2536 | \r | |
57d16ba1 MK |
2537 | /**\r |
2538 | CPUID Intel Processor Trace Information\r | |
2539 | \r | |
2540 | @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)\r | |
2541 | @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).\r | |
2542 | CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).\r | |
2543 | \r | |
2544 | **/\r | |
2545 | #define CPUID_INTEL_PROCESSOR_TRACE 0x14\r | |
2546 | \r | |
2547 | /**\r | |
2548 | CPUID Intel Processor Trace Information Main Leaf\r | |
2549 | \r | |
2550 | @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)\r | |
2551 | @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)\r | |
2552 | \r | |
2553 | @retval EAX Reports the maximum sub-leaf supported in leaf 14H.\r | |
2554 | @retval EBX Returns Intel processor trace information described by the\r | |
2555 | type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.\r | |
2556 | @retval ECX Returns Intel processor trace information described by the\r | |
2557 | type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.\r | |
2558 | @retval EDX Reserved.\r | |
2559 | \r | |
2560 | <b>Example usage</b>\r | |
2561 | @code\r | |
2562 | UINT32 Eax;\r | |
2563 | CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;\r | |
2564 | CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;\r | |
2565 | \r | |
2566 | AsmCpuidEx (\r | |
2567 | CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r | |
2568 | &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL\r | |
2569 | );\r | |
2570 | @endcode\r | |
2571 | **/\r | |
2572 | #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00\r | |
2573 | \r | |
2574 | /**\r | |
2575 | CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r | |
2576 | sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.\r | |
2577 | **/\r | |
2578 | typedef union {\r | |
2579 | ///\r | |
2580 | /// Individual bit fields\r | |
2581 | ///\r | |
2582 | struct {\r | |
2583 | ///\r | |
2584 | /// [Bit 0] If 1, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r | |
2585 | /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.\r | |
2586 | ///\r | |
2587 | UINT32 Cr3Filter:1;\r | |
2588 | ///\r | |
2589 | /// [Bit 1] If 1, Indicates support of Configurable PSB and Cycle-Accurate\r | |
2590 | /// Mode.\r | |
2591 | ///\r | |
2592 | UINT32 ConfigurablePsb:1;\r | |
2593 | ///\r | |
2594 | /// [Bit 2] If 1, Indicates support of IP Filtering, TraceStop filtering,\r | |
2595 | /// and preservation of Intel PT MSRs across warm reset.\r | |
2596 | ///\r | |
2597 | UINT32 IpTraceStopFiltering:1;\r | |
2598 | ///\r | |
2599 | /// [Bit 3] If 1, Indicates support of MTC timing packet and suppression of\r | |
2600 | /// COFI-based packets.\r | |
2601 | ///\r | |
2602 | UINT32 Mtc:1;\r | |
2603 | UINT32 Reserved:28;\r | |
2604 | } Bits;\r | |
2605 | ///\r | |
2606 | /// All bit fields as a 32-bit value\r | |
2607 | ///\r | |
2608 | UINT32 Uint32;\r | |
2609 | } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;\r | |
2610 | \r | |
2611 | /**\r | |
2612 | CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r | |
2613 | sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.\r | |
2614 | **/\r | |
2615 | typedef union {\r | |
2616 | ///\r | |
2617 | /// Individual bit fields\r | |
2618 | ///\r | |
2619 | struct {\r | |
2620 | ///\r | |
2621 | /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence\r | |
2622 | /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and\r | |
2623 | /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.\r | |
2624 | ///\r | |
2625 | UINT32 RTIT:1;\r | |
2626 | ///\r | |
2627 | /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to\r | |
2628 | /// the maximum allowed by the MaskOrTableOffset field of\r | |
2629 | /// IA32_RTIT_OUTPUT_MASK_PTRS.\r | |
2630 | ///\r | |
2631 | UINT32 ToPA:1;\r | |
2632 | ///\r | |
2633 | /// [Bit 2] If 1, Indicates support of Single-Range Output scheme.\r | |
2634 | ///\r | |
2635 | UINT32 SingleRangeOutput:1;\r | |
2636 | ///\r | |
2637 | /// [Bit 3] If 1, Indicates support of output to Trace Transport subsystem.\r | |
2638 | ///\r | |
2639 | UINT32 TraceTransportSubsystem:1;\r | |
2640 | UINT32 Reserved:27;\r | |
2641 | ///\r | |
2642 | /// [Bit 31] If 1, Generated packets which contain IP payloads have LIP\r | |
2643 | /// values, which include the CS base component.\r | |
2644 | ///\r | |
2645 | UINT32 LIP:1;\r | |
2646 | } Bits;\r | |
2647 | ///\r | |
2648 | /// All bit fields as a 32-bit value\r | |
2649 | ///\r | |
2650 | UINT32 Uint32;\r | |
2651 | } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;\r | |
2652 | \r | |
2653 | \r | |
2654 | /**\r | |
2655 | CPUID Intel Processor Trace Information Sub-leaf\r | |
2656 | \r | |
2657 | @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)\r | |
2658 | @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)\r | |
2659 | \r | |
2660 | @retval EAX Returns Intel processor trace information described by the\r | |
2661 | type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.\r | |
2662 | @retval EBX Returns Intel processor trace information described by the\r | |
2663 | type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.\r | |
2664 | @retval ECX Reserved.\r | |
2665 | @retval EDX Reserved.\r | |
2666 | \r | |
2667 | <b>Example usage</b>\r | |
2668 | @code\r | |
2669 | UINT32 MaximumSubLeaf;\r | |
2670 | UINT32 SubLeaf;\r | |
2671 | CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;\r | |
2672 | CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;\r | |
2673 | \r | |
2674 | AsmCpuidEx (\r | |
2675 | CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r | |
2676 | &MaximumSubLeaf, NULL, NULL, NULL\r | |
2677 | );\r | |
2678 | \r | |
2679 | for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {\r | |
2680 | AsmCpuidEx (\r | |
2681 | CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,\r | |
2682 | &Eax.Uint32, &Ebx.Uint32, NULL, NULL\r | |
2683 | );\r | |
2684 | }\r | |
2685 | @endcode\r | |
2686 | **/\r | |
2687 | #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01\r | |
2688 | \r | |
2689 | /**\r | |
2690 | CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r | |
2691 | sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.\r | |
2692 | **/\r | |
2693 | typedef union {\r | |
2694 | ///\r | |
2695 | /// Individual bit fields\r | |
2696 | ///\r | |
2697 | struct {\r | |
2698 | ///\r | |
2699 | /// [Bits 2:0] Number of configurable Address Ranges for filtering.\r | |
2700 | ///\r | |
2701 | UINT32 ConfigurableAddressRanges:3;\r | |
2702 | UINT32 Reserved:13;\r | |
2703 | ///\r | |
2704 | /// [Bits 31:16] Bitmap of supported MTC period encodings\r | |
2705 | ///\r | |
2706 | UINT32 MtcPeriodEncodings:16;\r | |
2707 | \r | |
2708 | } Bits;\r | |
2709 | ///\r | |
2710 | /// All bit fields as a 32-bit value\r | |
2711 | ///\r | |
2712 | UINT32 Uint32;\r | |
2713 | } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;\r | |
2714 | \r | |
2715 | /**\r | |
2716 | CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r | |
2717 | sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.\r | |
2718 | **/\r | |
2719 | typedef union {\r | |
2720 | ///\r | |
2721 | /// Individual bit fields\r | |
2722 | ///\r | |
2723 | struct {\r | |
2724 | ///\r | |
2725 | /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.\r | |
2726 | ///\r | |
2727 | UINT32 CycleThresholdEncodings:16;\r | |
2728 | ///\r | |
2729 | /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.\r | |
2730 | ///\r | |
2731 | UINT32 PsbFrequencyEncodings:16;\r | |
2732 | \r | |
2733 | } Bits;\r | |
2734 | ///\r | |
2735 | /// All bit fields as a 32-bit value\r | |
2736 | ///\r | |
2737 | UINT32 Uint32;\r | |
2738 | } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;\r | |
2739 | \r | |
2740 | \r | |
2741 | /**\r | |
2742 | CPUID Time Stamp Counter Information\r | |
2743 | \r | |
2744 | @note\r | |
2745 | If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.\r | |
2746 | EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core\r | |
2747 | crystal clock frequency.\r | |
2748 | "TSC frequency" = "core crystal clock frequency" * EBX/EAX.\r | |
2749 | The core crystal clock may differ from the reference clock, bus clock, or core\r | |
2750 | clock frequencies.\r | |
2751 | \r | |
2752 | @param EAX CPUID_TIME_STAMP_COUNTER (0x15)\r | |
2753 | \r | |
2754 | @retval EAX An unsigned integer which is the denominator of the\r | |
2755 | TSC/"core crystal clock" ratio\r | |
2756 | @retval EBX An unsigned integer which is the numerator of the\r | |
2757 | TSC/"core crystal clock" ratio.\r | |
2758 | @retval ECX Reserved.\r | |
2759 | @retval EDX Reserved.\r | |
2760 | \r | |
2761 | <b>Example usage</b>\r | |
2762 | @code\r | |
2763 | UINT32 Eax;\r | |
2764 | UINT32 Ebx;\r | |
2765 | \r | |
2766 | AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);\r | |
2767 | @endcode\r | |
2768 | **/\r | |
2769 | #define CPUID_TIME_STAMP_COUNTER 0x15\r | |
2770 | \r | |
2771 | \r | |
2772 | /**\r | |
2773 | CPUID Processor Frequency Information\r | |
2774 | \r | |
2775 | @note\r | |
2776 | Data is returned from this interface in accordance with the processor's\r | |
2777 | specification and does not reflect actual values. Suitable use of this data\r | |
2778 | includes the display of processor information in like manner to the processor\r | |
2779 | brand string and for determining the appropriate range to use when displaying\r | |
2780 | processor information e.g. frequency history graphs. The returned information\r | |
2781 | should not be used for any other purpose as the returned information does not\r | |
2782 | accurately correlate to information / counters returned by other processor\r | |
2783 | interfaces. While a processor may support the Processor Frequency Information\r | |
2784 | leaf, fields that return a value of zero are not supported.\r | |
2785 | \r | |
2786 | @param EAX CPUID_TIME_STAMP_COUNTER (0x16)\r | |
2787 | \r | |
2788 | @retval EAX Returns processor base frequency information described by the\r | |
2789 | type CPUID_PROCESSOR_FREQUENCY_EAX.\r | |
2790 | @retval EBX Returns maximum frequency information described by the type\r | |
2791 | CPUID_PROCESSOR_FREQUENCY_EBX.\r | |
2792 | @retval ECX Returns bus frequency information described by the type\r | |
2793 | CPUID_PROCESSOR_FREQUENCY_ECX.\r | |
2794 | @retval EDX Reserved.\r | |
2795 | \r | |
2796 | <b>Example usage</b>\r | |
2797 | @code\r | |
2798 | CPUID_PROCESSOR_FREQUENCY_EAX Eax;\r | |
2799 | CPUID_PROCESSOR_FREQUENCY_EBX Ebx;\r | |
2800 | CPUID_PROCESSOR_FREQUENCY_ECX Ecx;\r | |
2801 | \r | |
2802 | AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r | |
2803 | @endcode\r | |
2804 | **/\r | |
2805 | #define CPUID_PROCESSOR_FREQUENCY 0x16\r | |
2806 | \r | |
2807 | /**\r | |
2808 | CPUID Processor Frequency Information EAX for CPUID leaf\r | |
2809 | #CPUID_PROCESSOR_FREQUENCY.\r | |
2810 | **/\r | |
2811 | typedef union {\r | |
2812 | ///\r | |
2813 | /// Individual bit fields\r | |
2814 | ///\r | |
2815 | struct {\r | |
2816 | ///\r | |
2817 | /// [Bits 15:0] Processor Base Frequency (in MHz).\r | |
2818 | ///\r | |
2819 | UINT32 ProcessorBaseFrequency:16;\r | |
2820 | UINT32 Reserved:16;\r | |
2821 | } Bits;\r | |
2822 | ///\r | |
2823 | /// All bit fields as a 32-bit value\r | |
2824 | ///\r | |
2825 | UINT32 Uint32;\r | |
2826 | } CPUID_PROCESSOR_FREQUENCY_EAX;\r | |
2827 | \r | |
2828 | /**\r | |
2829 | CPUID Processor Frequency Information EBX for CPUID leaf\r | |
2830 | #CPUID_PROCESSOR_FREQUENCY.\r | |
2831 | **/\r | |
2832 | typedef union {\r | |
2833 | ///\r | |
2834 | /// Individual bit fields\r | |
2835 | ///\r | |
2836 | struct {\r | |
2837 | ///\r | |
2838 | /// [Bits 15:0] Maximum Frequency (in MHz).\r | |
2839 | ///\r | |
2840 | UINT32 MaximumFrequency:16;\r | |
2841 | UINT32 Reserved:16;\r | |
2842 | } Bits;\r | |
2843 | ///\r | |
2844 | /// All bit fields as a 32-bit value\r | |
2845 | ///\r | |
2846 | UINT32 Uint32;\r | |
2847 | } CPUID_PROCESSOR_FREQUENCY_EBX;\r | |
2848 | \r | |
2849 | /**\r | |
2850 | CPUID Processor Frequency Information ECX for CPUID leaf\r | |
2851 | #CPUID_PROCESSOR_FREQUENCY.\r | |
2852 | **/\r | |
2853 | typedef union {\r | |
2854 | ///\r | |
2855 | /// Individual bit fields\r | |
2856 | ///\r | |
2857 | struct {\r | |
2858 | ///\r | |
2859 | /// [Bits 15:0] Bus (Reference) Frequency (in MHz).\r | |
2860 | ///\r | |
2861 | UINT32 BusFrequency:16;\r | |
2862 | UINT32 Reserved:16;\r | |
2863 | } Bits;\r | |
2864 | ///\r | |
2865 | /// All bit fields as a 32-bit value\r | |
2866 | ///\r | |
2867 | UINT32 Uint32;\r | |
2868 | } CPUID_PROCESSOR_FREQUENCY_ECX;\r | |
2869 | \r | |
28a7ddf0 | 2870 | \r |
57d16ba1 MK |
2871 | /**\r |
2872 | CPUID SoC Vendor Information\r | |
28a7ddf0 | 2873 | \r |
57d16ba1 MK |
2874 | @param EAX CPUID_SOC_VENDOR (0x17)\r |
2875 | @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)\r | |
2876 | CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)\r | |
2877 | CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)\r | |
2878 | CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)\r | |
28a7ddf0 | 2879 | \r |
57d16ba1 MK |
2880 | @note\r |
2881 | Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String\r | |
2882 | is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC\r | |
2883 | Vendor Brand String is constructed by concatenating in ascending order of\r | |
2884 | EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.\r | |
28a7ddf0 | 2885 | \r |
57d16ba1 MK |
2886 | **/\r |
2887 | #define CPUID_SOC_VENDOR 0x17\r | |
2888 | \r | |
2889 | /**\r | |
2890 | CPUID SoC Vendor Information\r | |
2891 | \r | |
2892 | @param EAX CPUID_SOC_VENDOR (0x17)\r | |
2893 | @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)\r | |
2894 | \r | |
2895 | @retval EAX MaxSOCID_Index. Reports the maximum input value of supported\r | |
2896 | sub-leaf in leaf 17H.\r | |
2897 | @retval EBX Returns SoC Vendor information described by the type\r | |
2898 | CPUID_SOC_VENDOR_MAIN_LEAF_EBX.\r | |
2899 | @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC\r | |
2900 | projects.\r | |
2901 | @retval EDX Stepping ID. A unique number within an SOC project that an SOC\r | |
2902 | vendor assigns.\r | |
2903 | \r | |
2904 | <b>Example usage</b>\r | |
2905 | @code\r | |
2906 | UINT32 Eax;\r | |
2907 | CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;\r | |
2908 | UINT32 Ecx;\r | |
2909 | UINT32 Edx;\r | |
2910 | \r | |
2911 | AsmCpuidEx (\r | |
2912 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,\r | |
2913 | &Eax, &Ebx.Uint32, &Ecx, &Edx\r | |
2914 | );\r | |
2915 | @endcode\r | |
2916 | **/\r | |
2917 | #define CPUID_SOC_VENDOR_MAIN_LEAF 0x00\r | |
2918 | \r | |
2919 | /**\r | |
2920 | CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf\r | |
2921 | #CPUID_SOC_VENDOR_MAIN_LEAF.\r | |
2922 | **/\r | |
2923 | typedef union {\r | |
2924 | ///\r | |
2925 | /// Individual bit fields\r | |
2926 | ///\r | |
2927 | struct {\r | |
2928 | ///\r | |
2929 | /// [Bits 15:0] SOC Vendor ID.\r | |
2930 | ///\r | |
2931 | UINT32 SocVendorId:16;\r | |
2932 | ///\r | |
2933 | /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry\r | |
2934 | /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is\r | |
2935 | /// assigned by Intel.\r | |
2936 | ///\r | |
2937 | UINT32 IsVendorScheme:1;\r | |
2938 | UINT32 Reserved:15;\r | |
2939 | } Bits;\r | |
2940 | ///\r | |
2941 | /// All bit fields as a 32-bit value\r | |
2942 | ///\r | |
2943 | UINT32 Uint32;\r | |
2944 | } CPUID_SOC_VENDOR_MAIN_LEAF_EBX;\r | |
2945 | \r | |
2946 | /**\r | |
2947 | CPUID SoC Vendor Information\r | |
2948 | \r | |
2949 | @param EAX CPUID_SOC_VENDOR (0x17)\r | |
2950 | @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)\r | |
2951 | \r | |
2952 | @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
2953 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
2954 | @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
2955 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
2956 | @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
2957 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
2958 | @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
2959 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
2960 | \r | |
2961 | <b>Example usage</b>\r | |
2962 | @code\r | |
2963 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r | |
2964 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r | |
2965 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r | |
2966 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r | |
2967 | \r | |
2968 | AsmCpuidEx (\r | |
2969 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,\r | |
2970 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r | |
2971 | );\r | |
2972 | @endcode\r | |
2973 | **/\r | |
2974 | #define CPUID_SOC_VENDOR_BRAND_STRING1 0x01\r | |
2975 | \r | |
2976 | /**\r | |
2977 | CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,\r | |
2978 | #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.\r | |
2979 | **/\r | |
2980 | typedef union {\r | |
2981 | ///\r | |
2982 | /// 4 UTF-8 characters of Soc Vendor Brand String\r | |
2983 | ///\r | |
2984 | CHAR8 BrandString[4];\r | |
2985 | ///\r | |
2986 | /// All fields as a 32-bit value\r | |
2987 | ///\r | |
2988 | UINT32 Uint32;\r | |
2989 | } CPUID_SOC_VENDOR_BRAND_STRING_DATA;\r | |
2990 | \r | |
2991 | /**\r | |
2992 | CPUID SoC Vendor Information\r | |
2993 | \r | |
2994 | @param EAX CPUID_SOC_VENDOR (0x17)\r | |
2995 | @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)\r | |
2996 | \r | |
2997 | @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
2998 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
2999 | @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3000 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3001 | @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3002 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3003 | @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3004 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3005 | \r | |
3006 | <b>Example usage</b>\r | |
3007 | @code\r | |
3008 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r | |
3009 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r | |
3010 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r | |
3011 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r | |
3012 | \r | |
3013 | AsmCpuidEx (\r | |
3014 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,\r | |
3015 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r | |
3016 | );\r | |
3017 | @endcode\r | |
3018 | **/\r | |
3019 | #define CPUID_SOC_VENDOR_BRAND_STRING2 0x02\r | |
3020 | \r | |
3021 | /**\r | |
3022 | CPUID SoC Vendor Information\r | |
3023 | \r | |
3024 | @param EAX CPUID_SOC_VENDOR (0x17)\r | |
3025 | @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)\r | |
28a7ddf0 | 3026 | \r |
57d16ba1 MK |
3027 | @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r |
3028 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3029 | @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3030 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3031 | @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3032 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3033 | @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3034 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3035 | \r | |
3036 | <b>Example usage</b>\r | |
3037 | @code\r | |
3038 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r | |
3039 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r | |
3040 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r | |
3041 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r | |
3042 | \r | |
3043 | AsmCpuidEx (\r | |
3044 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,\r | |
3045 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r | |
3046 | );\r | |
3047 | @endcode\r | |
3048 | **/\r | |
3049 | #define CPUID_SOC_VENDOR_BRAND_STRING3 0x03\r | |
4de216c0 | 3050 | \r |
28a7ddf0 | 3051 | \r |
57d16ba1 MK |
3052 | /**\r |
3053 | CPUID Extended Function\r | |
3054 | \r | |
3055 | @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)\r | |
3056 | \r | |
3057 | @retval EAX Maximum Input Value for Extended Function CPUID Information.\r | |
3058 | @retval EBX Reserved.\r | |
3059 | @retval ECX Reserved.\r | |
3060 | @retval EDX Reserved.\r | |
3061 | \r | |
3062 | <b>Example usage</b>\r | |
3063 | @code\r | |
3064 | UINT32 Eax;\r | |
3065 | \r | |
3066 | AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r | |
3067 | @endcode\r | |
3068 | **/\r | |
28a7ddf0 MK |
3069 | #define CPUID_EXTENDED_FUNCTION 0x80000000\r |
3070 | \r | |
57d16ba1 MK |
3071 | \r |
3072 | /**\r | |
3073 | CPUID Extended Processor Signature and Feature Bits\r | |
3074 | \r | |
3075 | @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)\r | |
3076 | \r | |
3077 | @retval EAX CPUID_EXTENDED_CPU_SIG.\r | |
3078 | @retval EBX Reserved.\r | |
3079 | @retval ECX Extended Processor Signature and Feature Bits information\r | |
3080 | described by the type CPUID_EXTENDED_CPU_SIG_ECX.\r | |
3081 | @retval EDX Extended Processor Signature and Feature Bits information\r | |
3082 | described by the type CPUID_EXTENDED_CPU_SIG_EDX.\r | |
3083 | \r | |
3084 | <b>Example usage</b>\r | |
3085 | @code\r | |
3086 | UINT32 Eax;\r | |
3087 | CPUID_EXTENDED_CPU_SIG_ECX Ecx;\r | |
3088 | CPUID_EXTENDED_CPU_SIG_EDX Edx;\r | |
3089 | \r | |
3090 | AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);\r | |
3091 | @endcode\r | |
3092 | **/\r | |
28a7ddf0 MK |
3093 | #define CPUID_EXTENDED_CPU_SIG 0x80000001\r |
3094 | \r | |
57d16ba1 MK |
3095 | /**\r |
3096 | CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf\r | |
3097 | #CPUID_EXTENDED_CPU_SIG.\r | |
3098 | **/\r | |
3099 | typedef union {\r | |
3100 | ///\r | |
3101 | /// Individual bit fields\r | |
3102 | ///\r | |
3103 | struct {\r | |
3104 | ///\r | |
3105 | /// [Bit 0] LAHF/SAHF available in 64-bit mode.\r | |
3106 | ///\r | |
3107 | UINT32 LAHF_SAHF:1;\r | |
3108 | UINT32 Reserved1:4;\r | |
3109 | ///\r | |
3110 | /// [Bit 5] LZCNT.\r | |
3111 | ///\r | |
3112 | UINT32 LZCNT:1;\r | |
3113 | UINT32 Reserved2:2;\r | |
3114 | ///\r | |
3115 | /// [Bit 8] PREFETCHW.\r | |
3116 | ///\r | |
3117 | UINT32 PREFETCHW:1;\r | |
3118 | UINT32 Reserved3:23;\r | |
3119 | } Bits;\r | |
3120 | ///\r | |
3121 | /// All bit fields as a 32-bit value\r | |
3122 | ///\r | |
3123 | UINT32 Uint32;\r | |
3124 | } CPUID_EXTENDED_CPU_SIG_ECX;\r | |
3125 | \r | |
3126 | /**\r | |
3127 | CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf\r | |
3128 | #CPUID_EXTENDED_CPU_SIG.\r | |
3129 | **/\r | |
3130 | typedef union {\r | |
3131 | ///\r | |
3132 | /// Individual bit fields\r | |
3133 | ///\r | |
3134 | struct {\r | |
3135 | UINT32 Reserved1:11;\r | |
3136 | ///\r | |
3137 | /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.\r | |
3138 | ///\r | |
3139 | UINT32 SYSCALL_SYSRET:1;\r | |
3140 | UINT32 Reserved2:8;\r | |
3141 | ///\r | |
3142 | /// [Bit 20] Execute Disable Bit available.\r | |
3143 | ///\r | |
3144 | UINT32 NX:1;\r | |
3145 | UINT32 Reserved3:5;\r | |
3146 | ///\r | |
3147 | /// [Bit 26] 1-GByte pages are available if 1.\r | |
3148 | ///\r | |
3149 | UINT32 Page1GB:1;\r | |
3150 | ///\r | |
3151 | /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.\r | |
3152 | ///\r | |
3153 | UINT32 RDTSCP:1;\r | |
3154 | UINT32 Reserved4:1;\r | |
3155 | ///\r | |
3156 | /// [Bit 29] Intel(R) 64 Architecture available if 1.\r | |
3157 | ///\r | |
3158 | UINT32 LM:1;\r | |
3159 | UINT32 Reserved5:2;\r | |
3160 | } Bits;\r | |
3161 | ///\r | |
3162 | /// All bit fields as a 32-bit value\r | |
3163 | ///\r | |
3164 | UINT32 Uint32;\r | |
3165 | } CPUID_EXTENDED_CPU_SIG_EDX;\r | |
3166 | \r | |
3167 | \r | |
3168 | /**\r | |
3169 | CPUID Processor Brand String\r | |
3170 | \r | |
3171 | @param EAX CPUID_BRAND_STRING1 (0x80000002)\r | |
3172 | \r | |
3173 | @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.\r | |
3174 | @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3175 | @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3176 | @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3177 | \r | |
3178 | <b>Example usage</b>\r | |
3179 | @code\r | |
3180 | CPUID_BRAND_STRING_DATA Eax;\r | |
3181 | CPUID_BRAND_STRING_DATA Ebx;\r | |
3182 | CPUID_BRAND_STRING_DATA Ecx;\r | |
3183 | CPUID_BRAND_STRING_DATA Edx;\r | |
3184 | \r | |
3185 | AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
3186 | @endcode\r | |
3187 | **/\r | |
28a7ddf0 MK |
3188 | #define CPUID_BRAND_STRING1 0x80000002\r |
3189 | \r | |
57d16ba1 MK |
3190 | /**\r |
3191 | CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,\r | |
3192 | #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.\r | |
3193 | **/\r | |
3194 | typedef union {\r | |
3195 | ///\r | |
3196 | /// 4 ASCII characters of Processor Brand String\r | |
3197 | ///\r | |
3198 | CHAR8 BrandString[4];\r | |
3199 | ///\r | |
3200 | /// All fields as a 32-bit value\r | |
3201 | ///\r | |
3202 | UINT32 Uint32;\r | |
3203 | } CPUID_BRAND_STRING_DATA;\r | |
3204 | \r | |
3205 | /**\r | |
3206 | CPUID Processor Brand String\r | |
3207 | \r | |
3208 | @param EAX CPUID_BRAND_STRING2 (0x80000003)\r | |
3209 | \r | |
3210 | @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3211 | @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3212 | @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3213 | @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3214 | \r | |
3215 | <b>Example usage</b>\r | |
3216 | @code\r | |
3217 | CPUID_BRAND_STRING_DATA Eax;\r | |
3218 | CPUID_BRAND_STRING_DATA Ebx;\r | |
3219 | CPUID_BRAND_STRING_DATA Ecx;\r | |
3220 | CPUID_BRAND_STRING_DATA Edx;\r | |
3221 | \r | |
3222 | AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
3223 | @endcode\r | |
3224 | **/\r | |
28a7ddf0 MK |
3225 | #define CPUID_BRAND_STRING2 0x80000003\r |
3226 | \r | |
57d16ba1 MK |
3227 | /**\r |
3228 | CPUID Processor Brand String\r | |
3229 | \r | |
3230 | @param EAX CPUID_BRAND_STRING3 (0x80000004)\r | |
3231 | \r | |
3232 | @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3233 | @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3234 | @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3235 | @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3236 | \r | |
3237 | <b>Example usage</b>\r | |
3238 | @code\r | |
3239 | CPUID_BRAND_STRING_DATA Eax;\r | |
3240 | CPUID_BRAND_STRING_DATA Ebx;\r | |
3241 | CPUID_BRAND_STRING_DATA Ecx;\r | |
3242 | CPUID_BRAND_STRING_DATA Edx;\r | |
3243 | \r | |
3244 | AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
3245 | @endcode\r | |
3246 | **/\r | |
28a7ddf0 MK |
3247 | #define CPUID_BRAND_STRING3 0x80000004\r |
3248 | \r | |
57d16ba1 MK |
3249 | \r |
3250 | /**\r | |
3251 | CPUID Extended Cache information\r | |
3252 | \r | |
3253 | @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)\r | |
3254 | \r | |
3255 | @retval EAX Reserved.\r | |
3256 | @retval EBX Reserved.\r | |
3257 | @retval ECX Extended cache information described by the type\r | |
3258 | CPUID_EXTENDED_CACHE_INFO_ECX.\r | |
3259 | @retval EDX Reserved.\r | |
3260 | \r | |
3261 | <b>Example usage</b>\r | |
3262 | @code\r | |
3263 | CPUID_EXTENDED_CACHE_INFO_ECX Ecx;\r | |
3264 | \r | |
3265 | AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);\r | |
3266 | @endcode\r | |
3267 | **/\r | |
3268 | #define CPUID_EXTENDED_CACHE_INFO 0x80000006\r | |
3269 | \r | |
3270 | /**\r | |
3271 | CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.\r | |
3272 | **/\r | |
3273 | typedef union {\r | |
3274 | ///\r | |
3275 | /// Individual bit fields\r | |
3276 | ///\r | |
3277 | struct {\r | |
3278 | ///\r | |
3279 | /// [Bits 7:0] Cache line size in bytes.\r | |
3280 | ///\r | |
3281 | UINT32 CacheLineSize:8;\r | |
3282 | UINT32 Reserved:4;\r | |
3283 | ///\r | |
3284 | /// [Bits 15:12] L2 Associativity field. Supported values are in the range\r | |
3285 | /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to\r | |
3286 | /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL\r | |
3287 | ///\r | |
3288 | UINT32 L2Associativity:4;\r | |
3289 | ///\r | |
3290 | /// [Bits 31:16] Cache size in 1K units.\r | |
3291 | ///\r | |
3292 | UINT32 CacheSize:16;\r | |
3293 | } Bits;\r | |
3294 | ///\r | |
3295 | /// All bit fields as a 32-bit value\r | |
3296 | ///\r | |
3297 | UINT32 Uint32;\r | |
3298 | } CPUID_EXTENDED_CACHE_INFO_ECX;\r | |
3299 | \r | |
3300 | ///\r | |
3301 | /// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity\r | |
3302 | ///\r | |
3303 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00\r | |
3304 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01\r | |
3305 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02\r | |
3306 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04\r | |
3307 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06\r | |
3308 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08\r | |
3309 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F\r | |
3310 | ///\r | |
3311 | /// @}\r | |
3312 | ///\r | |
3313 | \r | |
3314 | /**\r | |
3315 | CPUID Extended Time Stamp Counter information\r | |
3316 | \r | |
3317 | @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)\r | |
3318 | \r | |
3319 | @retval EAX Reserved.\r | |
3320 | @retval EBX Reserved.\r | |
3321 | @retval ECX Reserved.\r | |
3322 | @retval EDX Extended time stamp counter (TSC) information described by the\r | |
3323 | type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.\r | |
3324 | \r | |
3325 | <b>Example usage</b>\r | |
3326 | @code\r | |
3327 | CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;\r | |
3328 | \r | |
3329 | AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);\r | |
3330 | @endcode\r | |
3331 | **/\r | |
3332 | #define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007\r | |
3333 | \r | |
3334 | /**\r | |
3335 | CPUID Extended Time Stamp Counter information EDX for CPUID leaf\r | |
3336 | #CPUID_EXTENDED_TIME_STAMP_COUNTER.\r | |
3337 | **/\r | |
3338 | typedef union {\r | |
3339 | ///\r | |
3340 | /// Individual bit fields\r | |
3341 | ///\r | |
3342 | struct {\r | |
3343 | UINT32 Reserved1:8;\r | |
3344 | ///\r | |
3345 | /// [Bit 8] Invariant TSC available if 1.\r | |
3346 | ///\r | |
3347 | UINT32 InvariantTsc:1;\r | |
3348 | UINT32 Reserved2:23;\r | |
3349 | } Bits;\r | |
3350 | ///\r | |
3351 | /// All bit fields as a 32-bit value\r | |
3352 | ///\r | |
3353 | UINT32 Uint32;\r | |
3354 | } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX;\r | |
3355 | \r | |
3356 | \r | |
3357 | /**\r | |
3358 | CPUID Linear Physical Address Size\r | |
3359 | \r | |
3360 | @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)\r | |
3361 | \r | |
3362 | @retval EAX Linear/Physical Address Size described by the type\r | |
3363 | CPUID_VIR_PHY_ADDRESS_SIZE_EAX.\r | |
3364 | @retval EBX Reserved.\r | |
3365 | @retval ECX Reserved.\r | |
3366 | @retval EDX Reserved.\r | |
3367 | \r | |
3368 | <b>Example usage</b>\r | |
3369 | @code\r | |
3370 | CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;\r | |
3371 | \r | |
3372 | AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);\r | |
3373 | @endcode\r | |
3374 | **/\r | |
28a7ddf0 MK |
3375 | #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r |
3376 | \r | |
57d16ba1 MK |
3377 | /**\r |
3378 | CPUID Linear Physical Address Size EAX for CPUID leaf\r | |
3379 | #CPUID_VIR_PHY_ADDRESS_SIZE.\r | |
3380 | **/\r | |
3381 | typedef union {\r | |
3382 | ///\r | |
3383 | /// Individual bit fields\r | |
3384 | ///\r | |
3385 | struct {\r | |
3386 | ///\r | |
3387 | /// [Bits 7:0] Number of physical address bits.\r | |
3388 | ///\r | |
3389 | /// @note\r | |
3390 | /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address\r | |
3391 | /// number supported should come from this field.\r | |
3392 | ///\r | |
3393 | UINT32 PhysicalAddressBits:8;\r | |
3394 | ///\r | |
3395 | /// [Bits 15:8] Number of linear address bits.\r | |
3396 | ///\r | |
3397 | UINT32 LinearAddressBits:8;\r | |
3398 | UINT32 Reserved:16;\r | |
3399 | } Bits;\r | |
3400 | ///\r | |
3401 | /// All bit fields as a 32-bit value\r | |
3402 | ///\r | |
3403 | UINT32 Uint32;\r | |
3404 | } CPUID_VIR_PHY_ADDRESS_SIZE_EAX;\r | |
3405 | \r | |
28a7ddf0 | 3406 | #endif\r |