]>
Commit | Line | Data |
---|---|---|
35fd9411 HW |
1 | /** @file\r |
2 | MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
ba1a2d11 | 9 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
35fd9411 HW |
11 | \r |
12 | @par Specification Reference:\r | |
ba1a2d11 ED |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
35fd9411 HW |
15 | \r |
16 | **/\r | |
17 | \r | |
18 | #ifndef __GOLDMONT_MSR_H__\r | |
19 | #define __GOLDMONT_MSR_H__\r | |
20 | \r | |
21 | #include <Register/ArchitecturalMsr.h>\r | |
22 | \r | |
f4c982bf JF |
23 | /**\r |
24 | Is Intel Atom processors based on the Goldmont microarchitecture?\r | |
25 | \r | |
26 | @param DisplayFamily Display Family ID\r | |
27 | @param DisplayModel Display Model ID\r | |
28 | \r | |
29 | @retval TRUE Yes, it is.\r | |
30 | @retval FALSE No, it isn't.\r | |
31 | **/\r | |
32 | #define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
33 | (DisplayFamily == 0x06 && \\r | |
34 | ( \\r | |
35 | DisplayModel == 0x5C \\r | |
36 | ) \\r | |
37 | )\r | |
38 | \r | |
35fd9411 HW |
39 | /**\r |
40 | Core. Control Features in Intel 64Processor (R/W).\r | |
41 | \r | |
42 | @param ECX MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A)\r | |
43 | @param EAX Lower 32-bits of MSR value.\r | |
44 | Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.\r | |
45 | @param EDX Upper 32-bits of MSR value.\r | |
46 | Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.\r | |
47 | \r | |
48 | <b>Example usage</b>\r | |
49 | @code\r | |
50 | MSR_GOLDMONT_FEATURE_CONTROL_REGISTER Msr;\r | |
51 | \r | |
52 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_FEATURE_CONTROL);\r | |
53 | AsmWriteMsr64 (MSR_GOLDMONT_FEATURE_CONTROL, Msr.Uint64);\r | |
54 | @endcode\r | |
55 | @note MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.\r | |
56 | **/\r | |
57 | #define MSR_GOLDMONT_FEATURE_CONTROL 0x0000003A\r | |
58 | \r | |
59 | /**\r | |
60 | MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL\r | |
61 | **/\r | |
62 | typedef union {\r | |
63 | ///\r | |
64 | /// Individual bit fields\r | |
65 | ///\r | |
66 | struct {\r | |
67 | ///\r | |
68 | /// [Bit 0] Lock bit (R/WL)\r | |
69 | ///\r | |
70 | UINT32 Lock:1;\r | |
71 | ///\r | |
72 | /// [Bit 1] Enable VMX inside SMX operation (R/WL)\r | |
73 | ///\r | |
74 | UINT32 EnableVmxInsideSmx:1;\r | |
75 | ///\r | |
76 | /// [Bit 2] Enable VMX outside SMX operation (R/WL)\r | |
77 | ///\r | |
78 | UINT32 EnableVmxOutsideSmx:1;\r | |
79 | UINT32 Reserved1:5;\r | |
80 | ///\r | |
81 | /// [Bits 14:8] SENTER local function enables (R/WL)\r | |
82 | ///\r | |
83 | UINT32 SenterLocalFunctionEnables:7;\r | |
84 | ///\r | |
85 | /// [Bit 15] SENTER global functions enable (R/WL)\r | |
86 | ///\r | |
87 | UINT32 SenterGlobalEnable:1;\r | |
88 | UINT32 Reserved2:2;\r | |
89 | ///\r | |
90 | /// [Bit 18] SGX global functions enable (R/WL)\r | |
91 | ///\r | |
92 | UINT32 SgxEnable:1;\r | |
93 | UINT32 Reserved3:13;\r | |
94 | UINT32 Reserved4:32;\r | |
95 | } Bits;\r | |
96 | ///\r | |
97 | /// All bit fields as a 32-bit value\r | |
98 | ///\r | |
99 | UINT32 Uint32;\r | |
100 | ///\r | |
101 | /// All bit fields as a 64-bit value\r | |
102 | ///\r | |
103 | UINT64 Uint64;\r | |
104 | } MSR_GOLDMONT_FEATURE_CONTROL_REGISTER;\r | |
105 | \r | |
106 | \r | |
107 | /**\r | |
108 | Package. See http://biosbits.org.\r | |
109 | \r | |
110 | @param ECX MSR_GOLDMONT_PLATFORM_INFO (0x000000CE)\r | |
111 | @param EAX Lower 32-bits of MSR value.\r | |
112 | Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.\r | |
113 | @param EDX Upper 32-bits of MSR value.\r | |
114 | Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.\r | |
115 | \r | |
116 | <b>Example usage</b>\r | |
117 | @code\r | |
118 | MSR_GOLDMONT_PLATFORM_INFO_REGISTER Msr;\r | |
119 | \r | |
120 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLATFORM_INFO);\r | |
121 | AsmWriteMsr64 (MSR_GOLDMONT_PLATFORM_INFO, Msr.Uint64);\r | |
122 | @endcode\r | |
123 | @note MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r | |
124 | **/\r | |
125 | #define MSR_GOLDMONT_PLATFORM_INFO 0x000000CE\r | |
126 | \r | |
127 | /**\r | |
128 | MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO\r | |
129 | **/\r | |
130 | typedef union {\r | |
131 | ///\r | |
132 | /// Individual bit fields\r | |
133 | ///\r | |
134 | struct {\r | |
135 | UINT32 Reserved1:8;\r | |
136 | ///\r | |
137 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r | |
138 | /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r | |
139 | /// MHz.\r | |
140 | ///\r | |
141 | UINT32 MaximumNonTurboRatio:8;\r | |
142 | UINT32 Reserved2:12;\r | |
143 | ///\r | |
144 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r | |
145 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r | |
146 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r | |
147 | /// Turbo mode is disabled.\r | |
148 | ///\r | |
149 | UINT32 RatioLimit:1;\r | |
150 | ///\r | |
151 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r | |
152 | /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r | |
153 | /// and when set to 0, indicates TDP Limit for Turbo mode is not\r | |
154 | /// programmable.\r | |
155 | ///\r | |
156 | UINT32 TDPLimit:1;\r | |
157 | ///\r | |
158 | /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,\r | |
159 | /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r | |
160 | /// specify an temperature offset.\r | |
161 | ///\r | |
162 | UINT32 TJOFFSET:1;\r | |
163 | UINT32 Reserved3:1;\r | |
164 | UINT32 Reserved4:8;\r | |
165 | ///\r | |
166 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r | |
167 | /// minimum ratio (maximum efficiency) that the processor can operates, in\r | |
168 | /// units of 100MHz.\r | |
169 | ///\r | |
170 | UINT32 MaximumEfficiencyRatio:8;\r | |
171 | UINT32 Reserved5:16;\r | |
172 | } Bits;\r | |
173 | ///\r | |
174 | /// All bit fields as a 64-bit value\r | |
175 | ///\r | |
176 | UINT64 Uint64;\r | |
177 | } MSR_GOLDMONT_PLATFORM_INFO_REGISTER;\r | |
178 | \r | |
179 | \r | |
180 | /**\r | |
181 | Core. C-State Configuration Control (R/W) Note: C-state values are\r | |
182 | processor specific C-state code names, unrelated to MWAIT extension C-state\r | |
183 | parameters or ACPI CStates. See http://biosbits.org.\r | |
184 | \r | |
185 | @param ECX MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
186 | @param EAX Lower 32-bits of MSR value.\r | |
187 | Described by the type\r | |
188 | MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
189 | @param EDX Upper 32-bits of MSR value.\r | |
190 | Described by the type\r | |
191 | MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
192 | \r | |
193 | <b>Example usage</b>\r | |
194 | @code\r | |
195 | MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
196 | \r | |
197 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL);\r | |
198 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
199 | @endcode\r | |
200 | @note MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r | |
201 | **/\r | |
202 | #define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
203 | \r | |
204 | /**\r | |
205 | MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL\r | |
206 | **/\r | |
207 | typedef union {\r | |
208 | ///\r | |
209 | /// Individual bit fields\r | |
210 | ///\r | |
211 | struct {\r | |
212 | ///\r | |
213 | /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r | |
214 | /// processor-specific C-state code name (consuming the least power). for\r | |
215 | /// the package. The default is set as factory-configured package C-state\r | |
216 | /// limit. The following C-state code name encodings are supported: 0000b:\r | |
217 | /// No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8\r | |
218 | /// 0111b: C9 1000b: C10.\r | |
219 | ///\r | |
220 | UINT32 Limit:4;\r | |
221 | UINT32 Reserved1:6;\r | |
222 | ///\r | |
223 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r | |
224 | /// IO_read instructions sent to IO register specified by\r | |
225 | /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r | |
226 | ///\r | |
227 | UINT32 IO_MWAIT:1;\r | |
228 | UINT32 Reserved2:4;\r | |
229 | ///\r | |
230 | /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r | |
231 | /// until next reset.\r | |
232 | ///\r | |
233 | UINT32 CFGLock:1;\r | |
234 | UINT32 Reserved3:16;\r | |
235 | UINT32 Reserved4:32;\r | |
236 | } Bits;\r | |
237 | ///\r | |
238 | /// All bit fields as a 32-bit value\r | |
239 | ///\r | |
240 | UINT32 Uint32;\r | |
241 | ///\r | |
242 | /// All bit fields as a 64-bit value\r | |
243 | ///\r | |
244 | UINT64 Uint64;\r | |
245 | } MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
246 | \r | |
247 | \r | |
248 | /**\r | |
249 | Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement.\r | |
250 | Accessible only while in SMM.\r | |
251 | \r | |
252 | @param ECX MSR_GOLDMONT_SMM_MCA_CAP (0x0000017D)\r | |
253 | @param EAX Lower 32-bits of MSR value.\r | |
254 | Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.\r | |
255 | @param EDX Upper 32-bits of MSR value.\r | |
256 | Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.\r | |
257 | \r | |
258 | <b>Example usage</b>\r | |
259 | @code\r | |
260 | MSR_GOLDMONT_SMM_MCA_CAP_REGISTER Msr;\r | |
261 | \r | |
262 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_MCA_CAP);\r | |
263 | AsmWriteMsr64 (MSR_GOLDMONT_SMM_MCA_CAP, Msr.Uint64);\r | |
264 | @endcode\r | |
265 | @note MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r | |
266 | **/\r | |
267 | #define MSR_GOLDMONT_SMM_MCA_CAP 0x0000017D\r | |
268 | \r | |
269 | /**\r | |
270 | MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP\r | |
271 | **/\r | |
272 | typedef union {\r | |
273 | ///\r | |
274 | /// Individual bit fields\r | |
275 | ///\r | |
276 | struct {\r | |
277 | UINT32 Reserved1:32;\r | |
278 | UINT32 Reserved2:26;\r | |
279 | ///\r | |
280 | /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r | |
281 | /// SMM code access restriction is supported and the\r | |
282 | /// MSR_SMM_FEATURE_CONTROL is supported.\r | |
283 | ///\r | |
284 | UINT32 SMM_Code_Access_Chk:1;\r | |
285 | ///\r | |
286 | /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r | |
287 | /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is\r | |
288 | /// supported.\r | |
289 | ///\r | |
290 | UINT32 Long_Flow_Indication:1;\r | |
291 | UINT32 Reserved3:4;\r | |
292 | } Bits;\r | |
293 | ///\r | |
294 | /// All bit fields as a 64-bit value\r | |
295 | ///\r | |
296 | UINT64 Uint64;\r | |
297 | } MSR_GOLDMONT_SMM_MCA_CAP_REGISTER;\r | |
298 | \r | |
299 | \r | |
300 | /**\r | |
301 | Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
302 | functions to be enabled and disabled.\r | |
303 | \r | |
304 | @param ECX MSR_GOLDMONT_IA32_MISC_ENABLE (0x000001A0)\r | |
305 | @param EAX Lower 32-bits of MSR value.\r | |
306 | Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.\r | |
307 | @param EDX Upper 32-bits of MSR value.\r | |
308 | Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.\r | |
309 | \r | |
310 | <b>Example usage</b>\r | |
311 | @code\r | |
312 | MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER Msr;\r | |
313 | \r | |
314 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE);\r | |
315 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE, Msr.Uint64);\r | |
316 | @endcode\r | |
317 | @note MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r | |
318 | **/\r | |
319 | #define MSR_GOLDMONT_IA32_MISC_ENABLE 0x000001A0\r | |
320 | \r | |
321 | /**\r | |
322 | MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE\r | |
323 | **/\r | |
324 | typedef union {\r | |
325 | ///\r | |
326 | /// Individual bit fields\r | |
327 | ///\r | |
328 | struct {\r | |
329 | ///\r | |
ba1a2d11 | 330 | /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.\r |
35fd9411 HW |
331 | ///\r |
332 | UINT32 FastStrings:1;\r | |
333 | UINT32 Reserved1:2;\r | |
334 | ///\r | |
335 | /// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See\r | |
ba1a2d11 | 336 | /// Table 2-2. Default value is 1.\r |
35fd9411 HW |
337 | ///\r |
338 | UINT32 AutomaticThermalControlCircuit:1;\r | |
339 | UINT32 Reserved2:3;\r | |
340 | ///\r | |
ba1a2d11 | 341 | /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.\r |
35fd9411 HW |
342 | ///\r |
343 | UINT32 PerformanceMonitoring:1;\r | |
344 | UINT32 Reserved3:3;\r | |
345 | ///\r | |
ba1a2d11 | 346 | /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.\r |
35fd9411 HW |
347 | ///\r |
348 | UINT32 BTS:1;\r | |
349 | ///\r | |
350 | /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See\r | |
ba1a2d11 | 351 | /// Table 2-2.\r |
35fd9411 HW |
352 | ///\r |
353 | UINT32 PEBS:1;\r | |
354 | UINT32 Reserved4:3;\r | |
355 | ///\r | |
356 | /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r | |
ba1a2d11 | 357 | /// Table 2-2.\r |
35fd9411 HW |
358 | ///\r |
359 | UINT32 EIST:1;\r | |
360 | UINT32 Reserved5:1;\r | |
361 | ///\r | |
ba1a2d11 | 362 | /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.\r |
35fd9411 HW |
363 | ///\r |
364 | UINT32 MONITOR:1;\r | |
365 | UINT32 Reserved6:3;\r | |
366 | ///\r | |
ba1a2d11 | 367 | /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.\r |
35fd9411 HW |
368 | ///\r |
369 | UINT32 LimitCpuidMaxval:1;\r | |
370 | ///\r | |
ba1a2d11 | 371 | /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.\r |
35fd9411 HW |
372 | ///\r |
373 | UINT32 xTPR_Message_Disable:1;\r | |
374 | UINT32 Reserved7:8;\r | |
375 | UINT32 Reserved8:2;\r | |
376 | ///\r | |
ba1a2d11 | 377 | /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.\r |
35fd9411 HW |
378 | ///\r |
379 | UINT32 XD:1;\r | |
380 | UINT32 Reserved9:3;\r | |
381 | ///\r | |
382 | /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r | |
383 | /// that support Intel Turbo Boost Technology, the turbo mode feature is\r | |
384 | /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r | |
385 | /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r | |
386 | /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r | |
387 | /// the power-on default value is used by BIOS to detect hardware support\r | |
388 | /// of turbo mode. If power-on default value is 1, turbo mode is available\r | |
389 | /// in the processor. If power-on default value is 0, turbo mode is not\r | |
390 | /// available.\r | |
391 | ///\r | |
392 | UINT32 TurboModeDisable:1;\r | |
393 | UINT32 Reserved10:25;\r | |
394 | } Bits;\r | |
395 | ///\r | |
396 | /// All bit fields as a 64-bit value\r | |
397 | ///\r | |
398 | UINT64 Uint64;\r | |
399 | } MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER;\r | |
400 | \r | |
401 | \r | |
402 | /**\r | |
403 | Miscellaneous Feature Control (R/W).\r | |
404 | \r | |
405 | @param ECX MSR_GOLDMONT_MISC_FEATURE_CONTROL (0x000001A4)\r | |
406 | @param EAX Lower 32-bits of MSR value.\r | |
407 | Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.\r | |
408 | @param EDX Upper 32-bits of MSR value.\r | |
409 | Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.\r | |
410 | \r | |
411 | <b>Example usage</b>\r | |
412 | @code\r | |
413 | MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER Msr;\r | |
414 | \r | |
415 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL);\r | |
416 | AsmWriteMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL, Msr.Uint64);\r | |
417 | @endcode\r | |
418 | @note MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r | |
419 | **/\r | |
420 | #define MSR_GOLDMONT_MISC_FEATURE_CONTROL 0x000001A4\r | |
421 | \r | |
422 | /**\r | |
423 | MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL\r | |
424 | **/\r | |
425 | typedef union {\r | |
426 | ///\r | |
427 | /// Individual bit fields\r | |
428 | ///\r | |
429 | struct {\r | |
430 | ///\r | |
431 | /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r | |
432 | /// L2 hardware prefetcher, which fetches additional lines of code or data\r | |
433 | /// into the L2 cache.\r | |
434 | ///\r | |
435 | UINT32 L2HardwarePrefetcherDisable:1;\r | |
436 | UINT32 Reserved1:1;\r | |
437 | ///\r | |
438 | /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r | |
439 | /// the L1 data cache prefetcher, which fetches the next cache line into\r | |
440 | /// L1 data cache.\r | |
441 | ///\r | |
442 | UINT32 DCUHardwarePrefetcherDisable:1;\r | |
443 | UINT32 Reserved2:29;\r | |
444 | UINT32 Reserved3:32;\r | |
445 | } Bits;\r | |
446 | ///\r | |
447 | /// All bit fields as a 32-bit value\r | |
448 | ///\r | |
449 | UINT32 Uint32;\r | |
450 | ///\r | |
451 | /// All bit fields as a 64-bit value\r | |
452 | ///\r | |
453 | UINT64 Uint64;\r | |
454 | } MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER;\r | |
455 | \r | |
456 | \r | |
457 | /**\r | |
458 | Package. See http://biosbits.org.\r | |
459 | \r | |
460 | @param ECX MSR_GOLDMONT_MISC_PWR_MGMT (0x000001AA)\r | |
461 | @param EAX Lower 32-bits of MSR value.\r | |
462 | Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.\r | |
463 | @param EDX Upper 32-bits of MSR value.\r | |
464 | Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.\r | |
465 | \r | |
466 | <b>Example usage</b>\r | |
467 | @code\r | |
468 | MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER Msr;\r | |
469 | \r | |
470 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT);\r | |
471 | AsmWriteMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT, Msr.Uint64);\r | |
472 | @endcode\r | |
473 | @note MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r | |
474 | **/\r | |
475 | #define MSR_GOLDMONT_MISC_PWR_MGMT 0x000001AA\r | |
476 | \r | |
477 | /**\r | |
478 | MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT\r | |
479 | **/\r | |
480 | typedef union {\r | |
481 | ///\r | |
482 | /// Individual bit fields\r | |
483 | ///\r | |
484 | struct {\r | |
485 | ///\r | |
486 | /// [Bit 0] EIST Hardware Coordination Disable (R/W) When 0, enables\r | |
487 | /// hardware coordination of Enhanced Intel Speedstep Technology request\r | |
488 | /// from processor cores; When 1, disables hardware coordination of\r | |
489 | /// Enhanced Intel Speedstep Technology requests.\r | |
490 | ///\r | |
491 | UINT32 EISTHardwareCoordinationDisable:1;\r | |
492 | UINT32 Reserved1:21;\r | |
493 | ///\r | |
494 | /// [Bit 22] Thermal Interrupt Coordination Enable (R/W) If set, then\r | |
495 | /// thermal interrupt on one core is routed to all cores.\r | |
496 | ///\r | |
497 | UINT32 ThermalInterruptCoordinationEnable:1;\r | |
498 | UINT32 Reserved2:9;\r | |
499 | UINT32 Reserved3:32;\r | |
500 | } Bits;\r | |
501 | ///\r | |
502 | /// All bit fields as a 32-bit value\r | |
503 | ///\r | |
504 | UINT32 Uint32;\r | |
505 | ///\r | |
506 | /// All bit fields as a 64-bit value\r | |
507 | ///\r | |
508 | UINT64 Uint64;\r | |
509 | } MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER;\r | |
510 | \r | |
511 | \r | |
512 | /**\r | |
513 | Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies\r | |
514 | Maximum Ratio Limit for each Core Group. Max ratio for groups with more\r | |
515 | cores must decrease monotonically. For groups with less than 4 cores, the\r | |
516 | max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must\r | |
517 | be 22 or less. For groups with more than 5 cores, the max ratio must be 16\r | |
518 | or less..\r | |
519 | \r | |
520 | @param ECX MSR_GOLDMONT_TURBO_RATIO_LIMIT (0x000001AD)\r | |
521 | @param EAX Lower 32-bits of MSR value.\r | |
522 | Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.\r | |
523 | @param EDX Upper 32-bits of MSR value.\r | |
524 | Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.\r | |
525 | \r | |
526 | <b>Example usage</b>\r | |
527 | @code\r | |
528 | MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
529 | \r | |
530 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT);\r | |
531 | AsmWriteMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT, Msr.Uint64);\r | |
532 | @endcode\r | |
533 | @note MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r | |
534 | **/\r | |
535 | #define MSR_GOLDMONT_TURBO_RATIO_LIMIT 0x000001AD\r | |
536 | \r | |
537 | /**\r | |
538 | MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT\r | |
539 | **/\r | |
540 | typedef union {\r | |
541 | ///\r | |
542 | /// Individual bit fields\r | |
543 | ///\r | |
544 | struct {\r | |
545 | ///\r | |
546 | /// [Bits 7:0] Package. Maximum Ratio Limit for Active cores in Group 0\r | |
547 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
548 | /// to Group 0 threshold.\r | |
549 | ///\r | |
550 | UINT32 MaxRatioLimitGroup0:8;\r | |
551 | ///\r | |
552 | /// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1\r | |
553 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
554 | /// to Group 1 threshold and greater than Group 0 threshold.\r | |
555 | ///\r | |
556 | UINT32 MaxRatioLimitGroup1:8;\r | |
557 | ///\r | |
558 | /// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2\r | |
559 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
560 | /// to Group 2 threshold and greater than Group 1 threshold.\r | |
561 | ///\r | |
562 | UINT32 MaxRatioLimitGroup2:8;\r | |
563 | ///\r | |
564 | /// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3\r | |
565 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
566 | /// to Group 3 threshold and greater than Group 2 threshold.\r | |
567 | ///\r | |
568 | UINT32 MaxRatioLimitGroup3:8;\r | |
569 | ///\r | |
570 | /// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4\r | |
571 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
572 | /// to Group 4 threshold and greater than Group 3 threshold.\r | |
573 | ///\r | |
574 | UINT32 MaxRatioLimitGroup4:8;\r | |
575 | ///\r | |
576 | /// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5\r | |
577 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
578 | /// to Group 5 threshold and greater than Group 4 threshold.\r | |
579 | ///\r | |
580 | UINT32 MaxRatioLimitGroup5:8;\r | |
581 | ///\r | |
582 | /// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6\r | |
583 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
584 | /// to Group 6 threshold and greater than Group 5 threshold.\r | |
585 | ///\r | |
586 | UINT32 MaxRatioLimitGroup6:8;\r | |
587 | ///\r | |
588 | /// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7\r | |
589 | /// Maximum turbo ratio limit when number of active cores is less or equal\r | |
590 | /// to Group 7 threshold and greater than Group 6 threshold.\r | |
591 | ///\r | |
592 | UINT32 MaxRatioLimitGroup7:8;\r | |
593 | } Bits;\r | |
594 | ///\r | |
595 | /// All bit fields as a 64-bit value\r | |
596 | ///\r | |
597 | UINT64 Uint64;\r | |
598 | } MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER;\r | |
599 | \r | |
600 | \r | |
601 | /**\r | |
602 | Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of\r | |
603 | 0 threshold is ignored.\r | |
604 | \r | |
605 | @param ECX MSR_GOLDMONT_TURBO_GROUP_CORECNT (0x000001AE)\r | |
606 | @param EAX Lower 32-bits of MSR value.\r | |
607 | Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.\r | |
608 | @param EDX Upper 32-bits of MSR value.\r | |
609 | Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.\r | |
610 | \r | |
611 | <b>Example usage</b>\r | |
612 | @code\r | |
613 | MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER Msr;\r | |
614 | \r | |
615 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT);\r | |
616 | AsmWriteMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT, Msr.Uint64);\r | |
617 | @endcode\r | |
618 | @note MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM.\r | |
619 | **/\r | |
620 | #define MSR_GOLDMONT_TURBO_GROUP_CORECNT 0x000001AE\r | |
621 | \r | |
622 | /**\r | |
623 | MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT\r | |
624 | **/\r | |
625 | typedef union {\r | |
626 | ///\r | |
627 | /// Individual bit fields\r | |
628 | ///\r | |
629 | struct {\r | |
630 | ///\r | |
631 | /// [Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of\r | |
632 | /// active cores to operate under Group 0 Max Turbo Ratio limit.\r | |
633 | ///\r | |
634 | UINT32 CoreCountThresholdGroup0:8;\r | |
635 | ///\r | |
636 | /// [Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of\r | |
637 | /// active cores to operate under Group 1 Max Turbo Ratio limit. Must be\r | |
638 | /// greater than Group 0 Core Count.\r | |
639 | ///\r | |
640 | UINT32 CoreCountThresholdGroup1:8;\r | |
641 | ///\r | |
642 | /// [Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of\r | |
643 | /// active cores to operate under Group 2 Max Turbo Ratio limit. Must be\r | |
644 | /// greater than Group 1 Core Count.\r | |
645 | ///\r | |
646 | UINT32 CoreCountThresholdGroup2:8;\r | |
647 | ///\r | |
648 | /// [Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of\r | |
649 | /// active cores to operate under Group 3 Max Turbo Ratio limit. Must be\r | |
650 | /// greater than Group 2 Core Count.\r | |
651 | ///\r | |
652 | UINT32 CoreCountThresholdGroup3:8;\r | |
653 | ///\r | |
654 | /// [Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of\r | |
655 | /// active cores to operate under Group 4 Max Turbo Ratio limit. Must be\r | |
656 | /// greater than Group 3 Core Count.\r | |
657 | ///\r | |
658 | UINT32 CoreCountThresholdGroup4:8;\r | |
659 | ///\r | |
660 | /// [Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of\r | |
661 | /// active cores to operate under Group 5 Max Turbo Ratio limit. Must be\r | |
662 | /// greater than Group 4 Core Count.\r | |
663 | ///\r | |
664 | UINT32 CoreCountThresholdGroup5:8;\r | |
665 | ///\r | |
666 | /// [Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of\r | |
667 | /// active cores to operate under Group 6 Max Turbo Ratio limit. Must be\r | |
668 | /// greater than Group 5 Core Count.\r | |
669 | ///\r | |
670 | UINT32 CoreCountThresholdGroup6:8;\r | |
671 | ///\r | |
672 | /// [Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of\r | |
673 | /// active cores to operate under Group 7 Max Turbo Ratio limit. Must be\r | |
674 | /// greater than Group 6 Core Count and not less than the total number of\r | |
675 | /// processor cores in the package. E.g. specify 255.\r | |
676 | ///\r | |
677 | UINT32 CoreCountThresholdGroup7:8;\r | |
678 | } Bits;\r | |
679 | ///\r | |
680 | /// All bit fields as a 64-bit value\r | |
681 | ///\r | |
682 | UINT64 Uint64;\r | |
683 | } MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER;\r | |
684 | \r | |
685 | \r | |
686 | /**\r | |
ba1a2d11 ED |
687 | Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r |
688 | "Filtering of Last Branch Records.".\r | |
35fd9411 HW |
689 | \r |
690 | @param ECX MSR_GOLDMONT_LBR_SELECT (0x000001C8)\r | |
691 | @param EAX Lower 32-bits of MSR value.\r | |
692 | Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.\r | |
693 | @param EDX Upper 32-bits of MSR value.\r | |
694 | Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.\r | |
695 | \r | |
696 | <b>Example usage</b>\r | |
697 | @code\r | |
698 | MSR_GOLDMONT_LBR_SELECT_REGISTER Msr;\r | |
699 | \r | |
700 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LBR_SELECT);\r | |
701 | AsmWriteMsr64 (MSR_GOLDMONT_LBR_SELECT, Msr.Uint64);\r | |
702 | @endcode\r | |
703 | @note MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r | |
704 | **/\r | |
705 | #define MSR_GOLDMONT_LBR_SELECT 0x000001C8\r | |
706 | \r | |
707 | /**\r | |
708 | MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT\r | |
709 | **/\r | |
710 | typedef union {\r | |
711 | ///\r | |
712 | /// Individual bit fields\r | |
713 | ///\r | |
714 | struct {\r | |
715 | ///\r | |
716 | /// [Bit 0] CPL_EQ_0.\r | |
717 | ///\r | |
718 | UINT32 CPL_EQ_0:1;\r | |
719 | ///\r | |
720 | /// [Bit 1] CPL_NEQ_0.\r | |
721 | ///\r | |
722 | UINT32 CPL_NEQ_0:1;\r | |
723 | ///\r | |
724 | /// [Bit 2] JCC.\r | |
725 | ///\r | |
726 | UINT32 JCC:1;\r | |
727 | ///\r | |
728 | /// [Bit 3] NEAR_REL_CALL.\r | |
729 | ///\r | |
730 | UINT32 NEAR_REL_CALL:1;\r | |
731 | ///\r | |
732 | /// [Bit 4] NEAR_IND_CALL.\r | |
733 | ///\r | |
734 | UINT32 NEAR_IND_CALL:1;\r | |
735 | ///\r | |
736 | /// [Bit 5] NEAR_RET.\r | |
737 | ///\r | |
738 | UINT32 NEAR_RET:1;\r | |
739 | ///\r | |
740 | /// [Bit 6] NEAR_IND_JMP.\r | |
741 | ///\r | |
742 | UINT32 NEAR_IND_JMP:1;\r | |
743 | ///\r | |
744 | /// [Bit 7] NEAR_REL_JMP.\r | |
745 | ///\r | |
746 | UINT32 NEAR_REL_JMP:1;\r | |
747 | ///\r | |
748 | /// [Bit 8] FAR_BRANCH.\r | |
749 | ///\r | |
750 | UINT32 FAR_BRANCH:1;\r | |
751 | ///\r | |
752 | /// [Bit 9] EN_CALL_STACK.\r | |
753 | ///\r | |
754 | UINT32 EN_CALL_STACK:1;\r | |
755 | UINT32 Reserved1:22;\r | |
756 | UINT32 Reserved2:32;\r | |
757 | } Bits;\r | |
758 | ///\r | |
759 | /// All bit fields as a 32-bit value\r | |
760 | ///\r | |
761 | UINT32 Uint32;\r | |
762 | ///\r | |
763 | /// All bit fields as a 64-bit value\r | |
764 | ///\r | |
765 | UINT64 Uint64;\r | |
766 | } MSR_GOLDMONT_LBR_SELECT_REGISTER;\r | |
767 | \r | |
768 | \r | |
769 | /**\r | |
770 | Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) that\r | |
771 | points to the MSR containing the most recent branch record. See\r | |
772 | MSR_LASTBRANCH_0_FROM_IP.\r | |
773 | \r | |
774 | @param ECX MSR_GOLDMONT_LASTBRANCH_TOS (0x000001C9)\r | |
775 | @param EAX Lower 32-bits of MSR value.\r | |
776 | @param EDX Upper 32-bits of MSR value.\r | |
777 | \r | |
778 | <b>Example usage</b>\r | |
779 | @code\r | |
780 | UINT64 Msr;\r | |
781 | \r | |
782 | Msr = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS);\r | |
783 | AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS, Msr);\r | |
784 | @endcode\r | |
785 | @note MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r | |
786 | **/\r | |
787 | #define MSR_GOLDMONT_LASTBRANCH_TOS 0x000001C9\r | |
788 | \r | |
789 | \r | |
790 | /**\r | |
791 | Core. Power Control Register. See http://biosbits.org.\r | |
792 | \r | |
793 | @param ECX MSR_GOLDMONT_POWER_CTL (0x000001FC)\r | |
794 | @param EAX Lower 32-bits of MSR value.\r | |
795 | Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.\r | |
796 | @param EDX Upper 32-bits of MSR value.\r | |
797 | Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.\r | |
798 | \r | |
799 | <b>Example usage</b>\r | |
800 | @code\r | |
801 | MSR_GOLDMONT_POWER_CTL_REGISTER Msr;\r | |
802 | \r | |
803 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_POWER_CTL);\r | |
804 | AsmWriteMsr64 (MSR_GOLDMONT_POWER_CTL, Msr.Uint64);\r | |
805 | @endcode\r | |
806 | @note MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r | |
807 | **/\r | |
808 | #define MSR_GOLDMONT_POWER_CTL 0x000001FC\r | |
809 | \r | |
810 | /**\r | |
811 | MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL\r | |
812 | **/\r | |
813 | typedef union {\r | |
814 | ///\r | |
815 | /// Individual bit fields\r | |
816 | ///\r | |
817 | struct {\r | |
818 | UINT32 Reserved1:1;\r | |
819 | ///\r | |
820 | /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the\r | |
821 | /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology\r | |
822 | /// operating point when all execution cores enter MWAIT (C1).\r | |
823 | ///\r | |
824 | UINT32 C1EEnable:1;\r | |
825 | UINT32 Reserved2:30;\r | |
826 | UINT32 Reserved3:32;\r | |
827 | } Bits;\r | |
828 | ///\r | |
829 | /// All bit fields as a 32-bit value\r | |
830 | ///\r | |
831 | UINT32 Uint32;\r | |
832 | ///\r | |
833 | /// All bit fields as a 64-bit value\r | |
834 | ///\r | |
835 | UINT64 Uint64;\r | |
836 | } MSR_GOLDMONT_POWER_CTL_REGISTER;\r | |
837 | \r | |
838 | \r | |
839 | /**\r | |
140d7131 ED |
840 | Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r |
841 | CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r | |
842 | the package. Lower 64 bits of an 128-bit external entropy value for key\r | |
843 | derivation of an enclave.\r | |
35fd9411 | 844 | \r |
140d7131 | 845 | @param ECX MSR_GOLDMONT_SGXOWNEREPOCH0 (0x00000300)\r |
35fd9411 HW |
846 | @param EAX Lower 32-bits of MSR value.\r |
847 | @param EDX Upper 32-bits of MSR value.\r | |
848 | \r | |
849 | <b>Example usage</b>\r | |
850 | @code\r | |
851 | UINT64 Msr;\r | |
852 | \r | |
140d7131 | 853 | Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0);\r |
35fd9411 | 854 | @endcode\r |
140d7131 | 855 | @note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.\r |
35fd9411 | 856 | **/\r |
140d7131 ED |
857 | #define MSR_GOLDMONT_SGXOWNEREPOCH0 0x00000300\r |
858 | \r | |
859 | \r | |
860 | //\r | |
861 | // Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM.\r | |
862 | //\r | |
863 | #define MSR_GOLDMONT_SGXOWNER0 MSR_GOLDMONT_SGXOWNEREPOCH0\r | |
35fd9411 HW |
864 | \r |
865 | \r | |
866 | /**\r | |
867 | Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of\r | |
868 | an 128-bit external entropy value for key derivation of an enclave.\r | |
869 | \r | |
140d7131 | 870 | @param ECX MSR_GOLDMONT_SGXOWNEREPOCH1 (0x00000301)\r |
35fd9411 HW |
871 | @param EAX Lower 32-bits of MSR value.\r |
872 | @param EDX Upper 32-bits of MSR value.\r | |
873 | \r | |
874 | <b>Example usage</b>\r | |
875 | @code\r | |
876 | UINT64 Msr;\r | |
877 | \r | |
140d7131 | 878 | Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1);\r |
35fd9411 | 879 | @endcode\r |
140d7131 | 880 | @note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.\r |
35fd9411 | 881 | **/\r |
140d7131 ED |
882 | #define MSR_GOLDMONT_SGXOWNEREPOCH1 0x00000301\r |
883 | \r | |
884 | \r | |
885 | //\r | |
886 | // Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM.\r | |
887 | //\r | |
888 | #define MSR_GOLDMONT_SGXOWNER1 MSR_GOLDMONT_SGXOWNEREPOCH1\r | |
35fd9411 HW |
889 | \r |
890 | \r | |
891 | /**\r | |
ba1a2d11 | 892 | Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r |
35fd9411 HW |
893 | Monitoring Version 4.".\r |
894 | \r | |
895 | @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r | |
896 | @param EAX Lower 32-bits of MSR value.\r | |
897 | Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
898 | @param EDX Upper 32-bits of MSR value.\r | |
899 | Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r | |
900 | \r | |
901 | <b>Example usage</b>\r | |
902 | @code\r | |
903 | MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r | |
904 | \r | |
905 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET);\r | |
906 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r | |
907 | @endcode\r | |
908 | @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r | |
909 | **/\r | |
910 | #define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r | |
911 | \r | |
912 | /**\r | |
913 | MSR information returned for MSR index\r | |
914 | #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET\r | |
915 | **/\r | |
916 | typedef union {\r | |
917 | ///\r | |
918 | /// Individual bit fields\r | |
919 | ///\r | |
920 | struct {\r | |
921 | ///\r | |
922 | /// [Bit 0] Set 1 to clear Ovf_PMC0.\r | |
923 | ///\r | |
924 | UINT32 Ovf_PMC0:1;\r | |
925 | ///\r | |
926 | /// [Bit 1] Set 1 to clear Ovf_PMC1.\r | |
927 | ///\r | |
928 | UINT32 Ovf_PMC1:1;\r | |
929 | ///\r | |
930 | /// [Bit 2] Set 1 to clear Ovf_PMC2.\r | |
931 | ///\r | |
932 | UINT32 Ovf_PMC2:1;\r | |
933 | ///\r | |
934 | /// [Bit 3] Set 1 to clear Ovf_PMC3.\r | |
935 | ///\r | |
936 | UINT32 Ovf_PMC3:1;\r | |
937 | UINT32 Reserved1:28;\r | |
938 | ///\r | |
939 | /// [Bit 32] Set 1 to clear Ovf_FixedCtr0.\r | |
940 | ///\r | |
941 | UINT32 Ovf_FixedCtr0:1;\r | |
942 | ///\r | |
943 | /// [Bit 33] Set 1 to clear Ovf_FixedCtr1.\r | |
944 | ///\r | |
945 | UINT32 Ovf_FixedCtr1:1;\r | |
946 | ///\r | |
947 | /// [Bit 34] Set 1 to clear Ovf_FixedCtr2.\r | |
948 | ///\r | |
949 | UINT32 Ovf_FixedCtr2:1;\r | |
950 | UINT32 Reserved2:20;\r | |
951 | ///\r | |
952 | /// [Bit 55] Set 1 to clear Trace_ToPA_PMI.\r | |
953 | ///\r | |
954 | UINT32 Trace_ToPA_PMI:1;\r | |
955 | UINT32 Reserved3:2;\r | |
956 | ///\r | |
957 | /// [Bit 58] Set 1 to clear LBR_Frz.\r | |
958 | ///\r | |
959 | UINT32 LBR_Frz:1;\r | |
960 | ///\r | |
961 | /// [Bit 59] Set 1 to clear CTR_Frz.\r | |
962 | ///\r | |
963 | UINT32 CTR_Frz:1;\r | |
964 | ///\r | |
965 | /// [Bit 60] Set 1 to clear ASCI.\r | |
966 | ///\r | |
967 | UINT32 ASCI:1;\r | |
968 | ///\r | |
969 | /// [Bit 61] Set 1 to clear Ovf_Uncore.\r | |
970 | ///\r | |
971 | UINT32 Ovf_Uncore:1;\r | |
972 | ///\r | |
973 | /// [Bit 62] Set 1 to clear Ovf_BufDSSAVE.\r | |
974 | ///\r | |
975 | UINT32 Ovf_BufDSSAVE:1;\r | |
976 | ///\r | |
977 | /// [Bit 63] Set 1 to clear CondChgd.\r | |
978 | ///\r | |
979 | UINT32 CondChgd:1;\r | |
980 | } Bits;\r | |
981 | ///\r | |
982 | /// All bit fields as a 64-bit value\r | |
983 | ///\r | |
984 | UINT64 Uint64;\r | |
985 | } MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r | |
986 | \r | |
987 | \r | |
988 | /**\r | |
ba1a2d11 | 989 | Core. See Table 2-2. See Section 18.2.4, "Architectural Performance\r |
35fd9411 HW |
990 | Monitoring Version 4.".\r |
991 | \r | |
992 | @param ECX MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r | |
993 | @param EAX Lower 32-bits of MSR value.\r | |
994 | Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
995 | @param EDX Upper 32-bits of MSR value.\r | |
996 | Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r | |
997 | \r | |
998 | <b>Example usage</b>\r | |
999 | @code\r | |
1000 | MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r | |
1001 | \r | |
1002 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET);\r | |
1003 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r | |
1004 | @endcode\r | |
1005 | @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r | |
1006 | **/\r | |
1007 | #define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r | |
1008 | \r | |
1009 | /**\r | |
1010 | MSR information returned for MSR index\r | |
1011 | #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET\r | |
1012 | **/\r | |
1013 | typedef union {\r | |
1014 | ///\r | |
1015 | /// Individual bit fields\r | |
1016 | ///\r | |
1017 | struct {\r | |
1018 | ///\r | |
1019 | /// [Bit 0] Set 1 to cause Ovf_PMC0 = 1.\r | |
1020 | ///\r | |
1021 | UINT32 Ovf_PMC0:1;\r | |
1022 | ///\r | |
1023 | /// [Bit 1] Set 1 to cause Ovf_PMC1 = 1.\r | |
1024 | ///\r | |
1025 | UINT32 Ovf_PMC1:1;\r | |
1026 | ///\r | |
1027 | /// [Bit 2] Set 1 to cause Ovf_PMC2 = 1.\r | |
1028 | ///\r | |
1029 | UINT32 Ovf_PMC2:1;\r | |
1030 | ///\r | |
1031 | /// [Bit 3] Set 1 to cause Ovf_PMC3 = 1.\r | |
1032 | ///\r | |
1033 | UINT32 Ovf_PMC3:1;\r | |
1034 | UINT32 Reserved1:28;\r | |
1035 | ///\r | |
1036 | /// [Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1.\r | |
1037 | ///\r | |
1038 | UINT32 Ovf_FixedCtr0:1;\r | |
1039 | ///\r | |
1040 | /// [Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1.\r | |
1041 | ///\r | |
1042 | UINT32 Ovf_FixedCtr1:1;\r | |
1043 | ///\r | |
1044 | /// [Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1.\r | |
1045 | ///\r | |
1046 | UINT32 Ovf_FixedCtr2:1;\r | |
1047 | UINT32 Reserved2:20;\r | |
1048 | ///\r | |
1049 | /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1.\r | |
1050 | ///\r | |
1051 | UINT32 Trace_ToPA_PMI:1;\r | |
1052 | UINT32 Reserved3:2;\r | |
1053 | ///\r | |
1054 | /// [Bit 58] Set 1 to cause LBR_Frz = 1.\r | |
1055 | ///\r | |
1056 | UINT32 LBR_Frz:1;\r | |
1057 | ///\r | |
1058 | /// [Bit 59] Set 1 to cause CTR_Frz = 1.\r | |
1059 | ///\r | |
1060 | UINT32 CTR_Frz:1;\r | |
1061 | ///\r | |
1062 | /// [Bit 60] Set 1 to cause ASCI = 1.\r | |
1063 | ///\r | |
1064 | UINT32 ASCI:1;\r | |
1065 | ///\r | |
1066 | /// [Bit 61] Set 1 to cause Ovf_Uncore.\r | |
1067 | ///\r | |
1068 | UINT32 Ovf_Uncore:1;\r | |
1069 | ///\r | |
1070 | /// [Bit 62] Set 1 to cause Ovf_BufDSSAVE.\r | |
1071 | ///\r | |
1072 | UINT32 Ovf_BufDSSAVE:1;\r | |
1073 | UINT32 Reserved4:1;\r | |
1074 | } Bits;\r | |
1075 | ///\r | |
1076 | /// All bit fields as a 64-bit value\r | |
1077 | ///\r | |
1078 | UINT64 Uint64;\r | |
1079 | } MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r | |
1080 | \r | |
1081 | \r | |
1082 | /**\r | |
ba1a2d11 | 1083 | Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r |
35fd9411 HW |
1084 | (PEBS).".\r |
1085 | \r | |
1086 | @param ECX MSR_GOLDMONT_PEBS_ENABLE (0x000003F1)\r | |
1087 | @param EAX Lower 32-bits of MSR value.\r | |
1088 | Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.\r | |
1089 | @param EDX Upper 32-bits of MSR value.\r | |
1090 | Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.\r | |
1091 | \r | |
1092 | <b>Example usage</b>\r | |
1093 | @code\r | |
1094 | MSR_GOLDMONT_PEBS_ENABLE_REGISTER Msr;\r | |
1095 | \r | |
1096 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PEBS_ENABLE);\r | |
1097 | AsmWriteMsr64 (MSR_GOLDMONT_PEBS_ENABLE, Msr.Uint64);\r | |
1098 | @endcode\r | |
1099 | @note MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r | |
1100 | **/\r | |
1101 | #define MSR_GOLDMONT_PEBS_ENABLE 0x000003F1\r | |
1102 | \r | |
1103 | /**\r | |
1104 | MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE\r | |
1105 | **/\r | |
1106 | typedef union {\r | |
1107 | ///\r | |
1108 | /// Individual bit fields\r | |
1109 | ///\r | |
1110 | struct {\r | |
1111 | ///\r | |
1112 | /// [Bit 0] Enable PEBS trigger and recording for the programmed event\r | |
1113 | /// (precise or otherwise) on IA32_PMC0. (R/W).\r | |
1114 | ///\r | |
1115 | UINT32 Enable:1;\r | |
1116 | UINT32 Reserved1:31;\r | |
1117 | UINT32 Reserved2:32;\r | |
1118 | } Bits;\r | |
1119 | ///\r | |
1120 | /// All bit fields as a 32-bit value\r | |
1121 | ///\r | |
1122 | UINT32 Uint32;\r | |
1123 | ///\r | |
1124 | /// All bit fields as a 64-bit value\r | |
1125 | ///\r | |
1126 | UINT64 Uint64;\r | |
1127 | } MSR_GOLDMONT_PEBS_ENABLE_REGISTER;\r | |
1128 | \r | |
1129 | \r | |
1130 | /**\r | |
1131 | Package. Note: C-state values are processor specific C-state code names,\r | |
1132 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r | |
1133 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
1134 | processor-specific C3 states. Count at the same frequency as the TSC.\r | |
1135 | \r | |
1136 | @param ECX MSR_GOLDMONT_PKG_C3_RESIDENCY (0x000003F8)\r | |
1137 | @param EAX Lower 32-bits of MSR value.\r | |
1138 | @param EDX Upper 32-bits of MSR value.\r | |
1139 | \r | |
1140 | <b>Example usage</b>\r | |
1141 | @code\r | |
1142 | UINT64 Msr;\r | |
1143 | \r | |
1144 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY);\r | |
1145 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY, Msr);\r | |
1146 | @endcode\r | |
1147 | @note MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r | |
1148 | **/\r | |
1149 | #define MSR_GOLDMONT_PKG_C3_RESIDENCY 0x000003F8\r | |
1150 | \r | |
1151 | \r | |
1152 | /**\r | |
1153 | Package. Note: C-state values are processor specific C-state code names,\r | |
1154 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r | |
1155 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
1156 | processor-specific C6 states. Count at the same frequency as the TSC.\r | |
1157 | \r | |
1158 | @param ECX MSR_GOLDMONT_PKG_C6_RESIDENCY (0x000003F9)\r | |
1159 | @param EAX Lower 32-bits of MSR value.\r | |
1160 | @param EDX Upper 32-bits of MSR value.\r | |
1161 | \r | |
1162 | <b>Example usage</b>\r | |
1163 | @code\r | |
1164 | UINT64 Msr;\r | |
1165 | \r | |
1166 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY);\r | |
1167 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY, Msr);\r | |
1168 | @endcode\r | |
1169 | @note MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r | |
1170 | **/\r | |
1171 | #define MSR_GOLDMONT_PKG_C6_RESIDENCY 0x000003F9\r | |
1172 | \r | |
1173 | \r | |
1174 | /**\r | |
1175 | Core. Note: C-state values are processor specific C-state code names,\r | |
1176 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r | |
1177 | Residency Counter. (R/O) Value since last reset that this core is in\r | |
1178 | processor-specific C3 states. Count at the same frequency as the TSC.\r | |
1179 | \r | |
1180 | @param ECX MSR_GOLDMONT_CORE_C3_RESIDENCY (0x000003FC)\r | |
1181 | @param EAX Lower 32-bits of MSR value.\r | |
1182 | @param EDX Upper 32-bits of MSR value.\r | |
1183 | \r | |
1184 | <b>Example usage</b>\r | |
1185 | @code\r | |
1186 | UINT64 Msr;\r | |
1187 | \r | |
1188 | Msr = AsmReadMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY);\r | |
1189 | AsmWriteMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY, Msr);\r | |
1190 | @endcode\r | |
1191 | @note MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r | |
1192 | **/\r | |
1193 | #define MSR_GOLDMONT_CORE_C3_RESIDENCY 0x000003FC\r | |
1194 | \r | |
1195 | \r | |
1196 | /**\r | |
1197 | Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability\r | |
1198 | Enhancement. Accessible only while in SMM.\r | |
1199 | \r | |
1200 | @param ECX MSR_GOLDMONT_SMM_FEATURE_CONTROL (0x000004E0)\r | |
1201 | @param EAX Lower 32-bits of MSR value.\r | |
1202 | Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.\r | |
1203 | @param EDX Upper 32-bits of MSR value.\r | |
1204 | Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.\r | |
1205 | \r | |
1206 | <b>Example usage</b>\r | |
1207 | @code\r | |
1208 | MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER Msr;\r | |
1209 | \r | |
1210 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL);\r | |
1211 | AsmWriteMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL, Msr.Uint64);\r | |
1212 | @endcode\r | |
1213 | @note MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.\r | |
1214 | **/\r | |
1215 | #define MSR_GOLDMONT_SMM_FEATURE_CONTROL 0x000004E0\r | |
1216 | \r | |
1217 | /**\r | |
1218 | MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL\r | |
1219 | **/\r | |
1220 | typedef union {\r | |
1221 | ///\r | |
1222 | /// Individual bit fields\r | |
1223 | ///\r | |
1224 | struct {\r | |
1225 | ///\r | |
1226 | /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from\r | |
1227 | /// further changes.\r | |
1228 | ///\r | |
1229 | UINT32 Lock:1;\r | |
1230 | UINT32 Reserved1:1;\r | |
1231 | ///\r | |
1232 | /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if\r | |
1233 | /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the\r | |
1234 | /// logical processors are prevented from executing SMM code outside the\r | |
1235 | /// ranges defined by the SMRR. When set to '1' any logical processor in\r | |
1236 | /// the package that attempts to execute SMM code not within the ranges\r | |
1237 | /// defined by the SMRR will assert an unrecoverable MCE.\r | |
1238 | ///\r | |
1239 | UINT32 SMM_Code_Chk_En:1;\r | |
1240 | UINT32 Reserved2:29;\r | |
1241 | UINT32 Reserved3:32;\r | |
1242 | } Bits;\r | |
1243 | ///\r | |
1244 | /// All bit fields as a 32-bit value\r | |
1245 | ///\r | |
1246 | UINT32 Uint32;\r | |
1247 | ///\r | |
1248 | /// All bit fields as a 64-bit value\r | |
1249 | ///\r | |
1250 | UINT64 Uint64;\r | |
1251 | } MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER;\r | |
1252 | \r | |
1253 | \r | |
1254 | /**\r | |
1255 | Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical\r | |
1256 | processors in the package. Available only while in SMM and\r | |
1257 | MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.\r | |
1258 | \r | |
1259 | @param ECX MSR_GOLDMONT_SMM_DELAYED (0x000004E2)\r | |
1260 | @param EAX Lower 32-bits of MSR value.\r | |
1261 | Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.\r | |
1262 | @param EDX Upper 32-bits of MSR value.\r | |
1263 | Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.\r | |
1264 | \r | |
1265 | <b>Example usage</b>\r | |
1266 | @code\r | |
1267 | MSR_GOLDMONT_SMM_DELAYED_REGISTER Msr;\r | |
1268 | \r | |
1269 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_DELAYED);\r | |
1270 | AsmWriteMsr64 (MSR_GOLDMONT_SMM_DELAYED, Msr.Uint64);\r | |
1271 | @endcode\r | |
1272 | @note MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.\r | |
1273 | **/\r | |
1274 | #define MSR_GOLDMONT_SMM_DELAYED 0x000004E2\r | |
1275 | \r | |
1276 | \r | |
1277 | /**\r | |
1278 | Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical\r | |
1279 | processors in the package. Available only while in SMM.\r | |
1280 | \r | |
1281 | @param ECX MSR_GOLDMONT_SMM_BLOCKED (0x000004E3)\r | |
1282 | @param EAX Lower 32-bits of MSR value.\r | |
1283 | Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.\r | |
1284 | @param EDX Upper 32-bits of MSR value.\r | |
1285 | Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.\r | |
1286 | \r | |
1287 | <b>Example usage</b>\r | |
1288 | @code\r | |
1289 | MSR_GOLDMONT_SMM_BLOCKED_REGISTER Msr;\r | |
1290 | \r | |
1291 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_BLOCKED);\r | |
1292 | AsmWriteMsr64 (MSR_GOLDMONT_SMM_BLOCKED, Msr.Uint64);\r | |
1293 | @endcode\r | |
1294 | @note MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.\r | |
1295 | **/\r | |
1296 | #define MSR_GOLDMONT_SMM_BLOCKED 0x000004E3\r | |
1297 | \r | |
1298 | \r | |
1299 | /**\r | |
1300 | Core. Trace Control Register (R/W).\r | |
1301 | \r | |
1302 | @param ECX MSR_GOLDMONT_IA32_RTIT_CTL (0x00000570)\r | |
1303 | @param EAX Lower 32-bits of MSR value.\r | |
1304 | Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.\r | |
1305 | @param EDX Upper 32-bits of MSR value.\r | |
1306 | Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.\r | |
1307 | \r | |
1308 | <b>Example usage</b>\r | |
1309 | @code\r | |
1310 | MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER Msr;\r | |
1311 | \r | |
1312 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL);\r | |
1313 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL, Msr.Uint64);\r | |
1314 | @endcode\r | |
1315 | @note MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.\r | |
1316 | **/\r | |
1317 | #define MSR_IA32_RTIT_CTL 0x00000570\r | |
1318 | \r | |
1319 | /**\r | |
1320 | MSR information returned for MSR index #MSR_IA32_RTIT_CTL\r | |
1321 | **/\r | |
1322 | typedef union {\r | |
1323 | ///\r | |
1324 | /// Individual bit fields\r | |
1325 | ///\r | |
1326 | struct {\r | |
1327 | ///\r | |
1328 | /// [Bit 0] TraceEn.\r | |
1329 | ///\r | |
1330 | UINT32 TraceEn:1;\r | |
1331 | ///\r | |
1332 | /// [Bit 1] CYCEn.\r | |
1333 | ///\r | |
1334 | UINT32 CYCEn:1;\r | |
1335 | ///\r | |
1336 | /// [Bit 2] OS.\r | |
1337 | ///\r | |
1338 | UINT32 OS:1;\r | |
1339 | ///\r | |
1340 | /// [Bit 3] User.\r | |
1341 | ///\r | |
1342 | UINT32 User:1;\r | |
1343 | UINT32 Reserved1:3;\r | |
1344 | ///\r | |
1345 | /// [Bit 7] CR3 filter.\r | |
1346 | ///\r | |
1347 | UINT32 CR3:1;\r | |
1348 | ///\r | |
1349 | /// [Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn.\r | |
1350 | ///\r | |
1351 | UINT32 ToPA:1;\r | |
1352 | ///\r | |
1353 | /// [Bit 9] MTCEn.\r | |
1354 | ///\r | |
1355 | UINT32 MTCEn:1;\r | |
1356 | ///\r | |
1357 | /// [Bit 10] TSCEn.\r | |
1358 | ///\r | |
1359 | UINT32 TSCEn:1;\r | |
1360 | ///\r | |
1361 | /// [Bit 11] DisRETC.\r | |
1362 | ///\r | |
1363 | UINT32 DisRETC:1;\r | |
1364 | UINT32 Reserved2:1;\r | |
1365 | ///\r | |
1366 | /// [Bit 13] BranchEn.\r | |
1367 | ///\r | |
1368 | UINT32 BranchEn:1;\r | |
1369 | ///\r | |
1370 | /// [Bits 17:14] MTCFreq.\r | |
1371 | ///\r | |
1372 | UINT32 MTCFreq:4;\r | |
1373 | UINT32 Reserved3:1;\r | |
1374 | ///\r | |
1375 | /// [Bits 22:19] CYCThresh.\r | |
1376 | ///\r | |
1377 | UINT32 CYCThresh:4;\r | |
1378 | UINT32 Reserved4:1;\r | |
1379 | ///\r | |
1380 | /// [Bits 27:24] PSBFreq.\r | |
1381 | ///\r | |
1382 | UINT32 PSBFreq:4;\r | |
1383 | UINT32 Reserved5:4;\r | |
1384 | ///\r | |
1385 | /// [Bits 35:32] ADDR0_CFG.\r | |
1386 | ///\r | |
1387 | UINT32 ADDR0_CFG:4;\r | |
1388 | ///\r | |
1389 | /// [Bits 39:36] ADDR1_CFG.\r | |
1390 | ///\r | |
1391 | UINT32 ADDR1_CFG:4;\r | |
1392 | UINT32 Reserved6:24;\r | |
1393 | } Bits;\r | |
1394 | ///\r | |
1395 | /// All bit fields as a 64-bit value\r | |
1396 | ///\r | |
1397 | UINT64 Uint64;\r | |
1398 | } MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER;\r | |
1399 | \r | |
1400 | \r | |
1401 | /**\r | |
1402 | Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r | |
1403 | "RAPL Interfaces.".\r | |
1404 | \r | |
1405 | @param ECX MSR_GOLDMONT_RAPL_POWER_UNIT (0x00000606)\r | |
1406 | @param EAX Lower 32-bits of MSR value.\r | |
1407 | Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.\r | |
1408 | @param EDX Upper 32-bits of MSR value.\r | |
1409 | Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.\r | |
1410 | \r | |
1411 | <b>Example usage</b>\r | |
1412 | @code\r | |
1413 | MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER Msr;\r | |
1414 | \r | |
1415 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_RAPL_POWER_UNIT);\r | |
1416 | @endcode\r | |
1417 | @note MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r | |
1418 | **/\r | |
1419 | #define MSR_GOLDMONT_RAPL_POWER_UNIT 0x00000606\r | |
1420 | \r | |
1421 | /**\r | |
1422 | MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT\r | |
1423 | **/\r | |
1424 | typedef union {\r | |
1425 | ///\r | |
1426 | /// Individual bit fields\r | |
1427 | ///\r | |
1428 | struct {\r | |
1429 | ///\r | |
1430 | /// [Bits 3:0] Power Units. Power related information (in Watts) is in\r | |
1431 | /// unit of, 1W/2^PU; where PU is an unsigned integer represented by bits\r | |
1432 | /// 3:0. Default value is 1000b, indicating power unit is in 3.9\r | |
1433 | /// milliWatts increment.\r | |
1434 | ///\r | |
1435 | UINT32 PowerUnits:4;\r | |
1436 | UINT32 Reserved1:4;\r | |
1437 | ///\r | |
1438 | /// [Bits 12:8] Energy Status Units. Energy related information (in\r | |
1439 | /// Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned\r | |
1440 | /// integer represented by bits 12:8. Default value is 01110b, indicating\r | |
1441 | /// energy unit is in 61 microJoules.\r | |
1442 | ///\r | |
1443 | UINT32 EnergyStatusUnits:5;\r | |
1444 | UINT32 Reserved2:3;\r | |
1445 | ///\r | |
1446 | /// [Bits 19:16] Time Unit. Time related information (in seconds) is in\r | |
1447 | /// unit of, 1S/2^TU; where TU is an unsigned integer represented by bits\r | |
1448 | /// 19:16. Default value is 1010b, indicating power unit is in 0.977\r | |
1449 | /// millisecond.\r | |
1450 | ///\r | |
1451 | UINT32 TimeUnit:4;\r | |
1452 | UINT32 Reserved3:12;\r | |
1453 | UINT32 Reserved4:32;\r | |
1454 | } Bits;\r | |
1455 | ///\r | |
1456 | /// All bit fields as a 32-bit value\r | |
1457 | ///\r | |
1458 | UINT32 Uint32;\r | |
1459 | ///\r | |
1460 | /// All bit fields as a 64-bit value\r | |
1461 | ///\r | |
1462 | UINT64 Uint64;\r | |
1463 | } MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER;\r | |
1464 | \r | |
1465 | \r | |
1466 | /**\r | |
1467 | Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are\r | |
1468 | processor specific C-state code names, unrelated to MWAIT extension C-state\r | |
1469 | parameters or ACPI CStates.\r | |
1470 | \r | |
1471 | @param ECX MSR_GOLDMONT_PKGC3_IRTL (0x0000060A)\r | |
1472 | @param EAX Lower 32-bits of MSR value.\r | |
1473 | Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.\r | |
1474 | @param EDX Upper 32-bits of MSR value.\r | |
1475 | Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.\r | |
1476 | \r | |
1477 | <b>Example usage</b>\r | |
1478 | @code\r | |
1479 | MSR_GOLDMONT_PKGC3_IRTL_REGISTER Msr;\r | |
1480 | \r | |
1481 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC3_IRTL);\r | |
1482 | AsmWriteMsr64 (MSR_GOLDMONT_PKGC3_IRTL, Msr.Uint64);\r | |
1483 | @endcode\r | |
1484 | @note MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.\r | |
1485 | **/\r | |
1486 | #define MSR_GOLDMONT_PKGC3_IRTL 0x0000060A\r | |
1487 | \r | |
1488 | /**\r | |
1489 | MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL\r | |
1490 | **/\r | |
1491 | typedef union {\r | |
1492 | ///\r | |
1493 | /// Individual bit fields\r | |
1494 | ///\r | |
1495 | struct {\r | |
1496 | ///\r | |
1497 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r | |
1498 | /// that should be used to decide if the package should be put into a\r | |
1499 | /// package C3 state.\r | |
1500 | ///\r | |
1501 | UINT32 InterruptResponseTimeLimit:10;\r | |
1502 | ///\r | |
ba1a2d11 ED |
1503 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r |
1504 | /// of the interrupt response time limit. See Table 2-19 for supported\r | |
1505 | /// time unit encodings.\r | |
35fd9411 HW |
1506 | ///\r |
1507 | UINT32 TimeUnit:3;\r | |
1508 | UINT32 Reserved1:2;\r | |
1509 | ///\r | |
1510 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r | |
1511 | /// valid and can be used by the processor for package C-sate management.\r | |
1512 | ///\r | |
1513 | UINT32 Valid:1;\r | |
1514 | UINT32 Reserved2:16;\r | |
1515 | UINT32 Reserved3:32;\r | |
1516 | } Bits;\r | |
1517 | ///\r | |
1518 | /// All bit fields as a 32-bit value\r | |
1519 | ///\r | |
1520 | UINT32 Uint32;\r | |
1521 | ///\r | |
1522 | /// All bit fields as a 64-bit value\r | |
1523 | ///\r | |
1524 | UINT64 Uint64;\r | |
1525 | } MSR_GOLDMONT_PKGC3_IRTL_REGISTER;\r | |
1526 | \r | |
1527 | \r | |
1528 | /**\r | |
1529 | Package. Package C6/C7S Interrupt Response Limit 1 (R/W) This MSR defines\r | |
1530 | the interrupt response time limit used by the processor to manage transition\r | |
1531 | to package C6 or C7S state. Note: C-state values are processor specific\r | |
1532 | C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r | |
1533 | CStates.\r | |
1534 | \r | |
1535 | @param ECX MSR_GOLDMONT_PKGC_IRTL1 (0x0000060B)\r | |
1536 | @param EAX Lower 32-bits of MSR value.\r | |
1537 | Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.\r | |
1538 | @param EDX Upper 32-bits of MSR value.\r | |
1539 | Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.\r | |
1540 | \r | |
1541 | <b>Example usage</b>\r | |
1542 | @code\r | |
1543 | MSR_GOLDMONT_PKGC_IRTL1_REGISTER Msr;\r | |
1544 | \r | |
1545 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL1);\r | |
1546 | AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL1, Msr.Uint64);\r | |
1547 | @endcode\r | |
1548 | @note MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.\r | |
1549 | **/\r | |
1550 | #define MSR_GOLDMONT_PKGC_IRTL1 0x0000060B\r | |
1551 | \r | |
1552 | /**\r | |
1553 | MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1\r | |
1554 | **/\r | |
1555 | typedef union {\r | |
1556 | ///\r | |
1557 | /// Individual bit fields\r | |
1558 | ///\r | |
1559 | struct {\r | |
1560 | ///\r | |
1561 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r | |
1562 | /// that should be used to decide if the package should be put into a\r | |
1563 | /// package C6 or C7S state.\r | |
1564 | ///\r | |
1565 | UINT32 InterruptResponseTimeLimit:10;\r | |
1566 | ///\r | |
ba1a2d11 ED |
1567 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r |
1568 | /// of the interrupt response time limit. See Table 2-19 for supported\r | |
1569 | /// time unit encodings.\r | |
35fd9411 HW |
1570 | ///\r |
1571 | UINT32 TimeUnit:3;\r | |
1572 | UINT32 Reserved1:2;\r | |
1573 | ///\r | |
1574 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r | |
1575 | /// valid and can be used by the processor for package C-sate management.\r | |
1576 | ///\r | |
1577 | UINT32 Valid:1;\r | |
1578 | UINT32 Reserved2:16;\r | |
1579 | UINT32 Reserved3:32;\r | |
1580 | } Bits;\r | |
1581 | ///\r | |
1582 | /// All bit fields as a 32-bit value\r | |
1583 | ///\r | |
1584 | UINT32 Uint32;\r | |
1585 | ///\r | |
1586 | /// All bit fields as a 64-bit value\r | |
1587 | ///\r | |
1588 | UINT64 Uint64;\r | |
1589 | } MSR_GOLDMONT_PKGC_IRTL1_REGISTER;\r | |
1590 | \r | |
1591 | \r | |
1592 | /**\r | |
1593 | Package. Package C7 Interrupt Response Limit 2 (R/W) This MSR defines the\r | |
1594 | interrupt response time limit used by the processor to manage transition to\r | |
1595 | package C7 state. Note: C-state values are processor specific C-state code\r | |
1596 | names, unrelated to MWAIT extension C-state parameters or ACPI CStates.\r | |
1597 | \r | |
1598 | @param ECX MSR_GOLDMONT_PKGC_IRTL2 (0x0000060C)\r | |
1599 | @param EAX Lower 32-bits of MSR value.\r | |
1600 | Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.\r | |
1601 | @param EDX Upper 32-bits of MSR value.\r | |
1602 | Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.\r | |
1603 | \r | |
1604 | <b>Example usage</b>\r | |
1605 | @code\r | |
1606 | MSR_GOLDMONT_PKGC_IRTL2_REGISTER Msr;\r | |
1607 | \r | |
1608 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL2);\r | |
1609 | AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL2, Msr.Uint64);\r | |
1610 | @endcode\r | |
1611 | @note MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.\r | |
1612 | **/\r | |
1613 | #define MSR_GOLDMONT_PKGC_IRTL2 0x0000060C\r | |
1614 | \r | |
1615 | /**\r | |
1616 | MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2\r | |
1617 | **/\r | |
1618 | typedef union {\r | |
1619 | ///\r | |
1620 | /// Individual bit fields\r | |
1621 | ///\r | |
1622 | struct {\r | |
1623 | ///\r | |
1624 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r | |
1625 | /// that should be used to decide if the package should be put into a\r | |
1626 | /// package C7 state.\r | |
1627 | ///\r | |
1628 | UINT32 InterruptResponseTimeLimit:10;\r | |
1629 | ///\r | |
ba1a2d11 ED |
1630 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit\r |
1631 | /// of the interrupt response time limit. See Table 2-19 for supported\r | |
1632 | /// time unit encodings.\r | |
35fd9411 HW |
1633 | ///\r |
1634 | UINT32 TimeUnit:3;\r | |
1635 | UINT32 Reserved1:2;\r | |
1636 | ///\r | |
1637 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r | |
1638 | /// valid and can be used by the processor for package C-sate management.\r | |
1639 | ///\r | |
1640 | UINT32 Valid:1;\r | |
1641 | UINT32 Reserved2:16;\r | |
1642 | UINT32 Reserved3:32;\r | |
1643 | } Bits;\r | |
1644 | ///\r | |
1645 | /// All bit fields as a 32-bit value\r | |
1646 | ///\r | |
1647 | UINT32 Uint32;\r | |
1648 | ///\r | |
1649 | /// All bit fields as a 64-bit value\r | |
1650 | ///\r | |
1651 | UINT64 Uint64;\r | |
1652 | } MSR_GOLDMONT_PKGC_IRTL2_REGISTER;\r | |
1653 | \r | |
1654 | \r | |
1655 | /**\r | |
1656 | Package. Note: C-state values are processor specific C-state code names,\r | |
1657 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2\r | |
1658 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
1659 | processor-specific C2 states. Count at the same frequency as the TSC.\r | |
1660 | \r | |
1661 | @param ECX MSR_GOLDMONT_PKG_C2_RESIDENCY (0x0000060D)\r | |
1662 | @param EAX Lower 32-bits of MSR value.\r | |
1663 | @param EDX Upper 32-bits of MSR value.\r | |
1664 | \r | |
1665 | <b>Example usage</b>\r | |
1666 | @code\r | |
1667 | UINT64 Msr;\r | |
1668 | \r | |
1669 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY);\r | |
1670 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY, Msr);\r | |
1671 | @endcode\r | |
1672 | @note MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r | |
1673 | **/\r | |
1674 | #define MSR_GOLDMONT_PKG_C2_RESIDENCY 0x0000060D\r | |
1675 | \r | |
1676 | \r | |
1677 | /**\r | |
1678 | Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r | |
1679 | RAPL Domain.".\r | |
1680 | \r | |
1681 | @param ECX MSR_GOLDMONT_PKG_POWER_LIMIT (0x00000610)\r | |
1682 | @param EAX Lower 32-bits of MSR value.\r | |
1683 | @param EDX Upper 32-bits of MSR value.\r | |
1684 | \r | |
1685 | <b>Example usage</b>\r | |
1686 | @code\r | |
1687 | UINT64 Msr;\r | |
1688 | \r | |
1689 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT);\r | |
1690 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT, Msr);\r | |
1691 | @endcode\r | |
1692 | @note MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r | |
1693 | **/\r | |
1694 | #define MSR_GOLDMONT_PKG_POWER_LIMIT 0x00000610\r | |
1695 | \r | |
1696 | \r | |
1697 | /**\r | |
1698 | Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r | |
1699 | \r | |
1700 | @param ECX MSR_GOLDMONT_PKG_ENERGY_STATUS (0x00000611)\r | |
1701 | @param EAX Lower 32-bits of MSR value.\r | |
1702 | @param EDX Upper 32-bits of MSR value.\r | |
1703 | \r | |
1704 | <b>Example usage</b>\r | |
1705 | @code\r | |
1706 | UINT64 Msr;\r | |
1707 | \r | |
1708 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_ENERGY_STATUS);\r | |
1709 | @endcode\r | |
1710 | @note MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r | |
1711 | **/\r | |
1712 | #define MSR_GOLDMONT_PKG_ENERGY_STATUS 0x00000611\r | |
1713 | \r | |
1714 | \r | |
1715 | /**\r | |
1716 | Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r | |
1717 | \r | |
1718 | @param ECX MSR_GOLDMONT_PKG_PERF_STATUS (0x00000613)\r | |
1719 | @param EAX Lower 32-bits of MSR value.\r | |
1720 | @param EDX Upper 32-bits of MSR value.\r | |
1721 | \r | |
1722 | <b>Example usage</b>\r | |
1723 | @code\r | |
1724 | UINT64 Msr;\r | |
1725 | \r | |
1726 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_PERF_STATUS);\r | |
1727 | @endcode\r | |
1728 | @note MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r | |
1729 | **/\r | |
1730 | #define MSR_GOLDMONT_PKG_PERF_STATUS 0x00000613\r | |
1731 | \r | |
1732 | \r | |
1733 | /**\r | |
1734 | Package. PKG RAPL Parameters (R/W).\r | |
1735 | \r | |
1736 | @param ECX MSR_GOLDMONT_PKG_POWER_INFO (0x00000614)\r | |
1737 | @param EAX Lower 32-bits of MSR value.\r | |
1738 | Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.\r | |
1739 | @param EDX Upper 32-bits of MSR value.\r | |
1740 | Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.\r | |
1741 | \r | |
1742 | <b>Example usage</b>\r | |
1743 | @code\r | |
1744 | MSR_GOLDMONT_PKG_POWER_INFO_REGISTER Msr;\r | |
1745 | \r | |
1746 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_INFO);\r | |
1747 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_INFO, Msr.Uint64);\r | |
1748 | @endcode\r | |
1749 | @note MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r | |
1750 | **/\r | |
1751 | #define MSR_GOLDMONT_PKG_POWER_INFO 0x00000614\r | |
1752 | \r | |
1753 | /**\r | |
1754 | MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO\r | |
1755 | **/\r | |
1756 | typedef union {\r | |
1757 | ///\r | |
1758 | /// Individual bit fields\r | |
1759 | ///\r | |
1760 | struct {\r | |
1761 | ///\r | |
1762 | /// [Bits 14:0] Thermal Spec Power (R/W) See Section 14.9.3, "Package\r | |
1763 | /// RAPL Domain.".\r | |
1764 | ///\r | |
1765 | UINT32 ThermalSpecPower:15;\r | |
1766 | UINT32 Reserved1:1;\r | |
1767 | ///\r | |
1768 | /// [Bits 30:16] Minimum Power (R/W) See Section 14.9.3, "Package RAPL\r | |
1769 | /// Domain.".\r | |
1770 | ///\r | |
1771 | UINT32 MinimumPower:15;\r | |
1772 | UINT32 Reserved2:1;\r | |
1773 | ///\r | |
1774 | /// [Bits 46:32] Maximum Power (R/W) See Section 14.9.3, "Package RAPL\r | |
1775 | /// Domain.".\r | |
1776 | ///\r | |
1777 | UINT32 MaximumPower:15;\r | |
1778 | UINT32 Reserved3:1;\r | |
1779 | ///\r | |
1780 | /// [Bits 54:48] Maximum Time Window (R/W) Specified by 2^Y * (1.0 +\r | |
1781 | /// Z/4.0) * Time_Unit, where "Y" is the unsigned integer value\r | |
1782 | /// represented. by bits 52:48, "Z" is an unsigned integer represented by\r | |
1783 | /// bits 54:53. "Time_Unit" is specified by the "Time Units" field of\r | |
1784 | /// MSR_RAPL_POWER_UNIT.\r | |
1785 | ///\r | |
1786 | UINT32 MaximumTimeWindow:7;\r | |
1787 | UINT32 Reserved4:9;\r | |
1788 | } Bits;\r | |
1789 | ///\r | |
1790 | /// All bit fields as a 64-bit value\r | |
1791 | ///\r | |
1792 | UINT64 Uint64;\r | |
1793 | } MSR_GOLDMONT_PKG_POWER_INFO_REGISTER;\r | |
1794 | \r | |
1795 | \r | |
1796 | /**\r | |
1797 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r | |
1798 | Domain.".\r | |
1799 | \r | |
1800 | @param ECX MSR_GOLDMONT_DRAM_POWER_LIMIT (0x00000618)\r | |
1801 | @param EAX Lower 32-bits of MSR value.\r | |
1802 | @param EDX Upper 32-bits of MSR value.\r | |
1803 | \r | |
1804 | <b>Example usage</b>\r | |
1805 | @code\r | |
1806 | UINT64 Msr;\r | |
1807 | \r | |
1808 | Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT);\r | |
1809 | AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT, Msr);\r | |
1810 | @endcode\r | |
1811 | @note MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r | |
1812 | **/\r | |
1813 | #define MSR_GOLDMONT_DRAM_POWER_LIMIT 0x00000618\r | |
1814 | \r | |
1815 | \r | |
1816 | /**\r | |
1817 | Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
1818 | \r | |
1819 | @param ECX MSR_GOLDMONT_DRAM_ENERGY_STATUS (0x00000619)\r | |
1820 | @param EAX Lower 32-bits of MSR value.\r | |
1821 | @param EDX Upper 32-bits of MSR value.\r | |
1822 | \r | |
1823 | <b>Example usage</b>\r | |
1824 | @code\r | |
1825 | UINT64 Msr;\r | |
1826 | \r | |
1827 | Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_ENERGY_STATUS);\r | |
1828 | @endcode\r | |
1829 | @note MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r | |
1830 | **/\r | |
1831 | #define MSR_GOLDMONT_DRAM_ENERGY_STATUS 0x00000619\r | |
1832 | \r | |
1833 | \r | |
1834 | /**\r | |
1835 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r | |
1836 | RAPL Domain.".\r | |
1837 | \r | |
1838 | @param ECX MSR_GOLDMONT_DRAM_PERF_STATUS (0x0000061B)\r | |
1839 | @param EAX Lower 32-bits of MSR value.\r | |
1840 | @param EDX Upper 32-bits of MSR value.\r | |
1841 | \r | |
1842 | <b>Example usage</b>\r | |
1843 | @code\r | |
1844 | UINT64 Msr;\r | |
1845 | \r | |
1846 | Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_PERF_STATUS);\r | |
1847 | @endcode\r | |
1848 | @note MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r | |
1849 | **/\r | |
1850 | #define MSR_GOLDMONT_DRAM_PERF_STATUS 0x0000061B\r | |
1851 | \r | |
1852 | \r | |
1853 | /**\r | |
1854 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
1855 | \r | |
1856 | @param ECX MSR_GOLDMONT_DRAM_POWER_INFO (0x0000061C)\r | |
1857 | @param EAX Lower 32-bits of MSR value.\r | |
1858 | @param EDX Upper 32-bits of MSR value.\r | |
1859 | \r | |
1860 | <b>Example usage</b>\r | |
1861 | @code\r | |
1862 | UINT64 Msr;\r | |
1863 | \r | |
1864 | Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO);\r | |
1865 | AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO, Msr);\r | |
1866 | @endcode\r | |
1867 | @note MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r | |
1868 | **/\r | |
1869 | #define MSR_GOLDMONT_DRAM_POWER_INFO 0x0000061C\r | |
1870 | \r | |
1871 | \r | |
1872 | /**\r | |
1873 | Package. Note: C-state values are processor specific C-state code names,.\r | |
1874 | Package C10 Residency Counter. (R/O) Value since last reset that the entire\r | |
1875 | SOC is in an S0i3 state. Count at the same frequency as the TSC.\r | |
1876 | \r | |
1877 | @param ECX MSR_GOLDMONT_PKG_C10_RESIDENCY (0x00000632)\r | |
1878 | @param EAX Lower 32-bits of MSR value.\r | |
1879 | @param EDX Upper 32-bits of MSR value.\r | |
1880 | \r | |
1881 | <b>Example usage</b>\r | |
1882 | @code\r | |
1883 | UINT64 Msr;\r | |
1884 | \r | |
1885 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY);\r | |
1886 | AsmWriteMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY, Msr);\r | |
1887 | @endcode\r | |
1888 | @note MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r | |
1889 | **/\r | |
1890 | #define MSR_GOLDMONT_PKG_C10_RESIDENCY 0x00000632\r | |
1891 | \r | |
1892 | \r | |
1893 | /**\r | |
1894 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
1895 | Domains.".\r | |
1896 | \r | |
1897 | @param ECX MSR_GOLDMONT_PP0_ENERGY_STATUS (0x00000639)\r | |
1898 | @param EAX Lower 32-bits of MSR value.\r | |
1899 | @param EDX Upper 32-bits of MSR value.\r | |
1900 | \r | |
1901 | <b>Example usage</b>\r | |
1902 | @code\r | |
1903 | UINT64 Msr;\r | |
1904 | \r | |
1905 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PP0_ENERGY_STATUS);\r | |
1906 | @endcode\r | |
1907 | @note MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r | |
1908 | **/\r | |
1909 | #define MSR_GOLDMONT_PP0_ENERGY_STATUS 0x00000639\r | |
1910 | \r | |
1911 | \r | |
1912 | /**\r | |
1913 | Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
1914 | Domains.".\r | |
1915 | \r | |
1916 | @param ECX MSR_GOLDMONT_PP1_ENERGY_STATUS (0x00000641)\r | |
1917 | @param EAX Lower 32-bits of MSR value.\r | |
1918 | @param EDX Upper 32-bits of MSR value.\r | |
1919 | \r | |
1920 | <b>Example usage</b>\r | |
1921 | @code\r | |
1922 | UINT64 Msr;\r | |
1923 | \r | |
1924 | Msr = AsmReadMsr64 (MSR_GOLDMONT_PP1_ENERGY_STATUS);\r | |
1925 | @endcode\r | |
1926 | @note MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r | |
1927 | **/\r | |
1928 | #define MSR_GOLDMONT_PP1_ENERGY_STATUS 0x00000641\r | |
1929 | \r | |
1930 | \r | |
1931 | /**\r | |
1932 | Package. ConfigTDP Control (R/W).\r | |
1933 | \r | |
1934 | @param ECX MSR_GOLDMONT_TURBO_ACTIVATION_RATIO (0x0000064C)\r | |
1935 | @param EAX Lower 32-bits of MSR value.\r | |
1936 | Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.\r | |
1937 | @param EDX Upper 32-bits of MSR value.\r | |
1938 | Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.\r | |
1939 | \r | |
1940 | <b>Example usage</b>\r | |
1941 | @code\r | |
1942 | MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r | |
1943 | \r | |
1944 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO);\r | |
1945 | AsmWriteMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r | |
1946 | @endcode\r | |
1947 | @note MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r | |
1948 | **/\r | |
1949 | #define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO 0x0000064C\r | |
1950 | \r | |
1951 | /**\r | |
1952 | MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO\r | |
1953 | **/\r | |
1954 | typedef union {\r | |
1955 | ///\r | |
1956 | /// Individual bit fields\r | |
1957 | ///\r | |
1958 | struct {\r | |
1959 | ///\r | |
1960 | /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r | |
1961 | /// field.\r | |
1962 | ///\r | |
1963 | UINT32 MAX_NON_TURBO_RATIO:8;\r | |
1964 | UINT32 Reserved1:23;\r | |
1965 | ///\r | |
1966 | /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r | |
1967 | /// content of this register is locked until a reset.\r | |
1968 | ///\r | |
1969 | UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r | |
1970 | UINT32 Reserved2:32;\r | |
1971 | } Bits;\r | |
1972 | ///\r | |
1973 | /// All bit fields as a 32-bit value\r | |
1974 | ///\r | |
1975 | UINT32 Uint32;\r | |
1976 | ///\r | |
1977 | /// All bit fields as a 64-bit value\r | |
1978 | ///\r | |
1979 | UINT64 Uint64;\r | |
1980 | } MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER;\r | |
1981 | \r | |
1982 | \r | |
1983 | /**\r | |
1984 | Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r | |
1985 | refers to processor core frequency).\r | |
1986 | \r | |
1987 | @param ECX MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS (0x0000064F)\r | |
1988 | @param EAX Lower 32-bits of MSR value.\r | |
1989 | Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
1990 | @param EDX Upper 32-bits of MSR value.\r | |
1991 | Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
1992 | \r | |
1993 | <b>Example usage</b>\r | |
1994 | @code\r | |
1995 | MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
1996 | \r | |
1997 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS);\r | |
1998 | AsmWriteMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
1999 | @endcode\r | |
2000 | @note MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r | |
2001 | **/\r | |
2002 | #define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS 0x0000064F\r | |
2003 | \r | |
2004 | /**\r | |
2005 | MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS\r | |
2006 | **/\r | |
2007 | typedef union {\r | |
2008 | ///\r | |
2009 | /// Individual bit fields\r | |
2010 | ///\r | |
2011 | struct {\r | |
2012 | ///\r | |
2013 | /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r | |
2014 | /// reduced below the operating system request due to assertion of\r | |
2015 | /// external PROCHOT.\r | |
2016 | ///\r | |
2017 | UINT32 PROCHOTStatus:1;\r | |
2018 | ///\r | |
2019 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r | |
2020 | /// operating system request due to a thermal event.\r | |
2021 | ///\r | |
2022 | UINT32 ThermalStatus:1;\r | |
2023 | ///\r | |
2024 | /// [Bit 2] Package-Level Power Limiting PL1 Status (R0) When set,\r | |
2025 | /// frequency is reduced below the operating system request due to\r | |
2026 | /// package-level power limiting PL1.\r | |
2027 | ///\r | |
2028 | UINT32 PL1Status:1;\r | |
2029 | ///\r | |
2030 | /// [Bit 3] Package-Level PL2 Power Limiting Status (R0) When set,\r | |
2031 | /// frequency is reduced below the operating system request due to\r | |
2032 | /// package-level power limiting PL2.\r | |
2033 | ///\r | |
2034 | UINT32 PL2Status:1;\r | |
2035 | UINT32 Reserved1:5;\r | |
2036 | ///\r | |
2037 | /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced\r | |
2038 | /// below the operating system request due to domain-level power limiting.\r | |
2039 | ///\r | |
2040 | UINT32 PowerLimitingStatus:1;\r | |
2041 | ///\r | |
2042 | /// [Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced\r | |
2043 | /// below the operating system request due to a thermal alert from the\r | |
2044 | /// Voltage Regulator.\r | |
2045 | ///\r | |
2046 | UINT32 VRThermAlertStatus:1;\r | |
2047 | ///\r | |
2048 | /// [Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced\r | |
2049 | /// below the operating system request due to multi-core turbo limits.\r | |
2050 | ///\r | |
2051 | UINT32 MaxTurboLimitStatus:1;\r | |
2052 | ///\r | |
2053 | /// [Bit 12] Electrical Design Point Status (R0) When set, frequency is\r | |
2054 | /// reduced below the operating system request due to electrical design\r | |
2055 | /// point constraints (e.g. maximum electrical current consumption).\r | |
2056 | ///\r | |
2057 | UINT32 ElectricalDesignPointStatus:1;\r | |
2058 | ///\r | |
2059 | /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r | |
2060 | /// is reduced below the operating system request due to Turbo transition\r | |
2061 | /// attenuation. This prevents performance degradation due to frequent\r | |
2062 | /// operating ratio changes.\r | |
2063 | ///\r | |
2064 | UINT32 TurboTransitionAttenuationStatus:1;\r | |
2065 | ///\r | |
2066 | /// [Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency\r | |
2067 | /// is reduced below the maximum efficiency frequency.\r | |
2068 | ///\r | |
2069 | UINT32 MaximumEfficiencyFrequencyStatus:1;\r | |
2070 | UINT32 Reserved2:1;\r | |
2071 | ///\r | |
2072 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r | |
2073 | /// has asserted since the log bit was last cleared. This log bit will\r | |
2074 | /// remain set until cleared by software writing 0.\r | |
2075 | ///\r | |
2076 | UINT32 PROCHOT:1;\r | |
2077 | ///\r | |
2078 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r | |
2079 | /// has asserted since the log bit was last cleared. This log bit will\r | |
2080 | /// remain set until cleared by software writing 0.\r | |
2081 | ///\r | |
2082 | UINT32 ThermalLog:1;\r | |
2083 | ///\r | |
2084 | /// [Bit 18] Package-Level PL1 Power Limiting Log When set, indicates\r | |
2085 | /// that the Package Level PL1 Power Limiting Status bit has asserted\r | |
2086 | /// since the log bit was last cleared. This log bit will remain set until\r | |
2087 | /// cleared by software writing 0.\r | |
2088 | ///\r | |
2089 | UINT32 PL1Log:1;\r | |
2090 | ///\r | |
2091 | /// [Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that\r | |
2092 | /// the Package Level PL2 Power Limiting Status bit has asserted since the\r | |
2093 | /// log bit was last cleared. This log bit will remain set until cleared\r | |
2094 | /// by software writing 0.\r | |
2095 | ///\r | |
2096 | UINT32 PL2Log:1;\r | |
2097 | UINT32 Reserved3:5;\r | |
2098 | ///\r | |
2099 | /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r | |
2100 | /// Power Limiting Status bit has asserted since the log bit was last\r | |
2101 | /// cleared. This log bit will remain set until cleared by software\r | |
2102 | /// writing 0.\r | |
2103 | ///\r | |
2104 | UINT32 CorePowerLimitingLog:1;\r | |
2105 | ///\r | |
2106 | /// [Bit 26] VR Therm Alert Log When set, indicates that the VR Therm\r | |
2107 | /// Alert Status bit has asserted since the log bit was last cleared. This\r | |
2108 | /// log bit will remain set until cleared by software writing 0.\r | |
2109 | ///\r | |
2110 | UINT32 VRThermAlertLog:1;\r | |
2111 | ///\r | |
2112 | /// [Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo\r | |
2113 | /// Limit Status bit has asserted since the log bit was last cleared. This\r | |
2114 | /// log bit will remain set until cleared by software writing 0.\r | |
2115 | ///\r | |
2116 | UINT32 MaxTurboLimitLog:1;\r | |
2117 | ///\r | |
2118 | /// [Bit 28] Electrical Design Point Log When set, indicates that the EDP\r | |
2119 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
2120 | /// bit will remain set until cleared by software writing 0.\r | |
2121 | ///\r | |
2122 | UINT32 ElectricalDesignPointLog:1;\r | |
2123 | ///\r | |
2124 | /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r | |
2125 | /// Turbo Transition Attenuation Status bit has asserted since the log bit\r | |
2126 | /// was last cleared. This log bit will remain set until cleared by\r | |
2127 | /// software writing 0.\r | |
2128 | ///\r | |
2129 | UINT32 TurboTransitionAttenuationLog:1;\r | |
2130 | ///\r | |
2131 | /// [Bit 30] Maximum Efficiency Frequency Log When set, indicates that\r | |
2132 | /// the Maximum Efficiency Frequency Status bit has asserted since the log\r | |
2133 | /// bit was last cleared. This log bit will remain set until cleared by\r | |
2134 | /// software writing 0.\r | |
2135 | ///\r | |
2136 | UINT32 MaximumEfficiencyFrequencyLog:1;\r | |
2137 | UINT32 Reserved4:1;\r | |
2138 | UINT32 Reserved5:32;\r | |
2139 | } Bits;\r | |
2140 | ///\r | |
2141 | /// All bit fields as a 32-bit value\r | |
2142 | ///\r | |
2143 | UINT32 Uint32;\r | |
2144 | ///\r | |
2145 | /// All bit fields as a 64-bit value\r | |
2146 | ///\r | |
2147 | UINT64 Uint64;\r | |
2148 | } MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER;\r | |
2149 | \r | |
2150 | \r | |
2151 | /**\r | |
2152 | Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch\r | |
2153 | record registers on the last branch record stack. The From_IP part of the\r | |
2154 | stack contains pointers to the source instruction . See also: - Last Branch\r | |
2155 | Record Stack TOS at 1C9H - Section 17.6 and record format in Section\r | |
2156 | 17.4.8.1.\r | |
2157 | \r | |
2158 | @param ECX MSR_GOLDMONT_LASTBRANCH_n_FROM_IP\r | |
2159 | @param EAX Lower 32-bits of MSR value.\r | |
2160 | Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.\r | |
2161 | @param EDX Upper 32-bits of MSR value.\r | |
2162 | Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.\r | |
2163 | \r | |
2164 | <b>Example usage</b>\r | |
2165 | @code\r | |
2166 | MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER Msr;\r | |
2167 | \r | |
2168 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP);\r | |
2169 | AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP, Msr.Uint64);\r | |
2170 | @endcode\r | |
2171 | @note MSR_GOLDMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r | |
2172 | MSR_GOLDMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r | |
2173 | MSR_GOLDMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r | |
2174 | MSR_GOLDMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r | |
2175 | MSR_GOLDMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r | |
2176 | MSR_GOLDMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r | |
2177 | MSR_GOLDMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r | |
2178 | MSR_GOLDMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r | |
2179 | MSR_GOLDMONT_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r | |
2180 | MSR_GOLDMONT_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r | |
2181 | MSR_GOLDMONT_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r | |
2182 | MSR_GOLDMONT_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r | |
2183 | MSR_GOLDMONT_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r | |
2184 | MSR_GOLDMONT_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r | |
2185 | MSR_GOLDMONT_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r | |
2186 | MSR_GOLDMONT_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r | |
2187 | MSR_GOLDMONT_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.\r | |
2188 | MSR_GOLDMONT_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.\r | |
2189 | MSR_GOLDMONT_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.\r | |
2190 | MSR_GOLDMONT_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.\r | |
2191 | MSR_GOLDMONT_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.\r | |
2192 | MSR_GOLDMONT_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.\r | |
2193 | MSR_GOLDMONT_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.\r | |
2194 | MSR_GOLDMONT_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.\r | |
2195 | MSR_GOLDMONT_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.\r | |
2196 | MSR_GOLDMONT_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.\r | |
2197 | MSR_GOLDMONT_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.\r | |
2198 | MSR_GOLDMONT_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.\r | |
2199 | MSR_GOLDMONT_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.\r | |
2200 | MSR_GOLDMONT_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.\r | |
2201 | MSR_GOLDMONT_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.\r | |
2202 | MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r | |
2203 | @{\r | |
2204 | **/\r | |
2205 | #define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP 0x00000680\r | |
2206 | #define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP 0x00000681\r | |
2207 | #define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP 0x00000682\r | |
2208 | #define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP 0x00000683\r | |
2209 | #define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP 0x00000684\r | |
2210 | #define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP 0x00000685\r | |
2211 | #define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP 0x00000686\r | |
2212 | #define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP 0x00000687\r | |
2213 | #define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP 0x00000688\r | |
2214 | #define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP 0x00000689\r | |
2215 | #define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP 0x0000068A\r | |
2216 | #define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP 0x0000068B\r | |
2217 | #define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP 0x0000068C\r | |
2218 | #define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP 0x0000068D\r | |
2219 | #define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP 0x0000068E\r | |
2220 | #define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP 0x0000068F\r | |
2221 | #define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP 0x00000690\r | |
2222 | #define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP 0x00000691\r | |
2223 | #define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP 0x00000692\r | |
2224 | #define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP 0x00000693\r | |
2225 | #define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP 0x00000694\r | |
2226 | #define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP 0x00000695\r | |
2227 | #define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP 0x00000696\r | |
2228 | #define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP 0x00000697\r | |
2229 | #define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP 0x00000698\r | |
2230 | #define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP 0x00000699\r | |
2231 | #define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP 0x0000069A\r | |
2232 | #define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP 0x0000069B\r | |
2233 | #define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP 0x0000069C\r | |
2234 | #define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP 0x0000069D\r | |
2235 | #define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP 0x0000069E\r | |
2236 | #define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP 0x0000069F\r | |
2237 | /// @}\r | |
2238 | \r | |
2239 | /**\r | |
2240 | MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_FROM_IP\r | |
2241 | to #MSR_GOLDMONT_LASTBRANCH_31_FROM_IP.\r | |
2242 | **/\r | |
2243 | typedef union {\r | |
2244 | ///\r | |
2245 | /// Individual bit fields\r | |
2246 | ///\r | |
2247 | struct {\r | |
2248 | ///\r | |
2249 | /// [Bit 31:0] From Linear Address (R/W).\r | |
2250 | ///\r | |
2251 | UINT32 FromLinearAddress:32;\r | |
2252 | ///\r | |
2253 | /// [Bit 47:32] From Linear Address (R/W).\r | |
2254 | ///\r | |
2255 | UINT32 FromLinearAddressHi:16;\r | |
2256 | ///\r | |
2257 | /// [Bits 62:48] Signed extension of bits 47:0.\r | |
2258 | ///\r | |
2259 | UINT32 SignedExtension:15;\r | |
2260 | ///\r | |
2261 | /// [Bit 63] Mispred.\r | |
2262 | ///\r | |
2263 | UINT32 Mispred:1;\r | |
2264 | } Bits;\r | |
2265 | ///\r | |
2266 | /// All bit fields as a 32-bit value\r | |
2267 | ///\r | |
2268 | UINT32 Uint32;\r | |
2269 | ///\r | |
2270 | /// All bit fields as a 64-bit value\r | |
2271 | ///\r | |
2272 | UINT64 Uint64;\r | |
2273 | } MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER;\r | |
2274 | \r | |
2275 | \r | |
2276 | /**\r | |
2277 | Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record\r | |
2278 | registers on the last branch record stack. The To_IP part of the stack\r | |
2279 | contains pointers to the Destination instruction and elapsed cycles from\r | |
2280 | last LBR update. See also: - Section 17.6.\r | |
2281 | \r | |
2282 | @param ECX MSR_GOLDMONT_LASTBRANCH_n_TO_IP\r | |
2283 | @param EAX Lower 32-bits of MSR value.\r | |
2284 | Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.\r | |
2285 | @param EDX Upper 32-bits of MSR value.\r | |
2286 | Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.\r | |
2287 | \r | |
2288 | <b>Example usage</b>\r | |
2289 | @code\r | |
2290 | MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER Msr;\r | |
2291 | \r | |
2292 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP);\r | |
2293 | AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP, Msr.Uint64);\r | |
2294 | @endcode\r | |
2295 | @note MSR_GOLDMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r | |
2296 | MSR_GOLDMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r | |
2297 | MSR_GOLDMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r | |
2298 | MSR_GOLDMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r | |
2299 | MSR_GOLDMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r | |
2300 | MSR_GOLDMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r | |
2301 | MSR_GOLDMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r | |
2302 | MSR_GOLDMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r | |
2303 | MSR_GOLDMONT_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r | |
2304 | MSR_GOLDMONT_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r | |
2305 | MSR_GOLDMONT_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r | |
2306 | MSR_GOLDMONT_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r | |
2307 | MSR_GOLDMONT_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r | |
2308 | MSR_GOLDMONT_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r | |
2309 | MSR_GOLDMONT_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r | |
2310 | MSR_GOLDMONT_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r | |
2311 | MSR_GOLDMONT_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.\r | |
2312 | MSR_GOLDMONT_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.\r | |
2313 | MSR_GOLDMONT_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.\r | |
2314 | MSR_GOLDMONT_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.\r | |
2315 | MSR_GOLDMONT_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.\r | |
2316 | MSR_GOLDMONT_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.\r | |
2317 | MSR_GOLDMONT_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.\r | |
2318 | MSR_GOLDMONT_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.\r | |
2319 | MSR_GOLDMONT_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.\r | |
2320 | MSR_GOLDMONT_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.\r | |
2321 | MSR_GOLDMONT_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.\r | |
2322 | MSR_GOLDMONT_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.\r | |
2323 | MSR_GOLDMONT_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.\r | |
2324 | MSR_GOLDMONT_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.\r | |
2325 | MSR_GOLDMONT_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.\r | |
2326 | MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r | |
2327 | @{\r | |
2328 | **/\r | |
2329 | #define MSR_GOLDMONT_LASTBRANCH_0_TO_IP 0x000006C0\r | |
2330 | #define MSR_GOLDMONT_LASTBRANCH_1_TO_IP 0x000006C1\r | |
2331 | #define MSR_GOLDMONT_LASTBRANCH_2_TO_IP 0x000006C2\r | |
2332 | #define MSR_GOLDMONT_LASTBRANCH_3_TO_IP 0x000006C3\r | |
2333 | #define MSR_GOLDMONT_LASTBRANCH_4_TO_IP 0x000006C4\r | |
2334 | #define MSR_GOLDMONT_LASTBRANCH_5_TO_IP 0x000006C5\r | |
2335 | #define MSR_GOLDMONT_LASTBRANCH_6_TO_IP 0x000006C6\r | |
2336 | #define MSR_GOLDMONT_LASTBRANCH_7_TO_IP 0x000006C7\r | |
2337 | #define MSR_GOLDMONT_LASTBRANCH_8_TO_IP 0x000006C8\r | |
2338 | #define MSR_GOLDMONT_LASTBRANCH_9_TO_IP 0x000006C9\r | |
2339 | #define MSR_GOLDMONT_LASTBRANCH_10_TO_IP 0x000006CA\r | |
2340 | #define MSR_GOLDMONT_LASTBRANCH_11_TO_IP 0x000006CB\r | |
2341 | #define MSR_GOLDMONT_LASTBRANCH_12_TO_IP 0x000006CC\r | |
2342 | #define MSR_GOLDMONT_LASTBRANCH_13_TO_IP 0x000006CD\r | |
2343 | #define MSR_GOLDMONT_LASTBRANCH_14_TO_IP 0x000006CE\r | |
2344 | #define MSR_GOLDMONT_LASTBRANCH_15_TO_IP 0x000006CF\r | |
2345 | #define MSR_GOLDMONT_LASTBRANCH_16_TO_IP 0x000006D0\r | |
2346 | #define MSR_GOLDMONT_LASTBRANCH_17_TO_IP 0x000006D1\r | |
2347 | #define MSR_GOLDMONT_LASTBRANCH_18_TO_IP 0x000006D2\r | |
2348 | #define MSR_GOLDMONT_LASTBRANCH_19_TO_IP 0x000006D3\r | |
2349 | #define MSR_GOLDMONT_LASTBRANCH_20_TO_IP 0x000006D4\r | |
2350 | #define MSR_GOLDMONT_LASTBRANCH_21_TO_IP 0x000006D5\r | |
2351 | #define MSR_GOLDMONT_LASTBRANCH_22_TO_IP 0x000006D6\r | |
2352 | #define MSR_GOLDMONT_LASTBRANCH_23_TO_IP 0x000006D7\r | |
2353 | #define MSR_GOLDMONT_LASTBRANCH_24_TO_IP 0x000006D8\r | |
2354 | #define MSR_GOLDMONT_LASTBRANCH_25_TO_IP 0x000006D9\r | |
2355 | #define MSR_GOLDMONT_LASTBRANCH_26_TO_IP 0x000006DA\r | |
2356 | #define MSR_GOLDMONT_LASTBRANCH_27_TO_IP 0x000006DB\r | |
2357 | #define MSR_GOLDMONT_LASTBRANCH_28_TO_IP 0x000006DC\r | |
2358 | #define MSR_GOLDMONT_LASTBRANCH_29_TO_IP 0x000006DD\r | |
2359 | #define MSR_GOLDMONT_LASTBRANCH_30_TO_IP 0x000006DE\r | |
2360 | #define MSR_GOLDMONT_LASTBRANCH_31_TO_IP 0x000006DF\r | |
2361 | /// @}\r | |
2362 | \r | |
2363 | /**\r | |
2364 | MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_TO_IP to\r | |
2365 | #MSR_GOLDMONT_LASTBRANCH_31_TO_IP.\r | |
2366 | **/\r | |
2367 | typedef union {\r | |
2368 | ///\r | |
2369 | /// Individual bit fields\r | |
2370 | ///\r | |
2371 | struct {\r | |
2372 | ///\r | |
2373 | /// [Bit 31:0] Target Linear Address (R/W).\r | |
2374 | ///\r | |
2375 | UINT32 TargetLinearAddress:32;\r | |
2376 | ///\r | |
2377 | /// [Bit 47:32] Target Linear Address (R/W).\r | |
2378 | ///\r | |
2379 | UINT32 TargetLinearAddressHi:16;\r | |
2380 | ///\r | |
2381 | /// [Bits 63:48] Elapsed cycles from last update to the LBR.\r | |
2382 | ///\r | |
2383 | UINT32 ElapsedCycles:16;\r | |
2384 | } Bits;\r | |
2385 | ///\r | |
2386 | /// All bit fields as a 32-bit value\r | |
2387 | ///\r | |
2388 | UINT32 Uint32;\r | |
2389 | ///\r | |
2390 | /// All bit fields as a 64-bit value\r | |
2391 | ///\r | |
2392 | UINT64 Uint64;\r | |
2393 | } MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER;\r | |
2394 | \r | |
2395 | \r | |
2396 | /**\r | |
2397 | Core. Resource Association Register (R/W).\r | |
2398 | \r | |
2399 | @param ECX MSR_GOLDMONT_IA32_PQR_ASSOC (0x00000C8F)\r | |
2400 | @param EAX Lower 32-bits of MSR value.\r | |
2401 | Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.\r | |
2402 | @param EDX Upper 32-bits of MSR value.\r | |
2403 | Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.\r | |
2404 | \r | |
2405 | <b>Example usage</b>\r | |
2406 | @code\r | |
2407 | MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER Msr;\r | |
2408 | \r | |
2409 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC);\r | |
2410 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC, Msr.Uint64);\r | |
2411 | @endcode\r | |
2412 | @note MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r | |
2413 | **/\r | |
2414 | #define MSR_GOLDMONT_IA32_PQR_ASSOC 0x00000C8F\r | |
2415 | \r | |
2416 | /**\r | |
2417 | MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC\r | |
2418 | **/\r | |
2419 | typedef union {\r | |
2420 | ///\r | |
2421 | /// Individual bit fields\r | |
2422 | ///\r | |
2423 | struct {\r | |
2424 | UINT32 Reserved1:32;\r | |
2425 | ///\r | |
2426 | /// [Bits 33:32] COS (R/W).\r | |
2427 | ///\r | |
2428 | UINT32 COS:2;\r | |
2429 | UINT32 Reserved2:30;\r | |
2430 | } Bits;\r | |
2431 | ///\r | |
2432 | /// All bit fields as a 64-bit value\r | |
2433 | ///\r | |
2434 | UINT64 Uint64;\r | |
2435 | } MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER;\r | |
2436 | \r | |
2437 | \r | |
2438 | /**\r | |
2439 | Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r | |
2440 | ECX=1):EDX.COS_MAX[15:0] >=n.\r | |
2441 | \r | |
2442 | @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_n\r | |
2443 | @param EAX Lower 32-bits of MSR value.\r | |
2444 | Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.\r | |
2445 | @param EDX Upper 32-bits of MSR value.\r | |
2446 | Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.\r | |
2447 | \r | |
2448 | <b>Example usage</b>\r | |
2449 | @code\r | |
2450 | MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER Msr;\r | |
2451 | \r | |
2452 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n);\r | |
2453 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n, Msr.Uint64);\r | |
2454 | @endcode\r | |
2455 | @note MSR_GOLDMONT_IA32_L2_QOS_MASK_0 is defined as IA32_L2_QOS_MASK_0 in SDM.\r | |
2456 | MSR_GOLDMONT_IA32_L2_QOS_MASK_1 is defined as IA32_L2_QOS_MASK_1 in SDM.\r | |
2457 | MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM.\r | |
2458 | @{\r | |
2459 | **/\r | |
2460 | #define MSR_GOLDMONT_IA32_L2_QOS_MASK_0 0x00000D10\r | |
2461 | #define MSR_GOLDMONT_IA32_L2_QOS_MASK_1 0x00000D11\r | |
2462 | #define MSR_GOLDMONT_IA32_L2_QOS_MASK_2 0x00000D12\r | |
2463 | /// @}\r | |
2464 | \r | |
2465 | /**\r | |
2466 | MSR information returned for MSR indexes #MSR_GOLDMONT_IA32_L2_QOS_MASK_0 to\r | |
2467 | #MSR_GOLDMONT_IA32_L2_QOS_MASK_2.\r | |
2468 | **/\r | |
2469 | typedef union {\r | |
2470 | ///\r | |
2471 | /// Individual bit fields\r | |
2472 | ///\r | |
2473 | struct {\r | |
2474 | ///\r | |
2475 | /// [Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement\r | |
2476 | ///\r | |
2477 | UINT32 CBM:8;\r | |
2478 | UINT32 Reserved1:24;\r | |
2479 | UINT32 Reserved2:32;\r | |
2480 | } Bits;\r | |
2481 | ///\r | |
2482 | /// All bit fields as a 32-bit value\r | |
2483 | ///\r | |
2484 | UINT32 Uint32;\r | |
2485 | ///\r | |
2486 | /// All bit fields as a 64-bit value\r | |
2487 | ///\r | |
2488 | UINT64 Uint64;\r | |
2489 | } MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER;\r | |
2490 | \r | |
2491 | \r | |
2492 | /**\r | |
2493 | Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H,\r | |
2494 | ECX=1):EDX.COS_MAX[15:0] >=3.\r | |
2495 | \r | |
2496 | @param ECX MSR_GOLDMONT_IA32_L2_QOS_MASK_3\r | |
2497 | @param EAX Lower 32-bits of MSR value.\r | |
2498 | Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.\r | |
2499 | @param EDX Upper 32-bits of MSR value.\r | |
2500 | Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.\r | |
2501 | \r | |
2502 | <b>Example usage</b>\r | |
2503 | @code\r | |
2504 | MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER Msr;\r | |
2505 | \r | |
2506 | Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3);\r | |
2507 | AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3, Msr.Uint64);\r | |
2508 | @endcode\r | |
2509 | @note MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM.\r | |
2510 | **/\r | |
2511 | #define MSR_GOLDMONT_IA32_L2_QOS_MASK_3 0x00000D13\r | |
2512 | \r | |
2513 | /**\r | |
2514 | MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3.\r | |
2515 | **/\r | |
2516 | typedef union {\r | |
2517 | ///\r | |
2518 | /// Individual bit fields\r | |
2519 | ///\r | |
2520 | struct {\r | |
2521 | ///\r | |
2522 | /// [Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement\r | |
2523 | ///\r | |
2524 | UINT32 CBM:20;\r | |
2525 | UINT32 Reserved1:12;\r | |
2526 | UINT32 Reserved2:32;\r | |
2527 | } Bits;\r | |
2528 | ///\r | |
2529 | /// All bit fields as a 32-bit value\r | |
2530 | ///\r | |
2531 | UINT32 Uint32;\r | |
2532 | ///\r | |
2533 | /// All bit fields as a 64-bit value\r | |
2534 | ///\r | |
2535 | UINT64 Uint64;\r | |
2536 | } MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER;\r | |
2537 | \r | |
2538 | \r | |
2539 | #endif\r |