projects / mirror_edk2.git / blame
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| 84ada87c MK |
1 | /** @file\r |
| 2 | MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| ba1a2d11 | 9 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| 0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 84ada87c MK |
11 | \r |
| 12 | @par Specification Reference:\r | |
| ba1a2d11 ED |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
| 84ada87c MK |
15 | \r |
| 16 | **/\r | |
| 17 | \r | |
| 18 | #ifndef __IVY_BRIDGE_MSR_H__\r | |
| 19 | #define __IVY_BRIDGE_MSR_H__\r | |
| 20 | \r | |
| 21 | #include <Register/ArchitecturalMsr.h>\r | |
| 22 | \r | |
| f4c982bf JF |
23 | /**\r |
| 24 | Is Intel processors based on the Ivy Bridge microarchitecture?\r | |
| 25 | \r | |
| 26 | @param DisplayFamily Display Family ID\r | |
| 27 | @param DisplayModel Display Model ID\r | |
| 28 | \r | |
| 29 | @retval TRUE Yes, it is.\r | |
| 30 | @retval FALSE No, it isn't.\r | |
| 31 | **/\r | |
| 32 | #define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
| 33 | (DisplayFamily == 0x06 && \\r | |
| 34 | ( \\r | |
| 8836448b HW |
35 | DisplayModel == 0x3A || \\r |
| 36 | DisplayModel == 0x3E \\r | |
| f4c982bf JF |
37 | ) \\r |
| 38 | )\r | |
| 39 | \r | |
| 84ada87c MK |
40 | /**\r |
| 41 | Package. See http://biosbits.org.\r | |
| 42 | \r | |
| 43 | @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)\r | |
| 44 | @param EAX Lower 32-bits of MSR value.\r | |
| 45 | Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.\r | |
| 46 | @param EDX Upper 32-bits of MSR value.\r | |
| 47 | Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.\r | |
| 48 | \r | |
| 49 | <b>Example usage</b>\r | |
| 50 | @code\r | |
| 51 | MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Msr;\r | |
| 52 | \r | |
| 53 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);\r | |
| 54 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);\r | |
| 55 | @endcode\r | |
| fed6c37b | 56 | @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r |
| 84ada87c MK |
57 | **/\r |
| 58 | #define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE\r | |
| 59 | \r | |
| 60 | /**\r | |
| 61 | MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO\r | |
| 62 | **/\r | |
| 63 | typedef union {\r | |
| 64 | ///\r | |
| 65 | /// Individual bit fields\r | |
| 66 | ///\r | |
| 67 | struct {\r | |
| 68 | UINT32 Reserved1:8;\r | |
| 69 | ///\r | |
| 70 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r | |
| 71 | /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r | |
| 72 | /// MHz.\r | |
| 73 | ///\r | |
| 74 | UINT32 MaximumNonTurboRatio:8;\r | |
| 75 | UINT32 Reserved2:12;\r | |
| 76 | ///\r | |
| 77 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r | |
| 78 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r | |
| 79 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r | |
| 80 | /// Turbo mode is disabled.\r | |
| 81 | ///\r | |
| 82 | UINT32 RatioLimit:1;\r | |
| 83 | ///\r | |
| 84 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r | |
| 85 | /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r | |
| 86 | /// and when set to 0, indicates TDP Limit for Turbo mode is not\r | |
| 87 | /// programmable.\r | |
| 88 | ///\r | |
| 89 | UINT32 TDPLimit:1;\r | |
| 90 | UINT32 Reserved3:2;\r | |
| 91 | ///\r | |
| 92 | /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r | |
| 93 | /// indicates that LPM is supported, and when set to 0, indicates LPM is\r | |
| 94 | /// not supported.\r | |
| 95 | ///\r | |
| 96 | UINT32 LowPowerModeSupport:1;\r | |
| 97 | ///\r | |
| 98 | /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r | |
| 99 | /// TDP level available. 01: One additional TDP level available. 02: Two\r | |
| 100 | /// additional TDP level available. 11: Reserved.\r | |
| 101 | ///\r | |
| 102 | UINT32 ConfigTDPLevels:2;\r | |
| 103 | UINT32 Reserved4:5;\r | |
| 104 | ///\r | |
| 105 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r | |
| 106 | /// minimum ratio (maximum efficiency) that the processor can operates, in\r | |
| 107 | /// units of 100MHz.\r | |
| 108 | ///\r | |
| 109 | UINT32 MaximumEfficiencyRatio:8;\r | |
| 110 | ///\r | |
| 111 | /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r | |
| 112 | /// minimum supported operating ratio in units of 100 MHz.\r | |
| 113 | ///\r | |
| 114 | UINT32 MinimumOperatingRatio:8;\r | |
| 115 | UINT32 Reserved5:8;\r | |
| 116 | } Bits;\r | |
| 117 | ///\r | |
| 118 | /// All bit fields as a 64-bit value\r | |
| 119 | ///\r | |
| 120 | UINT64 Uint64;\r | |
| 121 | } MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;\r | |
| 122 | \r | |
| 123 | \r | |
| 124 | /**\r | |
| 125 | Core. C-State Configuration Control (R/W) Note: C-state values are\r | |
| 126 | processor specific C-state code names, unrelated to MWAIT extension C-state\r | |
| 127 | parameters or ACPI C-States. See http://biosbits.org.\r | |
| 128 | \r | |
| 129 | @param ECX MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
| 130 | @param EAX Lower 32-bits of MSR value.\r | |
| 131 | Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 132 | @param EDX Upper 32-bits of MSR value.\r | |
| 133 | Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 134 | \r | |
| 135 | <b>Example usage</b>\r | |
| 136 | @code\r | |
| 137 | MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
| 138 | \r | |
| 139 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);\r | |
| 140 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
| 141 | @endcode\r | |
| fed6c37b | 142 | @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r |
| 84ada87c MK |
143 | **/\r |
| 144 | #define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
| 145 | \r | |
| 146 | /**\r | |
| 147 | MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL\r | |
| 148 | **/\r | |
| 149 | typedef union {\r | |
| 150 | ///\r | |
| 151 | /// Individual bit fields\r | |
| 152 | ///\r | |
| 153 | struct {\r | |
| 154 | ///\r | |
| 155 | /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r | |
| 156 | /// processor-specific C-state code name (consuming the least power). for\r | |
| 157 | /// the package. The default is set as factory-configured package C-state\r | |
| 158 | /// limit. The following C-state code name encodings are supported: 000b:\r | |
| 159 | /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:\r | |
| 160 | /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r | |
| 161 | /// This field cannot be used to limit package C-state to C3.\r | |
| 162 | ///\r | |
| 163 | UINT32 Limit:3;\r | |
| 164 | UINT32 Reserved1:7;\r | |
| 165 | ///\r | |
| 166 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r | |
| 167 | /// IO_read instructions sent to IO register specified by\r | |
| 168 | /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r | |
| 169 | ///\r | |
| 170 | UINT32 IO_MWAIT:1;\r | |
| 171 | UINT32 Reserved2:4;\r | |
| 172 | ///\r | |
| 173 | /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r | |
| 174 | /// until next reset.\r | |
| 175 | ///\r | |
| 176 | UINT32 CFGLock:1;\r | |
| 177 | UINT32 Reserved3:9;\r | |
| 178 | ///\r | |
| 179 | /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r | |
| 180 | /// will conditionally demote C6/C7 requests to C3 based on uncore\r | |
| 181 | /// auto-demote information.\r | |
| 182 | ///\r | |
| 183 | UINT32 C3AutoDemotion:1;\r | |
| 184 | ///\r | |
| 185 | /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r | |
| 186 | /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r | |
| 187 | /// auto-demote information.\r | |
| 188 | ///\r | |
| 189 | UINT32 C1AutoDemotion:1;\r | |
| 190 | ///\r | |
| 191 | /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r | |
| 192 | /// demoted C3.\r | |
| 193 | ///\r | |
| 194 | UINT32 C3Undemotion:1;\r | |
| 195 | ///\r | |
| 196 | /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r | |
| 197 | /// demoted C1.\r | |
| 198 | ///\r | |
| 199 | UINT32 C1Undemotion:1;\r | |
| 200 | UINT32 Reserved4:3;\r | |
| 201 | UINT32 Reserved5:32;\r | |
| 202 | } Bits;\r | |
| 203 | ///\r | |
| 204 | /// All bit fields as a 32-bit value\r | |
| 205 | ///\r | |
| 206 | UINT32 Uint32;\r | |
| 207 | ///\r | |
| 208 | /// All bit fields as a 64-bit value\r | |
| 209 | ///\r | |
| 210 | UINT64 Uint64;\r | |
| 211 | } MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
| 212 | \r | |
| 213 | \r | |
| 0f16be6d HW |
214 | /**\r |
| 215 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
| 216 | Domains.".\r | |
| 217 | \r | |
| 218 | @param ECX MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)\r | |
| 219 | @param EAX Lower 32-bits of MSR value.\r | |
| 220 | @param EDX Upper 32-bits of MSR value.\r | |
| 221 | \r | |
| 222 | <b>Example usage</b>\r | |
| 223 | @code\r | |
| 224 | UINT64 Msr;\r | |
| 225 | \r | |
| 226 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS);\r | |
| 227 | @endcode\r | |
| 228 | @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r | |
| 229 | **/\r | |
| 230 | #define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r | |
| 231 | \r | |
| 232 | \r | |
| 84ada87c MK |
233 | /**\r |
| 234 | Package. Base TDP Ratio (R/O).\r | |
| 235 | \r | |
| 236 | @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)\r | |
| 237 | @param EAX Lower 32-bits of MSR value.\r | |
| 238 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.\r | |
| 239 | @param EDX Upper 32-bits of MSR value.\r | |
| 240 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.\r | |
| 241 | \r | |
| 242 | <b>Example usage</b>\r | |
| 243 | @code\r | |
| 244 | MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Msr;\r | |
| 245 | \r | |
| 246 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);\r | |
| 247 | @endcode\r | |
| fed6c37b | 248 | @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r |
| 84ada87c MK |
249 | **/\r |
| 250 | #define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648\r | |
| 251 | \r | |
| 252 | /**\r | |
| 253 | MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL\r | |
| 254 | **/\r | |
| 255 | typedef union {\r | |
| 256 | ///\r | |
| 257 | /// Individual bit fields\r | |
| 258 | ///\r | |
| 259 | struct {\r | |
| 260 | ///\r | |
| 261 | /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r | |
| 262 | /// specific processor (in units of 100 MHz).\r | |
| 263 | ///\r | |
| 264 | UINT32 Config_TDP_Base:8;\r | |
| 265 | UINT32 Reserved1:24;\r | |
| 266 | UINT32 Reserved2:32;\r | |
| 267 | } Bits;\r | |
| 268 | ///\r | |
| 269 | /// All bit fields as a 32-bit value\r | |
| 270 | ///\r | |
| 271 | UINT32 Uint32;\r | |
| 272 | ///\r | |
| 273 | /// All bit fields as a 64-bit value\r | |
| 274 | ///\r | |
| 275 | UINT64 Uint64;\r | |
| 276 | } MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;\r | |
| 277 | \r | |
| 278 | \r | |
| 279 | /**\r | |
| 280 | Package. ConfigTDP Level 1 ratio and power level (R/O).\r | |
| 281 | \r | |
| 282 | @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)\r | |
| 283 | @param EAX Lower 32-bits of MSR value.\r | |
| 284 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.\r | |
| 285 | @param EDX Upper 32-bits of MSR value.\r | |
| 286 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.\r | |
| 287 | \r | |
| 288 | <b>Example usage</b>\r | |
| 289 | @code\r | |
| 290 | MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Msr;\r | |
| 291 | \r | |
| 292 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);\r | |
| 293 | @endcode\r | |
| fed6c37b | 294 | @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r |
| 84ada87c MK |
295 | **/\r |
| 296 | #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649\r | |
| 297 | \r | |
| 298 | /**\r | |
| 299 | MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1\r | |
| 300 | **/\r | |
| 301 | typedef union {\r | |
| 302 | ///\r | |
| 303 | /// Individual bit fields\r | |
| 304 | ///\r | |
| 305 | struct {\r | |
| 306 | ///\r | |
| 307 | /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r | |
| 308 | ///\r | |
| 309 | UINT32 PKG_TDP_LVL1:15;\r | |
| 310 | UINT32 Reserved1:1;\r | |
| 311 | ///\r | |
| 312 | /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r | |
| 313 | /// for this specific processor.\r | |
| 314 | ///\r | |
| 315 | UINT32 Config_TDP_LVL1_Ratio:8;\r | |
| 316 | UINT32 Reserved2:8;\r | |
| 317 | ///\r | |
| 318 | /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r | |
| 319 | /// Level 1.\r | |
| 320 | ///\r | |
| 321 | UINT32 PKG_MAX_PWR_LVL1:15;\r | |
| 322 | UINT32 Reserved3:1;\r | |
| 323 | ///\r | |
| 324 | /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r | |
| 325 | /// Level 1.\r | |
| 326 | ///\r | |
| 327 | UINT32 PKG_MIN_PWR_LVL1:15;\r | |
| 328 | UINT32 Reserved4:1;\r | |
| 329 | } Bits;\r | |
| 330 | ///\r | |
| 331 | /// All bit fields as a 64-bit value\r | |
| 332 | ///\r | |
| 333 | UINT64 Uint64;\r | |
| 334 | } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;\r | |
| 335 | \r | |
| 336 | \r | |
| 337 | /**\r | |
| 338 | Package. ConfigTDP Level 2 ratio and power level (R/O).\r | |
| 339 | \r | |
| 340 | @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)\r | |
| 341 | @param EAX Lower 32-bits of MSR value.\r | |
| 342 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.\r | |
| 343 | @param EDX Upper 32-bits of MSR value.\r | |
| 344 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.\r | |
| 345 | \r | |
| 346 | <b>Example usage</b>\r | |
| 347 | @code\r | |
| 348 | MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Msr;\r | |
| 349 | \r | |
| 350 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);\r | |
| 351 | @endcode\r | |
| fed6c37b | 352 | @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r |
| 84ada87c MK |
353 | **/\r |
| 354 | #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A\r | |
| 355 | \r | |
| 356 | /**\r | |
| 357 | MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2\r | |
| 358 | **/\r | |
| 359 | typedef union {\r | |
| 360 | ///\r | |
| 361 | /// Individual bit fields\r | |
| 362 | ///\r | |
| 363 | struct {\r | |
| 364 | ///\r | |
| 365 | /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r | |
| 366 | ///\r | |
| 367 | UINT32 PKG_TDP_LVL2:15;\r | |
| 368 | UINT32 Reserved1:1;\r | |
| 369 | ///\r | |
| 370 | /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r | |
| 371 | /// for this specific processor.\r | |
| 372 | ///\r | |
| 373 | UINT32 Config_TDP_LVL2_Ratio:8;\r | |
| 374 | UINT32 Reserved2:8;\r | |
| 375 | ///\r | |
| 376 | /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r | |
| 377 | /// Level 2.\r | |
| 378 | ///\r | |
| 379 | UINT32 PKG_MAX_PWR_LVL2:15;\r | |
| 380 | UINT32 Reserved3:1;\r | |
| 381 | ///\r | |
| 382 | /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r | |
| 383 | /// Level 2.\r | |
| 384 | ///\r | |
| 385 | UINT32 PKG_MIN_PWR_LVL2:15;\r | |
| 386 | UINT32 Reserved4:1;\r | |
| 387 | } Bits;\r | |
| 388 | ///\r | |
| 389 | /// All bit fields as a 64-bit value\r | |
| 390 | ///\r | |
| 391 | UINT64 Uint64;\r | |
| 392 | } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;\r | |
| 393 | \r | |
| 394 | \r | |
| 395 | /**\r | |
| 396 | Package. ConfigTDP Control (R/W).\r | |
| 397 | \r | |
| 398 | @param ECX MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)\r | |
| 399 | @param EAX Lower 32-bits of MSR value.\r | |
| 400 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.\r | |
| 401 | @param EDX Upper 32-bits of MSR value.\r | |
| 402 | Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.\r | |
| 403 | \r | |
| 404 | <b>Example usage</b>\r | |
| 405 | @code\r | |
| 406 | MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Msr;\r | |
| 407 | \r | |
| 408 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);\r | |
| 409 | AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);\r | |
| 410 | @endcode\r | |
| fed6c37b | 411 | @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r |
| 84ada87c MK |
412 | **/\r |
| 413 | #define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B\r | |
| 414 | \r | |
| 415 | /**\r | |
| 416 | MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL\r | |
| 417 | **/\r | |
| 418 | typedef union {\r | |
| 419 | ///\r | |
| 420 | /// Individual bit fields\r | |
| 421 | ///\r | |
| 422 | struct {\r | |
| 423 | ///\r | |
| 424 | /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r | |
| 425 | ///\r | |
| 426 | UINT32 TDP_LEVEL:2;\r | |
| 427 | UINT32 Reserved1:29;\r | |
| 428 | ///\r | |
| 429 | /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r | |
| 430 | /// this register is locked until a reset.\r | |
| 431 | ///\r | |
| 432 | UINT32 Config_TDP_Lock:1;\r | |
| 433 | UINT32 Reserved2:32;\r | |
| 434 | } Bits;\r | |
| 435 | ///\r | |
| 436 | /// All bit fields as a 32-bit value\r | |
| 437 | ///\r | |
| 438 | UINT32 Uint32;\r | |
| 439 | ///\r | |
| 440 | /// All bit fields as a 64-bit value\r | |
| 441 | ///\r | |
| 442 | UINT64 Uint64;\r | |
| 443 | } MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;\r | |
| 444 | \r | |
| 445 | \r | |
| 446 | /**\r | |
| 447 | Package. ConfigTDP Control (R/W).\r | |
| 448 | \r | |
| 449 | @param ECX MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)\r | |
| 450 | @param EAX Lower 32-bits of MSR value.\r | |
| 451 | Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.\r | |
| 452 | @param EDX Upper 32-bits of MSR value.\r | |
| 453 | Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.\r | |
| 454 | \r | |
| 455 | <b>Example usage</b>\r | |
| 456 | @code\r | |
| 457 | MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r | |
| 458 | \r | |
| 459 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);\r | |
| 460 | AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r | |
| 461 | @endcode\r | |
| fed6c37b | 462 | @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r |
| 84ada87c MK |
463 | **/\r |
| 464 | #define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C\r | |
| 465 | \r | |
| 466 | /**\r | |
| 467 | MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO\r | |
| 468 | **/\r | |
| 469 | typedef union {\r | |
| 470 | ///\r | |
| 471 | /// Individual bit fields\r | |
| 472 | ///\r | |
| 473 | struct {\r | |
| 474 | ///\r | |
| 475 | /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r | |
| 476 | /// field.\r | |
| 477 | ///\r | |
| 478 | UINT32 MAX_NON_TURBO_RATIO:8;\r | |
| 479 | UINT32 Reserved1:23;\r | |
| 480 | ///\r | |
| 481 | /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r | |
| 482 | /// content of this register is locked until a reset.\r | |
| 483 | ///\r | |
| 484 | UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r | |
| 485 | UINT32 Reserved2:32;\r | |
| 486 | } Bits;\r | |
| 487 | ///\r | |
| 488 | /// All bit fields as a 32-bit value\r | |
| 489 | ///\r | |
| 490 | UINT32 Uint32;\r | |
| 491 | ///\r | |
| 492 | /// All bit fields as a 64-bit value\r | |
| 493 | ///\r | |
| 494 | UINT64 Uint64;\r | |
| 495 | } MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;\r | |
| 496 | \r | |
| 497 | \r | |
| 498 | /**\r | |
| 499 | Package. Protected Processor Inventory Number Enable Control (R/W).\r | |
| 500 | \r | |
| 501 | @param ECX MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)\r | |
| 502 | @param EAX Lower 32-bits of MSR value.\r | |
| 503 | Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.\r | |
| 504 | @param EDX Upper 32-bits of MSR value.\r | |
| 505 | Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.\r | |
| 506 | \r | |
| 507 | <b>Example usage</b>\r | |
| 508 | @code\r | |
| 509 | MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Msr;\r | |
| 510 | \r | |
| 511 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r | |
| 512 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);\r | |
| 513 | @endcode\r | |
| fed6c37b | 514 | @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r |
| 84ada87c MK |
515 | **/\r |
| 516 | #define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E\r | |
| 517 | \r | |
| 518 | /**\r | |
| 519 | MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL\r | |
| 520 | **/\r | |
| 521 | typedef union {\r | |
| 522 | ///\r | |
| 523 | /// Individual bit fields\r | |
| 524 | ///\r | |
| 525 | struct {\r | |
| 526 | ///\r | |
| 527 | /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.\r | |
| 528 | /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit\r | |
| 529 | /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to\r | |
| 530 | /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged\r | |
| 531 | /// inventory initialization agent to access MSR_PPIN. After reading\r | |
| 532 | /// MSR_PPIN, the privileged inventory initialization agent should write\r | |
| 533 | /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r | |
| 534 | /// prevent unauthorized modification to MSR_PPIN_CTL.\r | |
| 535 | ///\r | |
| 536 | UINT32 LockOut:1;\r | |
| 537 | ///\r | |
| 538 | /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r | |
| 539 | /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will\r | |
| 540 | /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default\r | |
| 541 | /// is 0.\r | |
| 542 | ///\r | |
| 543 | UINT32 Enable_PPIN:1;\r | |
| 544 | UINT32 Reserved1:30;\r | |
| 545 | UINT32 Reserved2:32;\r | |
| 546 | } Bits;\r | |
| 547 | ///\r | |
| 548 | /// All bit fields as a 32-bit value\r | |
| 549 | ///\r | |
| 550 | UINT32 Uint32;\r | |
| 551 | ///\r | |
| 552 | /// All bit fields as a 64-bit value\r | |
| 553 | ///\r | |
| 554 | UINT64 Uint64;\r | |
| 555 | } MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;\r | |
| 556 | \r | |
| 557 | \r | |
| 558 | /**\r | |
| 559 | Package. Protected Processor Inventory Number (R/O). Protected Processor\r | |
| 560 | Inventory Number (R/O) A unique value within a given CPUID\r | |
| 561 | family/model/stepping signature that a privileged inventory initialization\r | |
| 562 | agent can access to identify each physical processor, when access to\r | |
| 563 | MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if\r | |
| 564 | MSR_PPIN_CTL[bits 1:0] = '10b'.\r | |
| 565 | \r | |
| 566 | @param ECX MSR_IVY_BRIDGE_PPIN (0x0000004F)\r | |
| 567 | @param EAX Lower 32-bits of MSR value.\r | |
| 568 | @param EDX Upper 32-bits of MSR value.\r | |
| 569 | \r | |
| 570 | <b>Example usage</b>\r | |
| 571 | @code\r | |
| 572 | UINT64 Msr;\r | |
| 573 | \r | |
| 574 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);\r | |
| 575 | @endcode\r | |
| fed6c37b | 576 | @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.\r |
| 84ada87c MK |
577 | **/\r |
| 578 | #define MSR_IVY_BRIDGE_PPIN 0x0000004F\r | |
| 579 | \r | |
| 580 | \r | |
| 581 | /**\r | |
| 582 | Package. See http://biosbits.org.\r | |
| 583 | \r | |
| 584 | @param ECX MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)\r | |
| 585 | @param EAX Lower 32-bits of MSR value.\r | |
| 586 | Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.\r | |
| 587 | @param EDX Upper 32-bits of MSR value.\r | |
| 588 | Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.\r | |
| 589 | \r | |
| 590 | <b>Example usage</b>\r | |
| 591 | @code\r | |
| 592 | MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Msr;\r | |
| 593 | \r | |
| 594 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r | |
| 595 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);\r | |
| 596 | @endcode\r | |
| fed6c37b | 597 | @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.\r |
| 84ada87c MK |
598 | **/\r |
| 599 | #define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE\r | |
| 600 | \r | |
| 601 | /**\r | |
| 602 | MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1\r | |
| 603 | **/\r | |
| 604 | typedef union {\r | |
| 605 | ///\r | |
| 606 | /// Individual bit fields\r | |
| 607 | ///\r | |
| 608 | struct {\r | |
| 609 | UINT32 Reserved1:8;\r | |
| 610 | ///\r | |
| 611 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r | |
| 612 | /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r | |
| 613 | /// MHz.\r | |
| 614 | ///\r | |
| 615 | UINT32 MaximumNonTurboRatio:8;\r | |
| 616 | UINT32 Reserved2:7;\r | |
| 617 | ///\r | |
| 618 | /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that\r | |
| 619 | /// Protected Processor Inventory Number (PPIN) capability can be enabled\r | |
| 620 | /// for privileged system inventory agent to read PPIN from MSR_PPIN. When\r | |
| 621 | /// set to 0, PPIN capability is not supported. An attempt to access\r | |
| 622 | /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.\r | |
| 623 | ///\r | |
| 624 | UINT32 PPIN_CAP:1;\r | |
| 625 | UINT32 Reserved3:4;\r | |
| 626 | ///\r | |
| 627 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r | |
| 628 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r | |
| 629 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r | |
| 630 | /// Turbo mode is disabled.\r | |
| 631 | ///\r | |
| 632 | UINT32 RatioLimit:1;\r | |
| 633 | ///\r | |
| 634 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r | |
| 635 | /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r | |
| 636 | /// and when set to 0, indicates TDP Limit for Turbo mode is not\r | |
| 637 | /// programmable.\r | |
| 638 | ///\r | |
| 639 | UINT32 TDPLimit:1;\r | |
| 640 | ///\r | |
| 641 | /// [Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1,\r | |
| 642 | /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to\r | |
| 643 | /// specify an temperature offset.\r | |
| 644 | ///\r | |
| 645 | UINT32 TJOFFSET:1;\r | |
| 646 | UINT32 Reserved4:1;\r | |
| 647 | UINT32 Reserved5:8;\r | |
| 648 | ///\r | |
| 649 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r | |
| 650 | /// minimum ratio (maximum efficiency) that the processor can operates, in\r | |
| 651 | /// units of 100MHz.\r | |
| 652 | ///\r | |
| 653 | UINT32 MaximumEfficiencyRatio:8;\r | |
| 654 | UINT32 Reserved6:16;\r | |
| 655 | } Bits;\r | |
| 656 | ///\r | |
| 657 | /// All bit fields as a 64-bit value\r | |
| 658 | ///\r | |
| 659 | UINT64 Uint64;\r | |
| 660 | } MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;\r | |
| 661 | \r | |
| 662 | \r | |
| 663 | /**\r | |
| 664 | Package. MC Bank Error Configuration (R/W).\r | |
| 665 | \r | |
| 666 | @param ECX MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)\r | |
| 667 | @param EAX Lower 32-bits of MSR value.\r | |
| 668 | Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.\r | |
| 669 | @param EDX Upper 32-bits of MSR value.\r | |
| 670 | Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.\r | |
| 671 | \r | |
| 672 | <b>Example usage</b>\r | |
| 673 | @code\r | |
| 674 | MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Msr;\r | |
| 675 | \r | |
| 676 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);\r | |
| 677 | AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);\r | |
| 678 | @endcode\r | |
| fed6c37b | 679 | @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r |
| 84ada87c MK |
680 | **/\r |
| 681 | #define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F\r | |
| 682 | \r | |
| 683 | /**\r | |
| 684 | MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL\r | |
| 685 | **/\r | |
| 686 | typedef union {\r | |
| 687 | ///\r | |
| 688 | /// Individual bit fields\r | |
| 689 | ///\r | |
| 690 | struct {\r | |
| 691 | UINT32 Reserved1:1;\r | |
| 692 | ///\r | |
| 693 | /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r | |
| 694 | /// to log additional info in bits 36:32.\r | |
| 695 | ///\r | |
| 696 | UINT32 MemErrorLogEnable:1;\r | |
| 697 | UINT32 Reserved2:30;\r | |
| 698 | UINT32 Reserved3:32;\r | |
| 699 | } Bits;\r | |
| 700 | ///\r | |
| 701 | /// All bit fields as a 32-bit value\r | |
| 702 | ///\r | |
| 703 | UINT32 Uint32;\r | |
| 704 | ///\r | |
| 705 | /// All bit fields as a 64-bit value\r | |
| 706 | ///\r | |
| 707 | UINT64 Uint64;\r | |
| 708 | } MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;\r | |
| 709 | \r | |
| 710 | \r | |
| 711 | /**\r | |
| 712 | Package.\r | |
| 713 | \r | |
| 714 | @param ECX MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)\r | |
| 715 | @param EAX Lower 32-bits of MSR value.\r | |
| 716 | Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r | |
| 717 | @param EDX Upper 32-bits of MSR value.\r | |
| 718 | Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r | |
| 719 | \r | |
| 720 | <b>Example usage</b>\r | |
| 721 | @code\r | |
| 722 | MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;\r | |
| 723 | \r | |
| 724 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);\r | |
| 725 | AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);\r | |
| 726 | @endcode\r | |
| fed6c37b | 727 | @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r |
| 84ada87c MK |
728 | **/\r |
| 729 | #define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r | |
| 730 | \r | |
| 731 | /**\r | |
| 732 | MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET\r | |
| 733 | **/\r | |
| 734 | typedef union {\r | |
| 735 | ///\r | |
| 736 | /// Individual bit fields\r | |
| 737 | ///\r | |
| 738 | struct {\r | |
| 739 | UINT32 Reserved1:16;\r | |
| 740 | ///\r | |
| 741 | /// [Bits 23:16] Temperature Target (RO) The minimum temperature at which\r | |
| 742 | /// PROCHOT# will be asserted. The value is degree C.\r | |
| 743 | ///\r | |
| 744 | UINT32 TemperatureTarget:8;\r | |
| 745 | ///\r | |
| 746 | /// [Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature\r | |
| 747 | /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#\r | |
| 748 | /// will assert at the offset target temperature. Write is permitted only\r | |
| 749 | /// MSR_PLATFORM_INFO.[30] is set.\r | |
| 750 | ///\r | |
| 751 | UINT32 TCCActivationOffset:4;\r | |
| 752 | UINT32 Reserved2:4;\r | |
| 753 | UINT32 Reserved3:32;\r | |
| 754 | } Bits;\r | |
| 755 | ///\r | |
| 756 | /// All bit fields as a 32-bit value\r | |
| 757 | ///\r | |
| 758 | UINT32 Uint32;\r | |
| 759 | ///\r | |
| 760 | /// All bit fields as a 64-bit value\r | |
| 761 | ///\r | |
| 762 | UINT64 Uint64;\r | |
| 763 | } MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r | |
| 764 | \r | |
| 765 | \r | |
| 766 | /**\r | |
| 767 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
| 768 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
| 769 | \r | |
| 770 | @param ECX MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)\r | |
| 771 | @param EAX Lower 32-bits of MSR value.\r | |
| 772 | Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.\r | |
| 773 | @param EDX Upper 32-bits of MSR value.\r | |
| 774 | Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.\r | |
| 775 | \r | |
| 776 | <b>Example usage</b>\r | |
| 777 | @code\r | |
| 778 | MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Msr;\r | |
| 779 | \r | |
| 780 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);\r | |
| 781 | @endcode\r | |
| fed6c37b | 782 | @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r |
| 84ada87c MK |
783 | **/\r |
| 784 | #define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE\r | |
| 785 | \r | |
| 786 | /**\r | |
| 787 | MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1\r | |
| 788 | **/\r | |
| 789 | typedef union {\r | |
| 790 | ///\r | |
| 791 | /// Individual bit fields\r | |
| 792 | ///\r | |
| 793 | struct {\r | |
| 794 | ///\r | |
| 795 | /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio\r | |
| 796 | /// limit of 9 core active.\r | |
| 797 | ///\r | |
| 798 | UINT32 Maximum9C:8;\r | |
| 799 | ///\r | |
| 800 | /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio\r | |
| 801 | /// limit of 10core active.\r | |
| 802 | ///\r | |
| 803 | UINT32 Maximum10C:8;\r | |
| 804 | ///\r | |
| 805 | /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio\r | |
| 806 | /// limit of 11 core active.\r | |
| 807 | ///\r | |
| 808 | UINT32 Maximum11C:8;\r | |
| 809 | ///\r | |
| 810 | /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio\r | |
| 811 | /// limit of 12 core active.\r | |
| 812 | ///\r | |
| 813 | UINT32 Maximum12C:8;\r | |
| 814 | ///\r | |
| 815 | /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio\r | |
| 816 | /// limit of 13 core active.\r | |
| 817 | ///\r | |
| 818 | UINT32 Maximum13C:8;\r | |
| 819 | ///\r | |
| 820 | /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio\r | |
| 821 | /// limit of 14 core active.\r | |
| 822 | ///\r | |
| 823 | UINT32 Maximum14C:8;\r | |
| 824 | ///\r | |
| 825 | /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio\r | |
| 826 | /// limit of 15 core active.\r | |
| 827 | ///\r | |
| 828 | UINT32 Maximum15C:8;\r | |
| 829 | UINT32 Reserved:7;\r | |
| 830 | ///\r | |
| 831 | /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r | |
| 832 | /// the processor uses override configuration specified in\r | |
| 833 | /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r | |
| 834 | /// uses factory-set configuration (Default).\r | |
| 835 | ///\r | |
| 836 | UINT32 TurboRatioLimitConfigurationSemaphore:1;\r | |
| 837 | } Bits;\r | |
| 838 | ///\r | |
| 839 | /// All bit fields as a 64-bit value\r | |
| 840 | ///\r | |
| 841 | UINT64 Uint64;\r | |
| 842 | } MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;\r | |
| 843 | \r | |
| 844 | \r | |
| 845 | /**\r | |
| 0f16be6d | 846 | Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.\r |
| 84ada87c | 847 | \r |
| 0f16be6d | 848 | @param ECX MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)\r |
| 84ada87c | 849 | @param EAX Lower 32-bits of MSR value.\r |
| 0f16be6d | 850 | Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r |
| 84ada87c | 851 | @param EDX Upper 32-bits of MSR value.\r |
| 0f16be6d | 852 | Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.\r |
| 84ada87c MK |
853 | \r |
| 854 | <b>Example usage</b>\r | |
| 855 | @code\r | |
| 0f16be6d | 856 | MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Msr;\r |
| 84ada87c | 857 | \r |
| 0f16be6d | 858 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);\r |
| 84ada87c | 859 | @endcode\r |
| 0f16be6d | 860 | @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r |
| 84ada87c | 861 | **/\r |
| 0f16be6d HW |
862 | #define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B\r |
| 863 | \r | |
| 864 | /**\r | |
| 865 | MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC\r | |
| 866 | **/\r | |
| 867 | typedef union {\r | |
| 868 | ///\r | |
| 869 | /// Individual bit fields\r | |
| 870 | ///\r | |
| 871 | struct {\r | |
| 872 | ///\r | |
| 873 | /// [Bits 5:0] Recoverable Address LSB.\r | |
| 874 | ///\r | |
| 875 | UINT32 RecoverableAddressLSB:6;\r | |
| 876 | ///\r | |
| 877 | /// [Bits 8:6] Address Mode.\r | |
| 878 | ///\r | |
| 879 | UINT32 AddressMode:3;\r | |
| 880 | UINT32 Reserved1:7;\r | |
| 881 | ///\r | |
| 882 | /// [Bits 31:16] PCI Express Requestor ID.\r | |
| 883 | ///\r | |
| 884 | UINT32 PCIExpressRequestorID:16;\r | |
| 885 | ///\r | |
| 886 | /// [Bits 39:32] PCI Express Segment Number.\r | |
| 887 | ///\r | |
| 888 | UINT32 PCIExpressSegmentNumber:8;\r | |
| 889 | UINT32 Reserved2:24;\r | |
| 890 | } Bits;\r | |
| 891 | ///\r | |
| 892 | /// All bit fields as a 64-bit value\r | |
| 893 | ///\r | |
| 894 | UINT64 Uint64;\r | |
| 895 | } MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;\r | |
| 84ada87c MK |
896 | \r |
| 897 | \r | |
| 898 | /**\r | |
| 899 | Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r | |
| 900 | 15.3.2.4, "IA32_MCi_MISC MSRs.".\r | |
| 901 | \r | |
| 0f16be6d HW |
902 | Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r |
| 903 | and its corresponding slice of L3.\r | |
| 84ada87c | 904 | \r |
| 0f16be6d | 905 | @param ECX MSR_IVY_BRIDGE_IA32_MCi_CTL\r |
| 84ada87c MK |
906 | @param EAX Lower 32-bits of MSR value.\r |
| 907 | @param EDX Upper 32-bits of MSR value.\r | |
| 908 | \r | |
| 909 | <b>Example usage</b>\r | |
| 910 | @code\r | |
| 911 | UINT64 Msr;\r | |
| 912 | \r | |
| 0f16be6d HW |
913 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);\r |
| 914 | AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);\r | |
| 84ada87c | 915 | @endcode\r |
| 0f16be6d HW |
916 | @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM.\r |
| 917 | MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM.\r | |
| 918 | MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.\r | |
| 84ada87c MK |
919 | @{\r |
| 920 | **/\r | |
| 0f16be6d HW |
921 | #define MSR_IVY_BRIDGE_IA32_MC29_CTL 0x00000474\r |
| 922 | #define MSR_IVY_BRIDGE_IA32_MC30_CTL 0x00000478\r | |
| 923 | #define MSR_IVY_BRIDGE_IA32_MC31_CTL 0x0000047C\r | |
| 84ada87c MK |
924 | /// @}\r |
| 925 | \r | |
| 926 | \r | |
| 927 | /**\r | |
| 928 | Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r | |
| 929 | 15.3.2.4, "IA32_MCi_MISC MSRs.".\r | |
| 930 | \r | |
| 0f16be6d HW |
931 | Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r |
| 932 | and its corresponding slice of L3.\r | |
| 933 | \r | |
| 934 | @param ECX MSR_IVY_BRIDGE_IA32_MCi_STATUS\r | |
| 84ada87c MK |
935 | @param EAX Lower 32-bits of MSR value.\r |
| 936 | @param EDX Upper 32-bits of MSR value.\r | |
| 937 | \r | |
| 938 | <b>Example usage</b>\r | |
| 939 | @code\r | |
| 940 | UINT64 Msr;\r | |
| 941 | \r | |
| 0f16be6d HW |
942 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);\r |
| 943 | AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);\r | |
| 84ada87c | 944 | @endcode\r |
| 0f16be6d HW |
945 | @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM.\r |
| 946 | MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM.\r | |
| 947 | MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.\r | |
| 84ada87c MK |
948 | @{\r |
| 949 | **/\r | |
| 0f16be6d HW |
950 | #define MSR_IVY_BRIDGE_IA32_MC29_STATUS 0x00000475\r |
| 951 | #define MSR_IVY_BRIDGE_IA32_MC30_STATUS 0x00000479\r | |
| 952 | #define MSR_IVY_BRIDGE_IA32_MC31_STATUS 0x0000047D\r | |
| 84ada87c MK |
953 | /// @}\r |
| 954 | \r | |
| 955 | \r | |
| 956 | /**\r | |
| 957 | Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r | |
| 958 | 15.3.2.4, "IA32_MCi_MISC MSRs.".\r | |
| 959 | \r | |
| 0f16be6d HW |
960 | Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r |
| 961 | and its corresponding slice of L3.\r | |
| 962 | \r | |
| 963 | @param ECX MSR_IVY_BRIDGE_IA32_MCi_ADDR\r | |
| 84ada87c MK |
964 | @param EAX Lower 32-bits of MSR value.\r |
| 965 | @param EDX Upper 32-bits of MSR value.\r | |
| 966 | \r | |
| 967 | <b>Example usage</b>\r | |
| 968 | @code\r | |
| 969 | UINT64 Msr;\r | |
| 970 | \r | |
| 0f16be6d HW |
971 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);\r |
| 972 | AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);\r | |
| 84ada87c | 973 | @endcode\r |
| 0f16be6d HW |
974 | @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM.\r |
| 975 | MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM.\r | |
| 976 | MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.\r | |
| 84ada87c MK |
977 | @{\r |
| 978 | **/\r | |
| 0f16be6d HW |
979 | #define MSR_IVY_BRIDGE_IA32_MC29_ADDR 0x00000476\r |
| 980 | #define MSR_IVY_BRIDGE_IA32_MC30_ADDR 0x0000047A\r | |
| 981 | #define MSR_IVY_BRIDGE_IA32_MC31_ADDR 0x0000047E\r | |
| 84ada87c MK |
982 | /// @}\r |
| 983 | \r | |
| 984 | \r | |
| 985 | /**\r | |
| 0f16be6d HW |
986 | Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r |
| 987 | 15.3.2.4, "IA32_MCi_MISC MSRs.".\r | |
| 84ada87c | 988 | \r |
| 0f16be6d HW |
989 | Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)\r |
| 990 | and its corresponding slice of L3.\r | |
| 991 | \r | |
| 992 | @param ECX MSR_IVY_BRIDGE_IA32_MCi_MISC\r | |
| 84ada87c | 993 | @param EAX Lower 32-bits of MSR value.\r |
| 84ada87c | 994 | @param EDX Upper 32-bits of MSR value.\r |
| 84ada87c MK |
995 | \r |
| 996 | <b>Example usage</b>\r | |
| 997 | @code\r | |
| 0f16be6d | 998 | UINT64 Msr;\r |
| 84ada87c | 999 | \r |
| 0f16be6d HW |
1000 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);\r |
| 1001 | AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);\r | |
| 84ada87c | 1002 | @endcode\r |
| 0f16be6d HW |
1003 | @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM.\r |
| 1004 | MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM.\r | |
| 1005 | MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.\r | |
| 1006 | @{\r | |
| 84ada87c | 1007 | **/\r |
| 0f16be6d HW |
1008 | #define MSR_IVY_BRIDGE_IA32_MC29_MISC 0x00000477\r |
| 1009 | #define MSR_IVY_BRIDGE_IA32_MC30_MISC 0x0000047B\r | |
| 1010 | #define MSR_IVY_BRIDGE_IA32_MC31_MISC 0x0000047F\r | |
| 1011 | /// @}\r | |
| 84ada87c MK |
1012 | \r |
| 1013 | \r | |
| 1014 | /**\r | |
| 1015 | Package. Package RAPL Perf Status (R/O).\r | |
| 1016 | \r | |
| 1017 | @param ECX MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)\r | |
| 1018 | @param EAX Lower 32-bits of MSR value.\r | |
| 1019 | @param EDX Upper 32-bits of MSR value.\r | |
| 1020 | \r | |
| 1021 | <b>Example usage</b>\r | |
| 1022 | @code\r | |
| 1023 | UINT64 Msr;\r | |
| 1024 | \r | |
| 1025 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);\r | |
| 1026 | @endcode\r | |
| fed6c37b | 1027 | @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r |
| 84ada87c MK |
1028 | **/\r |
| 1029 | #define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613\r | |
| 1030 | \r | |
| 1031 | \r | |
| 1032 | /**\r | |
| 1033 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r | |
| 1034 | Domain.".\r | |
| 1035 | \r | |
| 1036 | @param ECX MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)\r | |
| 1037 | @param EAX Lower 32-bits of MSR value.\r | |
| 1038 | @param EDX Upper 32-bits of MSR value.\r | |
| 1039 | \r | |
| 1040 | <b>Example usage</b>\r | |
| 1041 | @code\r | |
| 1042 | UINT64 Msr;\r | |
| 1043 | \r | |
| 1044 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);\r | |
| 1045 | AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);\r | |
| 1046 | @endcode\r | |
| fed6c37b | 1047 | @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r |
| 84ada87c MK |
1048 | **/\r |
| 1049 | #define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r | |
| 1050 | \r | |
| 1051 | \r | |
| 1052 | /**\r | |
| 1053 | Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
| 1054 | \r | |
| 1055 | @param ECX MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)\r | |
| 1056 | @param EAX Lower 32-bits of MSR value.\r | |
| 1057 | @param EDX Upper 32-bits of MSR value.\r | |
| 1058 | \r | |
| 1059 | <b>Example usage</b>\r | |
| 1060 | @code\r | |
| 1061 | UINT64 Msr;\r | |
| 1062 | \r | |
| 1063 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);\r | |
| 1064 | @endcode\r | |
| fed6c37b | 1065 | @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r |
| 84ada87c MK |
1066 | **/\r |
| 1067 | #define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r | |
| 1068 | \r | |
| 1069 | \r | |
| 1070 | /**\r | |
| 1071 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r | |
| 1072 | RAPL Domain.".\r | |
| 1073 | \r | |
| 1074 | @param ECX MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)\r | |
| 1075 | @param EAX Lower 32-bits of MSR value.\r | |
| 1076 | @param EDX Upper 32-bits of MSR value.\r | |
| 1077 | \r | |
| 1078 | <b>Example usage</b>\r | |
| 1079 | @code\r | |
| 1080 | UINT64 Msr;\r | |
| 1081 | \r | |
| 1082 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);\r | |
| 1083 | @endcode\r | |
| fed6c37b | 1084 | @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r |
| 84ada87c MK |
1085 | **/\r |
| 1086 | #define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r | |
| 1087 | \r | |
| 1088 | \r | |
| 1089 | /**\r | |
| 1090 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
| 1091 | \r | |
| 1092 | @param ECX MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)\r | |
| 1093 | @param EAX Lower 32-bits of MSR value.\r | |
| 1094 | @param EDX Upper 32-bits of MSR value.\r | |
| 1095 | \r | |
| 1096 | <b>Example usage</b>\r | |
| 1097 | @code\r | |
| 1098 | UINT64 Msr;\r | |
| 1099 | \r | |
| 1100 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);\r | |
| 1101 | AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);\r | |
| 1102 | @endcode\r | |
| fed6c37b | 1103 | @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r |
| 84ada87c MK |
1104 | **/\r |
| 1105 | #define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r | |
| 1106 | \r | |
| 1107 | \r | |
| 1108 | /**\r | |
| ba1a2d11 | 1109 | Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r |
| 84ada87c MK |
1110 | \r |
| 1111 | @param ECX MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)\r | |
| 1112 | @param EAX Lower 32-bits of MSR value.\r | |
| 1113 | Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.\r | |
| 1114 | @param EDX Upper 32-bits of MSR value.\r | |
| 1115 | Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.\r | |
| 1116 | \r | |
| 1117 | <b>Example usage</b>\r | |
| 1118 | @code\r | |
| 1119 | MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Msr;\r | |
| 1120 | \r | |
| 1121 | Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);\r | |
| 1122 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);\r | |
| 1123 | @endcode\r | |
| fed6c37b | 1124 | @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r |
| 84ada87c MK |
1125 | **/\r |
| 1126 | #define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1\r | |
| 1127 | \r | |
| 1128 | /**\r | |
| 1129 | MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE\r | |
| 1130 | **/\r | |
| 1131 | typedef union {\r | |
| 1132 | ///\r | |
| 1133 | /// Individual bit fields\r | |
| 1134 | ///\r | |
| 1135 | struct {\r | |
| 1136 | ///\r | |
| 1137 | /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r | |
| 1138 | ///\r | |
| 1139 | UINT32 PEBS_EN_PMC0:1;\r | |
| 1140 | ///\r | |
| 1141 | /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r | |
| 1142 | ///\r | |
| 1143 | UINT32 PEBS_EN_PMC1:1;\r | |
| 1144 | ///\r | |
| 1145 | /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r | |
| 1146 | ///\r | |
| 1147 | UINT32 PEBS_EN_PMC2:1;\r | |
| 1148 | ///\r | |
| 1149 | /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r | |
| 1150 | ///\r | |
| 1151 | UINT32 PEBS_EN_PMC3:1;\r | |
| 1152 | UINT32 Reserved1:28;\r | |
| 1153 | ///\r | |
| 1154 | /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r | |
| 1155 | ///\r | |
| 1156 | UINT32 LL_EN_PMC0:1;\r | |
| 1157 | ///\r | |
| 1158 | /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r | |
| 1159 | ///\r | |
| 1160 | UINT32 LL_EN_PMC1:1;\r | |
| 1161 | ///\r | |
| 1162 | /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r | |
| 1163 | ///\r | |
| 1164 | UINT32 LL_EN_PMC2:1;\r | |
| 1165 | ///\r | |
| 1166 | /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r | |
| 1167 | ///\r | |
| 1168 | UINT32 LL_EN_PMC3:1;\r | |
| 1169 | UINT32 Reserved2:28;\r | |
| 1170 | } Bits;\r | |
| 1171 | ///\r | |
| 1172 | /// All bit fields as a 64-bit value\r | |
| 1173 | ///\r | |
| 1174 | UINT64 Uint64;\r | |
| 1175 | } MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;\r | |
| 1176 | \r | |
| 1177 | \r | |
| 1178 | /**\r | |
| 1179 | Package. Uncore perfmon per-socket global control.\r | |
| 1180 | \r | |
| 1181 | @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)\r | |
| 1182 | @param EAX Lower 32-bits of MSR value.\r | |
| 1183 | @param EDX Upper 32-bits of MSR value.\r | |
| 1184 | \r | |
| 1185 | <b>Example usage</b>\r | |
| 1186 | @code\r | |
| 1187 | UINT64 Msr;\r | |
| 1188 | \r | |
| 1189 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);\r | |
| 1190 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);\r | |
| 1191 | @endcode\r | |
| fed6c37b | 1192 | @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r |
| 84ada87c MK |
1193 | **/\r |
| 1194 | #define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00\r | |
| 1195 | \r | |
| 1196 | \r | |
| 1197 | /**\r | |
| 1198 | Package. Uncore perfmon per-socket global status.\r | |
| 1199 | \r | |
| 1200 | @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)\r | |
| 1201 | @param EAX Lower 32-bits of MSR value.\r | |
| 1202 | @param EDX Upper 32-bits of MSR value.\r | |
| 1203 | \r | |
| 1204 | <b>Example usage</b>\r | |
| 1205 | @code\r | |
| 1206 | UINT64 Msr;\r | |
| 1207 | \r | |
| 1208 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);\r | |
| 1209 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);\r | |
| 1210 | @endcode\r | |
| fed6c37b | 1211 | @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r |
| 84ada87c MK |
1212 | **/\r |
| 1213 | #define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01\r | |
| 1214 | \r | |
| 1215 | \r | |
| 1216 | /**\r | |
| 1217 | Package. Uncore perfmon per-socket global configuration.\r | |
| 1218 | \r | |
| 1219 | @param ECX MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)\r | |
| 1220 | @param EAX Lower 32-bits of MSR value.\r | |
| 1221 | @param EDX Upper 32-bits of MSR value.\r | |
| 1222 | \r | |
| 1223 | <b>Example usage</b>\r | |
| 1224 | @code\r | |
| 1225 | UINT64 Msr;\r | |
| 1226 | \r | |
| 1227 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);\r | |
| 1228 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);\r | |
| 1229 | @endcode\r | |
| fed6c37b | 1230 | @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r |
| 84ada87c MK |
1231 | **/\r |
| 1232 | #define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06\r | |
| 1233 | \r | |
| 1234 | \r | |
| 1235 | /**\r | |
| 1236 | Package. Uncore U-box perfmon U-box wide status.\r | |
| 1237 | \r | |
| 1238 | @param ECX MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)\r | |
| 1239 | @param EAX Lower 32-bits of MSR value.\r | |
| 1240 | @param EDX Upper 32-bits of MSR value.\r | |
| 1241 | \r | |
| 1242 | <b>Example usage</b>\r | |
| 1243 | @code\r | |
| 1244 | UINT64 Msr;\r | |
| 1245 | \r | |
| 1246 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);\r | |
| 1247 | AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);\r | |
| 1248 | @endcode\r | |
| fed6c37b | 1249 | @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r |
| 84ada87c MK |
1250 | **/\r |
| 1251 | #define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15\r | |
| 1252 | \r | |
| 1253 | \r | |
| 1254 | /**\r | |
| 1255 | Package. Uncore PCU perfmon box wide status.\r | |
| 1256 | \r | |
| 1257 | @param ECX MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)\r | |
| 1258 | @param EAX Lower 32-bits of MSR value.\r | |
| 1259 | @param EDX Upper 32-bits of MSR value.\r | |
| 1260 | \r | |
| 1261 | <b>Example usage</b>\r | |
| 1262 | @code\r | |
| 1263 | UINT64 Msr;\r | |
| 1264 | \r | |
| 1265 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);\r | |
| 1266 | AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);\r | |
| 1267 | @endcode\r | |
| fed6c37b | 1268 | @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r |
| 84ada87c MK |
1269 | **/\r |
| 1270 | #define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35\r | |
| 1271 | \r | |
| 1272 | \r | |
| 1273 | /**\r | |
| 1274 | Package. Uncore C-box 0 perfmon box wide filter1.\r | |
| 1275 | \r | |
| 1276 | @param ECX MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)\r | |
| 1277 | @param EAX Lower 32-bits of MSR value.\r | |
| 1278 | @param EDX Upper 32-bits of MSR value.\r | |
| 1279 | \r | |
| 1280 | <b>Example usage</b>\r | |
| 1281 | @code\r | |
| 1282 | UINT64 Msr;\r | |
| 1283 | \r | |
| 1284 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);\r | |
| 1285 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);\r | |
| 1286 | @endcode\r | |
| fed6c37b | 1287 | @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1288 | **/\r |
| 1289 | #define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A\r | |
| 1290 | \r | |
| 1291 | \r | |
| 1292 | /**\r | |
| 1293 | Package. Uncore C-box 1 perfmon box wide filter1.\r | |
| 1294 | \r | |
| 1295 | @param ECX MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)\r | |
| 1296 | @param EAX Lower 32-bits of MSR value.\r | |
| 1297 | @param EDX Upper 32-bits of MSR value.\r | |
| 1298 | \r | |
| 1299 | <b>Example usage</b>\r | |
| 1300 | @code\r | |
| 1301 | UINT64 Msr;\r | |
| 1302 | \r | |
| 1303 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);\r | |
| 1304 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);\r | |
| 1305 | @endcode\r | |
| fed6c37b | 1306 | @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1307 | **/\r |
| 1308 | #define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A\r | |
| 1309 | \r | |
| 1310 | \r | |
| 1311 | /**\r | |
| 1312 | Package. Uncore C-box 2 perfmon box wide filter1.\r | |
| 1313 | \r | |
| 1314 | @param ECX MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)\r | |
| 1315 | @param EAX Lower 32-bits of MSR value.\r | |
| 1316 | @param EDX Upper 32-bits of MSR value.\r | |
| 1317 | \r | |
| 1318 | <b>Example usage</b>\r | |
| 1319 | @code\r | |
| 1320 | UINT64 Msr;\r | |
| 1321 | \r | |
| 1322 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);\r | |
| 1323 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);\r | |
| 1324 | @endcode\r | |
| fed6c37b | 1325 | @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1326 | **/\r |
| 1327 | #define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A\r | |
| 1328 | \r | |
| 1329 | \r | |
| 1330 | /**\r | |
| 1331 | Package. Uncore C-box 3 perfmon box wide filter1.\r | |
| 1332 | \r | |
| 1333 | @param ECX MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)\r | |
| 1334 | @param EAX Lower 32-bits of MSR value.\r | |
| 1335 | @param EDX Upper 32-bits of MSR value.\r | |
| 1336 | \r | |
| 1337 | <b>Example usage</b>\r | |
| 1338 | @code\r | |
| 1339 | UINT64 Msr;\r | |
| 1340 | \r | |
| 1341 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);\r | |
| 1342 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);\r | |
| 1343 | @endcode\r | |
| fed6c37b | 1344 | @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1345 | **/\r |
| 1346 | #define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A\r | |
| 1347 | \r | |
| 1348 | \r | |
| 1349 | /**\r | |
| 1350 | Package. Uncore C-box 4 perfmon box wide filter1.\r | |
| 1351 | \r | |
| 1352 | @param ECX MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)\r | |
| 1353 | @param EAX Lower 32-bits of MSR value.\r | |
| 1354 | @param EDX Upper 32-bits of MSR value.\r | |
| 1355 | \r | |
| 1356 | <b>Example usage</b>\r | |
| 1357 | @code\r | |
| 1358 | UINT64 Msr;\r | |
| 1359 | \r | |
| 1360 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);\r | |
| 1361 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);\r | |
| 1362 | @endcode\r | |
| fed6c37b | 1363 | @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1364 | **/\r |
| 1365 | #define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A\r | |
| 1366 | \r | |
| 1367 | \r | |
| 1368 | /**\r | |
| 1369 | Package. Uncore C-box 5 perfmon box wide filter1.\r | |
| 1370 | \r | |
| 1371 | @param ECX MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)\r | |
| 1372 | @param EAX Lower 32-bits of MSR value.\r | |
| 1373 | @param EDX Upper 32-bits of MSR value.\r | |
| 1374 | \r | |
| 1375 | <b>Example usage</b>\r | |
| 1376 | @code\r | |
| 1377 | UINT64 Msr;\r | |
| 1378 | \r | |
| 1379 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);\r | |
| 1380 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);\r | |
| 1381 | @endcode\r | |
| fed6c37b | 1382 | @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1383 | **/\r |
| 1384 | #define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA\r | |
| 1385 | \r | |
| 1386 | \r | |
| 1387 | /**\r | |
| 1388 | Package. Uncore C-box 6 perfmon box wide filter1.\r | |
| 1389 | \r | |
| 1390 | @param ECX MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)\r | |
| 1391 | @param EAX Lower 32-bits of MSR value.\r | |
| 1392 | @param EDX Upper 32-bits of MSR value.\r | |
| 1393 | \r | |
| 1394 | <b>Example usage</b>\r | |
| 1395 | @code\r | |
| 1396 | UINT64 Msr;\r | |
| 1397 | \r | |
| 1398 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);\r | |
| 1399 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);\r | |
| 1400 | @endcode\r | |
| fed6c37b | 1401 | @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1402 | **/\r |
| 1403 | #define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA\r | |
| 1404 | \r | |
| 1405 | \r | |
| 1406 | /**\r | |
| 1407 | Package. Uncore C-box 7 perfmon box wide filter1.\r | |
| 1408 | \r | |
| 1409 | @param ECX MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)\r | |
| 1410 | @param EAX Lower 32-bits of MSR value.\r | |
| 1411 | @param EDX Upper 32-bits of MSR value.\r | |
| 1412 | \r | |
| 1413 | <b>Example usage</b>\r | |
| 1414 | @code\r | |
| 1415 | UINT64 Msr;\r | |
| 1416 | \r | |
| 1417 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);\r | |
| 1418 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);\r | |
| 1419 | @endcode\r | |
| fed6c37b | 1420 | @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1421 | **/\r |
| 1422 | #define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA\r | |
| 1423 | \r | |
| 1424 | \r | |
| 1425 | /**\r | |
| 1426 | Package. Uncore C-box 8 perfmon local box wide control.\r | |
| 1427 | \r | |
| 1428 | @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)\r | |
| 1429 | @param EAX Lower 32-bits of MSR value.\r | |
| 1430 | @param EDX Upper 32-bits of MSR value.\r | |
| 1431 | \r | |
| 1432 | <b>Example usage</b>\r | |
| 1433 | @code\r | |
| 1434 | UINT64 Msr;\r | |
| 1435 | \r | |
| 1436 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);\r | |
| 1437 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);\r | |
| 1438 | @endcode\r | |
| fed6c37b | 1439 | @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
1440 | **/\r |
| 1441 | #define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04\r | |
| 1442 | \r | |
| 1443 | \r | |
| 1444 | /**\r | |
| 1445 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.\r | |
| 1446 | \r | |
| 1447 | @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)\r | |
| 1448 | @param EAX Lower 32-bits of MSR value.\r | |
| 1449 | @param EDX Upper 32-bits of MSR value.\r | |
| 1450 | \r | |
| 1451 | <b>Example usage</b>\r | |
| 1452 | @code\r | |
| 1453 | UINT64 Msr;\r | |
| 1454 | \r | |
| 1455 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);\r | |
| 1456 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);\r | |
| 1457 | @endcode\r | |
| fed6c37b | 1458 | @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
1459 | **/\r |
| 1460 | #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10\r | |
| 1461 | \r | |
| 1462 | \r | |
| 1463 | /**\r | |
| 1464 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.\r | |
| 1465 | \r | |
| 1466 | @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)\r | |
| 1467 | @param EAX Lower 32-bits of MSR value.\r | |
| 1468 | @param EDX Upper 32-bits of MSR value.\r | |
| 1469 | \r | |
| 1470 | <b>Example usage</b>\r | |
| 1471 | @code\r | |
| 1472 | UINT64 Msr;\r | |
| 1473 | \r | |
| 1474 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);\r | |
| 1475 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);\r | |
| 1476 | @endcode\r | |
| fed6c37b | 1477 | @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
1478 | **/\r |
| 1479 | #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11\r | |
| 1480 | \r | |
| 1481 | \r | |
| 1482 | /**\r | |
| 1483 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.\r | |
| 1484 | \r | |
| 1485 | @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)\r | |
| 1486 | @param EAX Lower 32-bits of MSR value.\r | |
| 1487 | @param EDX Upper 32-bits of MSR value.\r | |
| 1488 | \r | |
| 1489 | <b>Example usage</b>\r | |
| 1490 | @code\r | |
| 1491 | UINT64 Msr;\r | |
| 1492 | \r | |
| 1493 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);\r | |
| 1494 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);\r | |
| 1495 | @endcode\r | |
| fed6c37b | 1496 | @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
1497 | **/\r |
| 1498 | #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12\r | |
| 1499 | \r | |
| 1500 | \r | |
| 1501 | /**\r | |
| 1502 | Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.\r | |
| 1503 | \r | |
| 1504 | @param ECX MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)\r | |
| 1505 | @param EAX Lower 32-bits of MSR value.\r | |
| 1506 | @param EDX Upper 32-bits of MSR value.\r | |
| 1507 | \r | |
| 1508 | <b>Example usage</b>\r | |
| 1509 | @code\r | |
| 1510 | UINT64 Msr;\r | |
| 1511 | \r | |
| 1512 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);\r | |
| 1513 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);\r | |
| 1514 | @endcode\r | |
| fed6c37b | 1515 | @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
1516 | **/\r |
| 1517 | #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13\r | |
| 1518 | \r | |
| 1519 | \r | |
| 1520 | /**\r | |
| 1521 | Package. Uncore C-box 8 perfmon box wide filter.\r | |
| 1522 | \r | |
| 1523 | @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)\r | |
| 1524 | @param EAX Lower 32-bits of MSR value.\r | |
| 1525 | @param EDX Upper 32-bits of MSR value.\r | |
| 1526 | \r | |
| 1527 | <b>Example usage</b>\r | |
| 1528 | @code\r | |
| 1529 | UINT64 Msr;\r | |
| 1530 | \r | |
| 1531 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);\r | |
| 1532 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);\r | |
| 1533 | @endcode\r | |
| fed6c37b | 1534 | @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
1535 | **/\r |
| 1536 | #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14\r | |
| 1537 | \r | |
| 1538 | \r | |
| 1539 | /**\r | |
| 1540 | Package. Uncore C-box 8 perfmon counter 0.\r | |
| 1541 | \r | |
| 1542 | @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)\r | |
| 1543 | @param EAX Lower 32-bits of MSR value.\r | |
| 1544 | @param EDX Upper 32-bits of MSR value.\r | |
| 1545 | \r | |
| 1546 | <b>Example usage</b>\r | |
| 1547 | @code\r | |
| 1548 | UINT64 Msr;\r | |
| 1549 | \r | |
| 1550 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);\r | |
| 1551 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);\r | |
| 1552 | @endcode\r | |
| fed6c37b | 1553 | @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
1554 | **/\r |
| 1555 | #define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16\r | |
| 1556 | \r | |
| 1557 | \r | |
| 1558 | /**\r | |
| 1559 | Package. Uncore C-box 8 perfmon counter 1.\r | |
| 1560 | \r | |
| 1561 | @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)\r | |
| 1562 | @param EAX Lower 32-bits of MSR value.\r | |
| 1563 | @param EDX Upper 32-bits of MSR value.\r | |
| 1564 | \r | |
| 1565 | <b>Example usage</b>\r | |
| 1566 | @code\r | |
| 1567 | UINT64 Msr;\r | |
| 1568 | \r | |
| 1569 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);\r | |
| 1570 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);\r | |
| 1571 | @endcode\r | |
| fed6c37b | 1572 | @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
1573 | **/\r |
| 1574 | #define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17\r | |
| 1575 | \r | |
| 1576 | \r | |
| 1577 | /**\r | |
| 1578 | Package. Uncore C-box 8 perfmon counter 2.\r | |
| 1579 | \r | |
| 1580 | @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)\r | |
| 1581 | @param EAX Lower 32-bits of MSR value.\r | |
| 1582 | @param EDX Upper 32-bits of MSR value.\r | |
| 1583 | \r | |
| 1584 | <b>Example usage</b>\r | |
| 1585 | @code\r | |
| 1586 | UINT64 Msr;\r | |
| 1587 | \r | |
| 1588 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);\r | |
| 1589 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);\r | |
| 1590 | @endcode\r | |
| fed6c37b | 1591 | @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
1592 | **/\r |
| 1593 | #define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18\r | |
| 1594 | \r | |
| 1595 | \r | |
| 1596 | /**\r | |
| 1597 | Package. Uncore C-box 8 perfmon counter 3.\r | |
| 1598 | \r | |
| 1599 | @param ECX MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)\r | |
| 1600 | @param EAX Lower 32-bits of MSR value.\r | |
| 1601 | @param EDX Upper 32-bits of MSR value.\r | |
| 1602 | \r | |
| 1603 | <b>Example usage</b>\r | |
| 1604 | @code\r | |
| 1605 | UINT64 Msr;\r | |
| 1606 | \r | |
| 1607 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);\r | |
| 1608 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);\r | |
| 1609 | @endcode\r | |
| fed6c37b | 1610 | @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
1611 | **/\r |
| 1612 | #define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19\r | |
| 1613 | \r | |
| 1614 | \r | |
| 1615 | /**\r | |
| 1616 | Package. Uncore C-box 8 perfmon box wide filter1.\r | |
| 1617 | \r | |
| 1618 | @param ECX MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)\r | |
| 1619 | @param EAX Lower 32-bits of MSR value.\r | |
| 1620 | @param EDX Upper 32-bits of MSR value.\r | |
| 1621 | \r | |
| 1622 | <b>Example usage</b>\r | |
| 1623 | @code\r | |
| 1624 | UINT64 Msr;\r | |
| 1625 | \r | |
| 1626 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);\r | |
| 1627 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);\r | |
| 1628 | @endcode\r | |
| fed6c37b | 1629 | @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1630 | **/\r |
| 1631 | #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A\r | |
| 1632 | \r | |
| 1633 | \r | |
| 1634 | /**\r | |
| 1635 | Package. Uncore C-box 9 perfmon local box wide control.\r | |
| 1636 | \r | |
| 1637 | @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)\r | |
| 1638 | @param EAX Lower 32-bits of MSR value.\r | |
| 1639 | @param EDX Upper 32-bits of MSR value.\r | |
| 1640 | \r | |
| 1641 | <b>Example usage</b>\r | |
| 1642 | @code\r | |
| 1643 | UINT64 Msr;\r | |
| 1644 | \r | |
| 1645 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);\r | |
| 1646 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);\r | |
| 1647 | @endcode\r | |
| fed6c37b | 1648 | @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
1649 | **/\r |
| 1650 | #define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24\r | |
| 1651 | \r | |
| 1652 | \r | |
| 1653 | /**\r | |
| 1654 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.\r | |
| 1655 | \r | |
| 1656 | @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)\r | |
| 1657 | @param EAX Lower 32-bits of MSR value.\r | |
| 1658 | @param EDX Upper 32-bits of MSR value.\r | |
| 1659 | \r | |
| 1660 | <b>Example usage</b>\r | |
| 1661 | @code\r | |
| 1662 | UINT64 Msr;\r | |
| 1663 | \r | |
| 1664 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);\r | |
| 1665 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);\r | |
| 1666 | @endcode\r | |
| fed6c37b | 1667 | @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
1668 | **/\r |
| 1669 | #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30\r | |
| 1670 | \r | |
| 1671 | \r | |
| 1672 | /**\r | |
| 1673 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.\r | |
| 1674 | \r | |
| 1675 | @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)\r | |
| 1676 | @param EAX Lower 32-bits of MSR value.\r | |
| 1677 | @param EDX Upper 32-bits of MSR value.\r | |
| 1678 | \r | |
| 1679 | <b>Example usage</b>\r | |
| 1680 | @code\r | |
| 1681 | UINT64 Msr;\r | |
| 1682 | \r | |
| 1683 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);\r | |
| 1684 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);\r | |
| 1685 | @endcode\r | |
| fed6c37b | 1686 | @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
1687 | **/\r |
| 1688 | #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31\r | |
| 1689 | \r | |
| 1690 | \r | |
| 1691 | /**\r | |
| 1692 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.\r | |
| 1693 | \r | |
| 1694 | @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)\r | |
| 1695 | @param EAX Lower 32-bits of MSR value.\r | |
| 1696 | @param EDX Upper 32-bits of MSR value.\r | |
| 1697 | \r | |
| 1698 | <b>Example usage</b>\r | |
| 1699 | @code\r | |
| 1700 | UINT64 Msr;\r | |
| 1701 | \r | |
| 1702 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);\r | |
| 1703 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);\r | |
| 1704 | @endcode\r | |
| fed6c37b | 1705 | @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
1706 | **/\r |
| 1707 | #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32\r | |
| 1708 | \r | |
| 1709 | \r | |
| 1710 | /**\r | |
| 1711 | Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.\r | |
| 1712 | \r | |
| 1713 | @param ECX MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)\r | |
| 1714 | @param EAX Lower 32-bits of MSR value.\r | |
| 1715 | @param EDX Upper 32-bits of MSR value.\r | |
| 1716 | \r | |
| 1717 | <b>Example usage</b>\r | |
| 1718 | @code\r | |
| 1719 | UINT64 Msr;\r | |
| 1720 | \r | |
| 1721 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);\r | |
| 1722 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);\r | |
| 1723 | @endcode\r | |
| fed6c37b | 1724 | @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
1725 | **/\r |
| 1726 | #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33\r | |
| 1727 | \r | |
| 1728 | \r | |
| 1729 | /**\r | |
| 1730 | Package. Uncore C-box 9 perfmon box wide filter.\r | |
| 1731 | \r | |
| 1732 | @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)\r | |
| 1733 | @param EAX Lower 32-bits of MSR value.\r | |
| 1734 | @param EDX Upper 32-bits of MSR value.\r | |
| 1735 | \r | |
| 1736 | <b>Example usage</b>\r | |
| 1737 | @code\r | |
| 1738 | UINT64 Msr;\r | |
| 1739 | \r | |
| 1740 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);\r | |
| 1741 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);\r | |
| 1742 | @endcode\r | |
| fed6c37b | 1743 | @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
1744 | **/\r |
| 1745 | #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34\r | |
| 1746 | \r | |
| 1747 | \r | |
| 1748 | /**\r | |
| 1749 | Package. Uncore C-box 9 perfmon counter 0.\r | |
| 1750 | \r | |
| 1751 | @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)\r | |
| 1752 | @param EAX Lower 32-bits of MSR value.\r | |
| 1753 | @param EDX Upper 32-bits of MSR value.\r | |
| 1754 | \r | |
| 1755 | <b>Example usage</b>\r | |
| 1756 | @code\r | |
| 1757 | UINT64 Msr;\r | |
| 1758 | \r | |
| 1759 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);\r | |
| 1760 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);\r | |
| 1761 | @endcode\r | |
| fed6c37b | 1762 | @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
1763 | **/\r |
| 1764 | #define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36\r | |
| 1765 | \r | |
| 1766 | \r | |
| 1767 | /**\r | |
| 1768 | Package. Uncore C-box 9 perfmon counter 1.\r | |
| 1769 | \r | |
| 1770 | @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)\r | |
| 1771 | @param EAX Lower 32-bits of MSR value.\r | |
| 1772 | @param EDX Upper 32-bits of MSR value.\r | |
| 1773 | \r | |
| 1774 | <b>Example usage</b>\r | |
| 1775 | @code\r | |
| 1776 | UINT64 Msr;\r | |
| 1777 | \r | |
| 1778 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);\r | |
| 1779 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);\r | |
| 1780 | @endcode\r | |
| fed6c37b | 1781 | @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
1782 | **/\r |
| 1783 | #define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37\r | |
| 1784 | \r | |
| 1785 | \r | |
| 1786 | /**\r | |
| 1787 | Package. Uncore C-box 9 perfmon counter 2.\r | |
| 1788 | \r | |
| 1789 | @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)\r | |
| 1790 | @param EAX Lower 32-bits of MSR value.\r | |
| 1791 | @param EDX Upper 32-bits of MSR value.\r | |
| 1792 | \r | |
| 1793 | <b>Example usage</b>\r | |
| 1794 | @code\r | |
| 1795 | UINT64 Msr;\r | |
| 1796 | \r | |
| 1797 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);\r | |
| 1798 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);\r | |
| 1799 | @endcode\r | |
| fed6c37b | 1800 | @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
1801 | **/\r |
| 1802 | #define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38\r | |
| 1803 | \r | |
| 1804 | \r | |
| 1805 | /**\r | |
| 1806 | Package. Uncore C-box 9 perfmon counter 3.\r | |
| 1807 | \r | |
| 1808 | @param ECX MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)\r | |
| 1809 | @param EAX Lower 32-bits of MSR value.\r | |
| 1810 | @param EDX Upper 32-bits of MSR value.\r | |
| 1811 | \r | |
| 1812 | <b>Example usage</b>\r | |
| 1813 | @code\r | |
| 1814 | UINT64 Msr;\r | |
| 1815 | \r | |
| 1816 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);\r | |
| 1817 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);\r | |
| 1818 | @endcode\r | |
| fed6c37b | 1819 | @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
1820 | **/\r |
| 1821 | #define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39\r | |
| 1822 | \r | |
| 1823 | \r | |
| 1824 | /**\r | |
| 1825 | Package. Uncore C-box 9 perfmon box wide filter1.\r | |
| 1826 | \r | |
| 1827 | @param ECX MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)\r | |
| 1828 | @param EAX Lower 32-bits of MSR value.\r | |
| 1829 | @param EDX Upper 32-bits of MSR value.\r | |
| 1830 | \r | |
| 1831 | <b>Example usage</b>\r | |
| 1832 | @code\r | |
| 1833 | UINT64 Msr;\r | |
| 1834 | \r | |
| 1835 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);\r | |
| 1836 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);\r | |
| 1837 | @endcode\r | |
| fed6c37b | 1838 | @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
1839 | **/\r |
| 1840 | #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A\r | |
| 1841 | \r | |
| 1842 | \r | |
| 1843 | /**\r | |
| 1844 | Package. Uncore C-box 10 perfmon local box wide control.\r | |
| 1845 | \r | |
| 1846 | @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)\r | |
| 1847 | @param EAX Lower 32-bits of MSR value.\r | |
| 1848 | @param EDX Upper 32-bits of MSR value.\r | |
| 1849 | \r | |
| 1850 | <b>Example usage</b>\r | |
| 1851 | @code\r | |
| 1852 | UINT64 Msr;\r | |
| 1853 | \r | |
| 1854 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);\r | |
| 1855 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);\r | |
| 1856 | @endcode\r | |
| fed6c37b | 1857 | @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
1858 | **/\r |
| 1859 | #define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44\r | |
| 1860 | \r | |
| 1861 | \r | |
| 1862 | /**\r | |
| 1863 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.\r | |
| 1864 | \r | |
| 1865 | @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)\r | |
| 1866 | @param EAX Lower 32-bits of MSR value.\r | |
| 1867 | @param EDX Upper 32-bits of MSR value.\r | |
| 1868 | \r | |
| 1869 | <b>Example usage</b>\r | |
| 1870 | @code\r | |
| 1871 | UINT64 Msr;\r | |
| 1872 | \r | |
| 1873 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);\r | |
| 1874 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);\r | |
| 1875 | @endcode\r | |
| fed6c37b | 1876 | @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
1877 | **/\r |
| 1878 | #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50\r | |
| 1879 | \r | |
| 1880 | \r | |
| 1881 | /**\r | |
| 1882 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.\r | |
| 1883 | \r | |
| 1884 | @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)\r | |
| 1885 | @param EAX Lower 32-bits of MSR value.\r | |
| 1886 | @param EDX Upper 32-bits of MSR value.\r | |
| 1887 | \r | |
| 1888 | <b>Example usage</b>\r | |
| 1889 | @code\r | |
| 1890 | UINT64 Msr;\r | |
| 1891 | \r | |
| 1892 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);\r | |
| 1893 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);\r | |
| 1894 | @endcode\r | |
| fed6c37b | 1895 | @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
1896 | **/\r |
| 1897 | #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51\r | |
| 1898 | \r | |
| 1899 | \r | |
| 1900 | /**\r | |
| 1901 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.\r | |
| 1902 | \r | |
| 1903 | @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)\r | |
| 1904 | @param EAX Lower 32-bits of MSR value.\r | |
| 1905 | @param EDX Upper 32-bits of MSR value.\r | |
| 1906 | \r | |
| 1907 | <b>Example usage</b>\r | |
| 1908 | @code\r | |
| 1909 | UINT64 Msr;\r | |
| 1910 | \r | |
| 1911 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);\r | |
| 1912 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);\r | |
| 1913 | @endcode\r | |
| fed6c37b | 1914 | @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
1915 | **/\r |
| 1916 | #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52\r | |
| 1917 | \r | |
| 1918 | \r | |
| 1919 | /**\r | |
| 1920 | Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.\r | |
| 1921 | \r | |
| 1922 | @param ECX MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)\r | |
| 1923 | @param EAX Lower 32-bits of MSR value.\r | |
| 1924 | @param EDX Upper 32-bits of MSR value.\r | |
| 1925 | \r | |
| 1926 | <b>Example usage</b>\r | |
| 1927 | @code\r | |
| 1928 | UINT64 Msr;\r | |
| 1929 | \r | |
| 1930 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);\r | |
| 1931 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);\r | |
| 1932 | @endcode\r | |
| fed6c37b | 1933 | @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
1934 | **/\r |
| 1935 | #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53\r | |
| 1936 | \r | |
| 1937 | \r | |
| 1938 | /**\r | |
| 1939 | Package. Uncore C-box 10 perfmon box wide filter.\r | |
| 1940 | \r | |
| 1941 | @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)\r | |
| 1942 | @param EAX Lower 32-bits of MSR value.\r | |
| 1943 | @param EDX Upper 32-bits of MSR value.\r | |
| 1944 | \r | |
| 1945 | <b>Example usage</b>\r | |
| 1946 | @code\r | |
| 1947 | UINT64 Msr;\r | |
| 1948 | \r | |
| 1949 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);\r | |
| 1950 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);\r | |
| 1951 | @endcode\r | |
| fed6c37b | 1952 | @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
1953 | **/\r |
| 1954 | #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54\r | |
| 1955 | \r | |
| 1956 | \r | |
| 1957 | /**\r | |
| 1958 | Package. Uncore C-box 10 perfmon counter 0.\r | |
| 1959 | \r | |
| 1960 | @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)\r | |
| 1961 | @param EAX Lower 32-bits of MSR value.\r | |
| 1962 | @param EDX Upper 32-bits of MSR value.\r | |
| 1963 | \r | |
| 1964 | <b>Example usage</b>\r | |
| 1965 | @code\r | |
| 1966 | UINT64 Msr;\r | |
| 1967 | \r | |
| 1968 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);\r | |
| 1969 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);\r | |
| 1970 | @endcode\r | |
| fed6c37b | 1971 | @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
1972 | **/\r |
| 1973 | #define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56\r | |
| 1974 | \r | |
| 1975 | \r | |
| 1976 | /**\r | |
| 1977 | Package. Uncore C-box 10 perfmon counter 1.\r | |
| 1978 | \r | |
| 1979 | @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)\r | |
| 1980 | @param EAX Lower 32-bits of MSR value.\r | |
| 1981 | @param EDX Upper 32-bits of MSR value.\r | |
| 1982 | \r | |
| 1983 | <b>Example usage</b>\r | |
| 1984 | @code\r | |
| 1985 | UINT64 Msr;\r | |
| 1986 | \r | |
| 1987 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);\r | |
| 1988 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);\r | |
| 1989 | @endcode\r | |
| fed6c37b | 1990 | @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
1991 | **/\r |
| 1992 | #define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57\r | |
| 1993 | \r | |
| 1994 | \r | |
| 1995 | /**\r | |
| 1996 | Package. Uncore C-box 10 perfmon counter 2.\r | |
| 1997 | \r | |
| 1998 | @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)\r | |
| 1999 | @param EAX Lower 32-bits of MSR value.\r | |
| 2000 | @param EDX Upper 32-bits of MSR value.\r | |
| 2001 | \r | |
| 2002 | <b>Example usage</b>\r | |
| 2003 | @code\r | |
| 2004 | UINT64 Msr;\r | |
| 2005 | \r | |
| 2006 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);\r | |
| 2007 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);\r | |
| 2008 | @endcode\r | |
| fed6c37b | 2009 | @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
2010 | **/\r |
| 2011 | #define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58\r | |
| 2012 | \r | |
| 2013 | \r | |
| 2014 | /**\r | |
| 2015 | Package. Uncore C-box 10 perfmon counter 3.\r | |
| 2016 | \r | |
| 2017 | @param ECX MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)\r | |
| 2018 | @param EAX Lower 32-bits of MSR value.\r | |
| 2019 | @param EDX Upper 32-bits of MSR value.\r | |
| 2020 | \r | |
| 2021 | <b>Example usage</b>\r | |
| 2022 | @code\r | |
| 2023 | UINT64 Msr;\r | |
| 2024 | \r | |
| 2025 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);\r | |
| 2026 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);\r | |
| 2027 | @endcode\r | |
| fed6c37b | 2028 | @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
2029 | **/\r |
| 2030 | #define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59\r | |
| 2031 | \r | |
| 2032 | \r | |
| 2033 | /**\r | |
| 2034 | Package. Uncore C-box 10 perfmon box wide filter1.\r | |
| 2035 | \r | |
| 2036 | @param ECX MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)\r | |
| 2037 | @param EAX Lower 32-bits of MSR value.\r | |
| 2038 | @param EDX Upper 32-bits of MSR value.\r | |
| 2039 | \r | |
| 2040 | <b>Example usage</b>\r | |
| 2041 | @code\r | |
| 2042 | UINT64 Msr;\r | |
| 2043 | \r | |
| 2044 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);\r | |
| 2045 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);\r | |
| 2046 | @endcode\r | |
| fed6c37b | 2047 | @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
2048 | **/\r |
| 2049 | #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A\r | |
| 2050 | \r | |
| 2051 | \r | |
| 2052 | /**\r | |
| 2053 | Package. Uncore C-box 11 perfmon local box wide control.\r | |
| 2054 | \r | |
| 2055 | @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)\r | |
| 2056 | @param EAX Lower 32-bits of MSR value.\r | |
| 2057 | @param EDX Upper 32-bits of MSR value.\r | |
| 2058 | \r | |
| 2059 | <b>Example usage</b>\r | |
| 2060 | @code\r | |
| 2061 | UINT64 Msr;\r | |
| 2062 | \r | |
| 2063 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);\r | |
| 2064 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);\r | |
| 2065 | @endcode\r | |
| fed6c37b | 2066 | @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
2067 | **/\r |
| 2068 | #define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64\r | |
| 2069 | \r | |
| 2070 | \r | |
| 2071 | /**\r | |
| 2072 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.\r | |
| 2073 | \r | |
| 2074 | @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)\r | |
| 2075 | @param EAX Lower 32-bits of MSR value.\r | |
| 2076 | @param EDX Upper 32-bits of MSR value.\r | |
| 2077 | \r | |
| 2078 | <b>Example usage</b>\r | |
| 2079 | @code\r | |
| 2080 | UINT64 Msr;\r | |
| 2081 | \r | |
| 2082 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);\r | |
| 2083 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);\r | |
| 2084 | @endcode\r | |
| fed6c37b | 2085 | @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
2086 | **/\r |
| 2087 | #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70\r | |
| 2088 | \r | |
| 2089 | \r | |
| 2090 | /**\r | |
| 2091 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.\r | |
| 2092 | \r | |
| 2093 | @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)\r | |
| 2094 | @param EAX Lower 32-bits of MSR value.\r | |
| 2095 | @param EDX Upper 32-bits of MSR value.\r | |
| 2096 | \r | |
| 2097 | <b>Example usage</b>\r | |
| 2098 | @code\r | |
| 2099 | UINT64 Msr;\r | |
| 2100 | \r | |
| 2101 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);\r | |
| 2102 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);\r | |
| 2103 | @endcode\r | |
| fed6c37b | 2104 | @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
2105 | **/\r |
| 2106 | #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71\r | |
| 2107 | \r | |
| 2108 | \r | |
| 2109 | /**\r | |
| 2110 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.\r | |
| 2111 | \r | |
| 2112 | @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)\r | |
| 2113 | @param EAX Lower 32-bits of MSR value.\r | |
| 2114 | @param EDX Upper 32-bits of MSR value.\r | |
| 2115 | \r | |
| 2116 | <b>Example usage</b>\r | |
| 2117 | @code\r | |
| 2118 | UINT64 Msr;\r | |
| 2119 | \r | |
| 2120 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);\r | |
| 2121 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);\r | |
| 2122 | @endcode\r | |
| fed6c37b | 2123 | @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
2124 | **/\r |
| 2125 | #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72\r | |
| 2126 | \r | |
| 2127 | \r | |
| 2128 | /**\r | |
| 2129 | Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.\r | |
| 2130 | \r | |
| 2131 | @param ECX MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)\r | |
| 2132 | @param EAX Lower 32-bits of MSR value.\r | |
| 2133 | @param EDX Upper 32-bits of MSR value.\r | |
| 2134 | \r | |
| 2135 | <b>Example usage</b>\r | |
| 2136 | @code\r | |
| 2137 | UINT64 Msr;\r | |
| 2138 | \r | |
| 2139 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);\r | |
| 2140 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);\r | |
| 2141 | @endcode\r | |
| fed6c37b | 2142 | @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
2143 | **/\r |
| 2144 | #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73\r | |
| 2145 | \r | |
| 2146 | \r | |
| 2147 | /**\r | |
| 2148 | Package. Uncore C-box 11 perfmon box wide filter.\r | |
| 2149 | \r | |
| 2150 | @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)\r | |
| 2151 | @param EAX Lower 32-bits of MSR value.\r | |
| 2152 | @param EDX Upper 32-bits of MSR value.\r | |
| 2153 | \r | |
| 2154 | <b>Example usage</b>\r | |
| 2155 | @code\r | |
| 2156 | UINT64 Msr;\r | |
| 2157 | \r | |
| 2158 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);\r | |
| 2159 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);\r | |
| 2160 | @endcode\r | |
| fed6c37b | 2161 | @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
2162 | **/\r |
| 2163 | #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74\r | |
| 2164 | \r | |
| 2165 | \r | |
| 2166 | /**\r | |
| 2167 | Package. Uncore C-box 11 perfmon counter 0.\r | |
| 2168 | \r | |
| 2169 | @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)\r | |
| 2170 | @param EAX Lower 32-bits of MSR value.\r | |
| 2171 | @param EDX Upper 32-bits of MSR value.\r | |
| 2172 | \r | |
| 2173 | <b>Example usage</b>\r | |
| 2174 | @code\r | |
| 2175 | UINT64 Msr;\r | |
| 2176 | \r | |
| 2177 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);\r | |
| 2178 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);\r | |
| 2179 | @endcode\r | |
| fed6c37b | 2180 | @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
2181 | **/\r |
| 2182 | #define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76\r | |
| 2183 | \r | |
| 2184 | \r | |
| 2185 | /**\r | |
| 2186 | Package. Uncore C-box 11 perfmon counter 1.\r | |
| 2187 | \r | |
| 2188 | @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)\r | |
| 2189 | @param EAX Lower 32-bits of MSR value.\r | |
| 2190 | @param EDX Upper 32-bits of MSR value.\r | |
| 2191 | \r | |
| 2192 | <b>Example usage</b>\r | |
| 2193 | @code\r | |
| 2194 | UINT64 Msr;\r | |
| 2195 | \r | |
| 2196 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);\r | |
| 2197 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);\r | |
| 2198 | @endcode\r | |
| fed6c37b | 2199 | @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
2200 | **/\r |
| 2201 | #define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77\r | |
| 2202 | \r | |
| 2203 | \r | |
| 2204 | /**\r | |
| 2205 | Package. Uncore C-box 11 perfmon counter 2.\r | |
| 2206 | \r | |
| 2207 | @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)\r | |
| 2208 | @param EAX Lower 32-bits of MSR value.\r | |
| 2209 | @param EDX Upper 32-bits of MSR value.\r | |
| 2210 | \r | |
| 2211 | <b>Example usage</b>\r | |
| 2212 | @code\r | |
| 2213 | UINT64 Msr;\r | |
| 2214 | \r | |
| 2215 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);\r | |
| 2216 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);\r | |
| 2217 | @endcode\r | |
| fed6c37b | 2218 | @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
2219 | **/\r |
| 2220 | #define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78\r | |
| 2221 | \r | |
| 2222 | \r | |
| 2223 | /**\r | |
| 2224 | Package. Uncore C-box 11 perfmon counter 3.\r | |
| 2225 | \r | |
| 2226 | @param ECX MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)\r | |
| 2227 | @param EAX Lower 32-bits of MSR value.\r | |
| 2228 | @param EDX Upper 32-bits of MSR value.\r | |
| 2229 | \r | |
| 2230 | <b>Example usage</b>\r | |
| 2231 | @code\r | |
| 2232 | UINT64 Msr;\r | |
| 2233 | \r | |
| 2234 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);\r | |
| 2235 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);\r | |
| 2236 | @endcode\r | |
| fed6c37b | 2237 | @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
2238 | **/\r |
| 2239 | #define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79\r | |
| 2240 | \r | |
| 2241 | \r | |
| 2242 | /**\r | |
| 2243 | Package. Uncore C-box 11 perfmon box wide filter1.\r | |
| 2244 | \r | |
| 2245 | @param ECX MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)\r | |
| 2246 | @param EAX Lower 32-bits of MSR value.\r | |
| 2247 | @param EDX Upper 32-bits of MSR value.\r | |
| 2248 | \r | |
| 2249 | <b>Example usage</b>\r | |
| 2250 | @code\r | |
| 2251 | UINT64 Msr;\r | |
| 2252 | \r | |
| 2253 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);\r | |
| 2254 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);\r | |
| 2255 | @endcode\r | |
| fed6c37b | 2256 | @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
2257 | **/\r |
| 2258 | #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A\r | |
| 2259 | \r | |
| 2260 | \r | |
| 2261 | /**\r | |
| 2262 | Package. Uncore C-box 12 perfmon local box wide control.\r | |
| 2263 | \r | |
| 2264 | @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)\r | |
| 2265 | @param EAX Lower 32-bits of MSR value.\r | |
| 2266 | @param EDX Upper 32-bits of MSR value.\r | |
| 2267 | \r | |
| 2268 | <b>Example usage</b>\r | |
| 2269 | @code\r | |
| 2270 | UINT64 Msr;\r | |
| 2271 | \r | |
| 2272 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);\r | |
| 2273 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);\r | |
| 2274 | @endcode\r | |
| fed6c37b | 2275 | @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
2276 | **/\r |
| 2277 | #define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84\r | |
| 2278 | \r | |
| 2279 | \r | |
| 2280 | /**\r | |
| 2281 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.\r | |
| 2282 | \r | |
| 2283 | @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)\r | |
| 2284 | @param EAX Lower 32-bits of MSR value.\r | |
| 2285 | @param EDX Upper 32-bits of MSR value.\r | |
| 2286 | \r | |
| 2287 | <b>Example usage</b>\r | |
| 2288 | @code\r | |
| 2289 | UINT64 Msr;\r | |
| 2290 | \r | |
| 2291 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);\r | |
| 2292 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);\r | |
| 2293 | @endcode\r | |
| fed6c37b | 2294 | @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
2295 | **/\r |
| 2296 | #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90\r | |
| 2297 | \r | |
| 2298 | \r | |
| 2299 | /**\r | |
| 2300 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.\r | |
| 2301 | \r | |
| 2302 | @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)\r | |
| 2303 | @param EAX Lower 32-bits of MSR value.\r | |
| 2304 | @param EDX Upper 32-bits of MSR value.\r | |
| 2305 | \r | |
| 2306 | <b>Example usage</b>\r | |
| 2307 | @code\r | |
| 2308 | UINT64 Msr;\r | |
| 2309 | \r | |
| 2310 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);\r | |
| 2311 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);\r | |
| 2312 | @endcode\r | |
| fed6c37b | 2313 | @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
2314 | **/\r |
| 2315 | #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91\r | |
| 2316 | \r | |
| 2317 | \r | |
| 2318 | /**\r | |
| 2319 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.\r | |
| 2320 | \r | |
| 2321 | @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)\r | |
| 2322 | @param EAX Lower 32-bits of MSR value.\r | |
| 2323 | @param EDX Upper 32-bits of MSR value.\r | |
| 2324 | \r | |
| 2325 | <b>Example usage</b>\r | |
| 2326 | @code\r | |
| 2327 | UINT64 Msr;\r | |
| 2328 | \r | |
| 2329 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);\r | |
| 2330 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);\r | |
| 2331 | @endcode\r | |
| fed6c37b | 2332 | @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
2333 | **/\r |
| 2334 | #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92\r | |
| 2335 | \r | |
| 2336 | \r | |
| 2337 | /**\r | |
| 2338 | Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.\r | |
| 2339 | \r | |
| 2340 | @param ECX MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)\r | |
| 2341 | @param EAX Lower 32-bits of MSR value.\r | |
| 2342 | @param EDX Upper 32-bits of MSR value.\r | |
| 2343 | \r | |
| 2344 | <b>Example usage</b>\r | |
| 2345 | @code\r | |
| 2346 | UINT64 Msr;\r | |
| 2347 | \r | |
| 2348 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);\r | |
| 2349 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);\r | |
| 2350 | @endcode\r | |
| fed6c37b | 2351 | @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
2352 | **/\r |
| 2353 | #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93\r | |
| 2354 | \r | |
| 2355 | \r | |
| 2356 | /**\r | |
| 2357 | Package. Uncore C-box 12 perfmon box wide filter.\r | |
| 2358 | \r | |
| 2359 | @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)\r | |
| 2360 | @param EAX Lower 32-bits of MSR value.\r | |
| 2361 | @param EDX Upper 32-bits of MSR value.\r | |
| 2362 | \r | |
| 2363 | <b>Example usage</b>\r | |
| 2364 | @code\r | |
| 2365 | UINT64 Msr;\r | |
| 2366 | \r | |
| 2367 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);\r | |
| 2368 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);\r | |
| 2369 | @endcode\r | |
| fed6c37b | 2370 | @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
2371 | **/\r |
| 2372 | #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94\r | |
| 2373 | \r | |
| 2374 | \r | |
| 2375 | /**\r | |
| 2376 | Package. Uncore C-box 12 perfmon counter 0.\r | |
| 2377 | \r | |
| 2378 | @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)\r | |
| 2379 | @param EAX Lower 32-bits of MSR value.\r | |
| 2380 | @param EDX Upper 32-bits of MSR value.\r | |
| 2381 | \r | |
| 2382 | <b>Example usage</b>\r | |
| 2383 | @code\r | |
| 2384 | UINT64 Msr;\r | |
| 2385 | \r | |
| 2386 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);\r | |
| 2387 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);\r | |
| 2388 | @endcode\r | |
| fed6c37b | 2389 | @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
2390 | **/\r |
| 2391 | #define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96\r | |
| 2392 | \r | |
| 2393 | \r | |
| 2394 | /**\r | |
| 2395 | Package. Uncore C-box 12 perfmon counter 1.\r | |
| 2396 | \r | |
| 2397 | @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)\r | |
| 2398 | @param EAX Lower 32-bits of MSR value.\r | |
| 2399 | @param EDX Upper 32-bits of MSR value.\r | |
| 2400 | \r | |
| 2401 | <b>Example usage</b>\r | |
| 2402 | @code\r | |
| 2403 | UINT64 Msr;\r | |
| 2404 | \r | |
| 2405 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);\r | |
| 2406 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);\r | |
| 2407 | @endcode\r | |
| fed6c37b | 2408 | @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
2409 | **/\r |
| 2410 | #define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97\r | |
| 2411 | \r | |
| 2412 | \r | |
| 2413 | /**\r | |
| 2414 | Package. Uncore C-box 12 perfmon counter 2.\r | |
| 2415 | \r | |
| 2416 | @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)\r | |
| 2417 | @param EAX Lower 32-bits of MSR value.\r | |
| 2418 | @param EDX Upper 32-bits of MSR value.\r | |
| 2419 | \r | |
| 2420 | <b>Example usage</b>\r | |
| 2421 | @code\r | |
| 2422 | UINT64 Msr;\r | |
| 2423 | \r | |
| 2424 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);\r | |
| 2425 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);\r | |
| 2426 | @endcode\r | |
| fed6c37b | 2427 | @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
2428 | **/\r |
| 2429 | #define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98\r | |
| 2430 | \r | |
| 2431 | \r | |
| 2432 | /**\r | |
| 2433 | Package. Uncore C-box 12 perfmon counter 3.\r | |
| 2434 | \r | |
| 2435 | @param ECX MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)\r | |
| 2436 | @param EAX Lower 32-bits of MSR value.\r | |
| 2437 | @param EDX Upper 32-bits of MSR value.\r | |
| 2438 | \r | |
| 2439 | <b>Example usage</b>\r | |
| 2440 | @code\r | |
| 2441 | UINT64 Msr;\r | |
| 2442 | \r | |
| 2443 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);\r | |
| 2444 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);\r | |
| 2445 | @endcode\r | |
| fed6c37b | 2446 | @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
2447 | **/\r |
| 2448 | #define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99\r | |
| 2449 | \r | |
| 2450 | \r | |
| 2451 | /**\r | |
| 2452 | Package. Uncore C-box 12 perfmon box wide filter1.\r | |
| 2453 | \r | |
| 2454 | @param ECX MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)\r | |
| 2455 | @param EAX Lower 32-bits of MSR value.\r | |
| 2456 | @param EDX Upper 32-bits of MSR value.\r | |
| 2457 | \r | |
| 2458 | <b>Example usage</b>\r | |
| 2459 | @code\r | |
| 2460 | UINT64 Msr;\r | |
| 2461 | \r | |
| 2462 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);\r | |
| 2463 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);\r | |
| 2464 | @endcode\r | |
| fed6c37b | 2465 | @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
2466 | **/\r |
| 2467 | #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A\r | |
| 2468 | \r | |
| 2469 | \r | |
| 2470 | /**\r | |
| 2471 | Package. Uncore C-box 13 perfmon local box wide control.\r | |
| 2472 | \r | |
| 2473 | @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)\r | |
| 2474 | @param EAX Lower 32-bits of MSR value.\r | |
| 2475 | @param EDX Upper 32-bits of MSR value.\r | |
| 2476 | \r | |
| 2477 | <b>Example usage</b>\r | |
| 2478 | @code\r | |
| 2479 | UINT64 Msr;\r | |
| 2480 | \r | |
| 2481 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);\r | |
| 2482 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);\r | |
| 2483 | @endcode\r | |
| fed6c37b | 2484 | @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
2485 | **/\r |
| 2486 | #define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4\r | |
| 2487 | \r | |
| 2488 | \r | |
| 2489 | /**\r | |
| 2490 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.\r | |
| 2491 | \r | |
| 2492 | @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)\r | |
| 2493 | @param EAX Lower 32-bits of MSR value.\r | |
| 2494 | @param EDX Upper 32-bits of MSR value.\r | |
| 2495 | \r | |
| 2496 | <b>Example usage</b>\r | |
| 2497 | @code\r | |
| 2498 | UINT64 Msr;\r | |
| 2499 | \r | |
| 2500 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);\r | |
| 2501 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);\r | |
| 2502 | @endcode\r | |
| fed6c37b | 2503 | @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
2504 | **/\r |
| 2505 | #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0\r | |
| 2506 | \r | |
| 2507 | \r | |
| 2508 | /**\r | |
| 2509 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.\r | |
| 2510 | \r | |
| 2511 | @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)\r | |
| 2512 | @param EAX Lower 32-bits of MSR value.\r | |
| 2513 | @param EDX Upper 32-bits of MSR value.\r | |
| 2514 | \r | |
| 2515 | <b>Example usage</b>\r | |
| 2516 | @code\r | |
| 2517 | UINT64 Msr;\r | |
| 2518 | \r | |
| 2519 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);\r | |
| 2520 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);\r | |
| 2521 | @endcode\r | |
| fed6c37b | 2522 | @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
2523 | **/\r |
| 2524 | #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1\r | |
| 2525 | \r | |
| 2526 | \r | |
| 2527 | /**\r | |
| 2528 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.\r | |
| 2529 | \r | |
| 2530 | @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)\r | |
| 2531 | @param EAX Lower 32-bits of MSR value.\r | |
| 2532 | @param EDX Upper 32-bits of MSR value.\r | |
| 2533 | \r | |
| 2534 | <b>Example usage</b>\r | |
| 2535 | @code\r | |
| 2536 | UINT64 Msr;\r | |
| 2537 | \r | |
| 2538 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);\r | |
| 2539 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);\r | |
| 2540 | @endcode\r | |
| fed6c37b | 2541 | @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
2542 | **/\r |
| 2543 | #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2\r | |
| 2544 | \r | |
| 2545 | \r | |
| 2546 | /**\r | |
| 2547 | Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.\r | |
| 2548 | \r | |
| 2549 | @param ECX MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)\r | |
| 2550 | @param EAX Lower 32-bits of MSR value.\r | |
| 2551 | @param EDX Upper 32-bits of MSR value.\r | |
| 2552 | \r | |
| 2553 | <b>Example usage</b>\r | |
| 2554 | @code\r | |
| 2555 | UINT64 Msr;\r | |
| 2556 | \r | |
| 2557 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);\r | |
| 2558 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);\r | |
| 2559 | @endcode\r | |
| fed6c37b | 2560 | @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
2561 | **/\r |
| 2562 | #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3\r | |
| 2563 | \r | |
| 2564 | \r | |
| 2565 | /**\r | |
| 2566 | Package. Uncore C-box 13 perfmon box wide filter.\r | |
| 2567 | \r | |
| 2568 | @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)\r | |
| 2569 | @param EAX Lower 32-bits of MSR value.\r | |
| 2570 | @param EDX Upper 32-bits of MSR value.\r | |
| 2571 | \r | |
| 2572 | <b>Example usage</b>\r | |
| 2573 | @code\r | |
| 2574 | UINT64 Msr;\r | |
| 2575 | \r | |
| 2576 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);\r | |
| 2577 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);\r | |
| 2578 | @endcode\r | |
| fed6c37b | 2579 | @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
2580 | **/\r |
| 2581 | #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4\r | |
| 2582 | \r | |
| 2583 | \r | |
| 2584 | /**\r | |
| 2585 | Package. Uncore C-box 13 perfmon counter 0.\r | |
| 2586 | \r | |
| 2587 | @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)\r | |
| 2588 | @param EAX Lower 32-bits of MSR value.\r | |
| 2589 | @param EDX Upper 32-bits of MSR value.\r | |
| 2590 | \r | |
| 2591 | <b>Example usage</b>\r | |
| 2592 | @code\r | |
| 2593 | UINT64 Msr;\r | |
| 2594 | \r | |
| 2595 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);\r | |
| 2596 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);\r | |
| 2597 | @endcode\r | |
| fed6c37b | 2598 | @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
2599 | **/\r |
| 2600 | #define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6\r | |
| 2601 | \r | |
| 2602 | \r | |
| 2603 | /**\r | |
| 2604 | Package. Uncore C-box 13 perfmon counter 1.\r | |
| 2605 | \r | |
| 2606 | @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)\r | |
| 2607 | @param EAX Lower 32-bits of MSR value.\r | |
| 2608 | @param EDX Upper 32-bits of MSR value.\r | |
| 2609 | \r | |
| 2610 | <b>Example usage</b>\r | |
| 2611 | @code\r | |
| 2612 | UINT64 Msr;\r | |
| 2613 | \r | |
| 2614 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);\r | |
| 2615 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);\r | |
| 2616 | @endcode\r | |
| fed6c37b | 2617 | @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
2618 | **/\r |
| 2619 | #define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7\r | |
| 2620 | \r | |
| 2621 | \r | |
| 2622 | /**\r | |
| 2623 | Package. Uncore C-box 13 perfmon counter 2.\r | |
| 2624 | \r | |
| 2625 | @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)\r | |
| 2626 | @param EAX Lower 32-bits of MSR value.\r | |
| 2627 | @param EDX Upper 32-bits of MSR value.\r | |
| 2628 | \r | |
| 2629 | <b>Example usage</b>\r | |
| 2630 | @code\r | |
| 2631 | UINT64 Msr;\r | |
| 2632 | \r | |
| 2633 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);\r | |
| 2634 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);\r | |
| 2635 | @endcode\r | |
| fed6c37b | 2636 | @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
2637 | **/\r |
| 2638 | #define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8\r | |
| 2639 | \r | |
| 2640 | \r | |
| 2641 | /**\r | |
| 2642 | Package. Uncore C-box 13 perfmon counter 3.\r | |
| 2643 | \r | |
| 2644 | @param ECX MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)\r | |
| 2645 | @param EAX Lower 32-bits of MSR value.\r | |
| 2646 | @param EDX Upper 32-bits of MSR value.\r | |
| 2647 | \r | |
| 2648 | <b>Example usage</b>\r | |
| 2649 | @code\r | |
| 2650 | UINT64 Msr;\r | |
| 2651 | \r | |
| 2652 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);\r | |
| 2653 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);\r | |
| 2654 | @endcode\r | |
| fed6c37b | 2655 | @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
2656 | **/\r |
| 2657 | #define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9\r | |
| 2658 | \r | |
| 2659 | \r | |
| 2660 | /**\r | |
| 2661 | Package. Uncore C-box 13 perfmon box wide filter1.\r | |
| 2662 | \r | |
| 2663 | @param ECX MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)\r | |
| 2664 | @param EAX Lower 32-bits of MSR value.\r | |
| 2665 | @param EDX Upper 32-bits of MSR value.\r | |
| 2666 | \r | |
| 2667 | <b>Example usage</b>\r | |
| 2668 | @code\r | |
| 2669 | UINT64 Msr;\r | |
| 2670 | \r | |
| 2671 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);\r | |
| 2672 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);\r | |
| 2673 | @endcode\r | |
| fed6c37b | 2674 | @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
2675 | **/\r |
| 2676 | #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA\r | |
| 2677 | \r | |
| 2678 | \r | |
| 2679 | /**\r | |
| 2680 | Package. Uncore C-box 14 perfmon local box wide control.\r | |
| 2681 | \r | |
| 2682 | @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)\r | |
| 2683 | @param EAX Lower 32-bits of MSR value.\r | |
| 2684 | @param EDX Upper 32-bits of MSR value.\r | |
| 2685 | \r | |
| 2686 | <b>Example usage</b>\r | |
| 2687 | @code\r | |
| 2688 | UINT64 Msr;\r | |
| 2689 | \r | |
| 2690 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);\r | |
| 2691 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);\r | |
| 2692 | @endcode\r | |
| fed6c37b | 2693 | @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r |
| 84ada87c MK |
2694 | **/\r |
| 2695 | #define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4\r | |
| 2696 | \r | |
| 2697 | \r | |
| 2698 | /**\r | |
| 2699 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.\r | |
| 2700 | \r | |
| 2701 | @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)\r | |
| 2702 | @param EAX Lower 32-bits of MSR value.\r | |
| 2703 | @param EDX Upper 32-bits of MSR value.\r | |
| 2704 | \r | |
| 2705 | <b>Example usage</b>\r | |
| 2706 | @code\r | |
| 2707 | UINT64 Msr;\r | |
| 2708 | \r | |
| 2709 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);\r | |
| 2710 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);\r | |
| 2711 | @endcode\r | |
| fed6c37b | 2712 | @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r |
| 84ada87c MK |
2713 | **/\r |
| 2714 | #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0\r | |
| 2715 | \r | |
| 2716 | \r | |
| 2717 | /**\r | |
| 2718 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.\r | |
| 2719 | \r | |
| 2720 | @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)\r | |
| 2721 | @param EAX Lower 32-bits of MSR value.\r | |
| 2722 | @param EDX Upper 32-bits of MSR value.\r | |
| 2723 | \r | |
| 2724 | <b>Example usage</b>\r | |
| 2725 | @code\r | |
| 2726 | UINT64 Msr;\r | |
| 2727 | \r | |
| 2728 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);\r | |
| 2729 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);\r | |
| 2730 | @endcode\r | |
| fed6c37b | 2731 | @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r |
| 84ada87c MK |
2732 | **/\r |
| 2733 | #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1\r | |
| 2734 | \r | |
| 2735 | \r | |
| 2736 | /**\r | |
| 2737 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.\r | |
| 2738 | \r | |
| 2739 | @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)\r | |
| 2740 | @param EAX Lower 32-bits of MSR value.\r | |
| 2741 | @param EDX Upper 32-bits of MSR value.\r | |
| 2742 | \r | |
| 2743 | <b>Example usage</b>\r | |
| 2744 | @code\r | |
| 2745 | UINT64 Msr;\r | |
| 2746 | \r | |
| 2747 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);\r | |
| 2748 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);\r | |
| 2749 | @endcode\r | |
| fed6c37b | 2750 | @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r |
| 84ada87c MK |
2751 | **/\r |
| 2752 | #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2\r | |
| 2753 | \r | |
| 2754 | \r | |
| 2755 | /**\r | |
| 2756 | Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.\r | |
| 2757 | \r | |
| 2758 | @param ECX MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)\r | |
| 2759 | @param EAX Lower 32-bits of MSR value.\r | |
| 2760 | @param EDX Upper 32-bits of MSR value.\r | |
| 2761 | \r | |
| 2762 | <b>Example usage</b>\r | |
| 2763 | @code\r | |
| 2764 | UINT64 Msr;\r | |
| 2765 | \r | |
| 2766 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);\r | |
| 2767 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);\r | |
| 2768 | @endcode\r | |
| fed6c37b | 2769 | @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r |
| 84ada87c MK |
2770 | **/\r |
| 2771 | #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3\r | |
| 2772 | \r | |
| 2773 | \r | |
| 2774 | /**\r | |
| 2775 | Package. Uncore C-box 14 perfmon box wide filter.\r | |
| 2776 | \r | |
| 2777 | @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)\r | |
| 2778 | @param EAX Lower 32-bits of MSR value.\r | |
| 2779 | @param EDX Upper 32-bits of MSR value.\r | |
| 2780 | \r | |
| 2781 | <b>Example usage</b>\r | |
| 2782 | @code\r | |
| 2783 | UINT64 Msr;\r | |
| 2784 | \r | |
| 2785 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);\r | |
| 2786 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);\r | |
| 2787 | @endcode\r | |
| fed6c37b | 2788 | @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r |
| 84ada87c MK |
2789 | **/\r |
| 2790 | #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4\r | |
| 2791 | \r | |
| 2792 | \r | |
| 2793 | /**\r | |
| 2794 | Package. Uncore C-box 14 perfmon counter 0.\r | |
| 2795 | \r | |
| 2796 | @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)\r | |
| 2797 | @param EAX Lower 32-bits of MSR value.\r | |
| 2798 | @param EDX Upper 32-bits of MSR value.\r | |
| 2799 | \r | |
| 2800 | <b>Example usage</b>\r | |
| 2801 | @code\r | |
| 2802 | UINT64 Msr;\r | |
| 2803 | \r | |
| 2804 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);\r | |
| 2805 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);\r | |
| 2806 | @endcode\r | |
| fed6c37b | 2807 | @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r |
| 84ada87c MK |
2808 | **/\r |
| 2809 | #define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6\r | |
| 2810 | \r | |
| 2811 | \r | |
| 2812 | /**\r | |
| 2813 | Package. Uncore C-box 14 perfmon counter 1.\r | |
| 2814 | \r | |
| 2815 | @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)\r | |
| 2816 | @param EAX Lower 32-bits of MSR value.\r | |
| 2817 | @param EDX Upper 32-bits of MSR value.\r | |
| 2818 | \r | |
| 2819 | <b>Example usage</b>\r | |
| 2820 | @code\r | |
| 2821 | UINT64 Msr;\r | |
| 2822 | \r | |
| 2823 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);\r | |
| 2824 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);\r | |
| 2825 | @endcode\r | |
| fed6c37b | 2826 | @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r |
| 84ada87c MK |
2827 | **/\r |
| 2828 | #define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7\r | |
| 2829 | \r | |
| 2830 | \r | |
| 2831 | /**\r | |
| 2832 | Package. Uncore C-box 14 perfmon counter 2.\r | |
| 2833 | \r | |
| 2834 | @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)\r | |
| 2835 | @param EAX Lower 32-bits of MSR value.\r | |
| 2836 | @param EDX Upper 32-bits of MSR value.\r | |
| 2837 | \r | |
| 2838 | <b>Example usage</b>\r | |
| 2839 | @code\r | |
| 2840 | UINT64 Msr;\r | |
| 2841 | \r | |
| 2842 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);\r | |
| 2843 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);\r | |
| 2844 | @endcode\r | |
| fed6c37b | 2845 | @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r |
| 84ada87c MK |
2846 | **/\r |
| 2847 | #define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8\r | |
| 2848 | \r | |
| 2849 | \r | |
| 2850 | /**\r | |
| 2851 | Package. Uncore C-box 14 perfmon counter 3.\r | |
| 2852 | \r | |
| 2853 | @param ECX MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)\r | |
| 2854 | @param EAX Lower 32-bits of MSR value.\r | |
| 2855 | @param EDX Upper 32-bits of MSR value.\r | |
| 2856 | \r | |
| 2857 | <b>Example usage</b>\r | |
| 2858 | @code\r | |
| 2859 | UINT64 Msr;\r | |
| 2860 | \r | |
| 2861 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);\r | |
| 2862 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);\r | |
| 2863 | @endcode\r | |
| fed6c37b | 2864 | @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r |
| 84ada87c MK |
2865 | **/\r |
| 2866 | #define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9\r | |
| 2867 | \r | |
| 2868 | \r | |
| 2869 | /**\r | |
| 2870 | Package. Uncore C-box 14 perfmon box wide filter1.\r | |
| 2871 | \r | |
| 2872 | @param ECX MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)\r | |
| 2873 | @param EAX Lower 32-bits of MSR value.\r | |
| 2874 | @param EDX Upper 32-bits of MSR value.\r | |
| 2875 | \r | |
| 2876 | <b>Example usage</b>\r | |
| 2877 | @code\r | |
| 2878 | UINT64 Msr;\r | |
| 2879 | \r | |
| 2880 | Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);\r | |
| 2881 | AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);\r | |
| 2882 | @endcode\r | |
| fed6c37b | 2883 | @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r |
| 84ada87c MK |
2884 | **/\r |
| 2885 | #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA\r | |
| 2886 | \r | |
| 2887 | #endif\r |