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1/** @file\r
2 Common header file for MP Initialize Library.\r
3\r
8c61f193 4 Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>\r
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5 Copyright (c) 2020, AMD Inc. All rights reserved.<BR>\r
6\r
0acd8697 7 SPDX-License-Identifier: BSD-2-Clause-Patent\r
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8\r
9**/\r
10\r
11#ifndef _MP_LIB_H_\r
12#define _MP_LIB_H_\r
13\r
14#include <PiPei.h>\r
15\r
01acb06c 16#include <Register/Intel/Cpuid.h>\r
4c0f6e34 17#include <Register/Amd/Cpuid.h>\r
01acb06c
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18#include <Register/Intel/Msr.h>\r
19#include <Register/Intel/LocalApic.h>\r
20#include <Register/Intel/Microcode.h>\r
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21\r
22#include <Library/MpInitLib.h>\r
23#include <Library/BaseLib.h>\r
24#include <Library/BaseMemoryLib.h>\r
25#include <Library/MemoryAllocationLib.h>\r
26#include <Library/DebugLib.h>\r
27#include <Library/LocalApicLib.h>\r
28#include <Library/CpuLib.h>\r
29#include <Library/UefiCpuLib.h>\r
30#include <Library/TimerLib.h>\r
31#include <Library/SynchronizationLib.h>\r
32#include <Library/MtrrLib.h>\r
33#include <Library/HobLib.h>\r
d5339c04 34#include <Library/PcdLib.h>\r
bce03284 35#include <Library/MicrocodeLib.h>\r
b95908e0 36#include <ConfidentialComputingGuestAttr.h>\r
3e8ad6bd 37\r
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38#include <Register/Amd/Fam17Msr.h>\r
39#include <Register/Amd/Ghcb.h>\r
40\r
348a34d9
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41#include <Guid/MicrocodePatchHob.h>\r
42\r
053e878b 43#define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P')\r
b8b04307 44\r
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45#define CPU_INIT_MP_LIB_HOB_GUID \\r
46 { \\r
47 0x58eb6a19, 0x3699, 0x4c68, { 0xa8, 0x36, 0xda, 0xcd, 0x8e, 0xdc, 0xad, 0x4a } \\r
48 }\r
49\r
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50//\r
51// The MP data for switch BSP\r
52//\r
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53#define CPU_SWITCH_STATE_IDLE 0\r
54#define CPU_SWITCH_STATE_STORED 1\r
55#define CPU_SWITCH_STATE_LOADED 2\r
41be0da5 56\r
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57//\r
58// Default maximum number of entries to store the microcode patches information\r
59//\r
053e878b 60#define DEFAULT_MAX_MICROCODE_PATCH_NUM 8\r
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61\r
62//\r
63// Data structure for microcode patch information\r
64//\r
65typedef struct {\r
66 UINTN Address;\r
67 UINTN Size;\r
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68} MICROCODE_PATCH_INFO;\r
69\r
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70//\r
71// CPU exchange information for switch BSP\r
72//\r
73typedef struct {\r
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74 UINT8 State; // offset 0\r
75 UINTN StackPointer; // offset 4 / 8\r
76 IA32_DESCRIPTOR Gdtr; // offset 8 / 16\r
77 IA32_DESCRIPTOR Idtr; // offset 14 / 26\r
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78} CPU_EXCHANGE_ROLE_INFO;\r
79\r
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80//\r
81// AP loop state when APs are in idle state\r
82// It's value is the same with PcdCpuApLoopMode\r
83//\r
84typedef enum {\r
85 ApInHltLoop = 1,\r
86 ApInMwaitLoop = 2,\r
87 ApInRunLoop = 3\r
88} AP_LOOP_MODE;\r
89\r
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90//\r
91// AP initialization state during APs wakeup\r
92//\r
93typedef enum {\r
94 ApInitConfig = 1,\r
95 ApInitReconfig = 2,\r
96 ApInitDone = 3\r
97} AP_INIT_STATE;\r
98\r
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99//\r
100// AP state\r
101//\r
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102// The state transitions for an AP when it process a procedure are:\r
103// Idle ----> Ready ----> Busy ----> Idle\r
104// [BSP] [AP] [AP]\r
105//\r
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106typedef enum {\r
107 CpuStateIdle,\r
108 CpuStateReady,\r
109 CpuStateBusy,\r
e048ce88 110 CpuStateFinished,\r
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111 CpuStateDisabled\r
112} CPU_STATE;\r
113\r
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114//\r
115// CPU volatile registers around INIT-SIPI-SIPI\r
116//\r
117typedef struct {\r
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118 UINTN Cr0;\r
119 UINTN Cr3;\r
120 UINTN Cr4;\r
121 UINTN Dr0;\r
122 UINTN Dr1;\r
123 UINTN Dr2;\r
124 UINTN Dr3;\r
125 UINTN Dr6;\r
126 UINTN Dr7;\r
127 IA32_DESCRIPTOR Gdtr;\r
128 IA32_DESCRIPTOR Idtr;\r
129 UINT16 Tr;\r
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130} CPU_VOLATILE_REGISTERS;\r
131\r
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132//\r
133// AP related data\r
134//\r
135typedef struct {\r
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136 SPIN_LOCK ApLock;\r
137 volatile UINT32 *StartupApSignal;\r
138 volatile UINTN ApFunction;\r
139 volatile UINTN ApFunctionArgument;\r
140 BOOLEAN CpuHealthy;\r
141 volatile CPU_STATE State;\r
142 CPU_VOLATILE_REGISTERS VolatileRegisters;\r
143 BOOLEAN Waiting;\r
144 BOOLEAN *Finished;\r
145 UINT64 ExpectedTime;\r
146 UINT64 CurrentTime;\r
147 UINT64 TotalTime;\r
148 EFI_EVENT WaitEvent;\r
149 UINT32 ProcessorSignature;\r
150 UINT8 PlatformId;\r
151 UINT64 MicrocodeEntryAddr;\r
152 UINT32 MicrocodeRevision;\r
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153} CPU_AP_DATA;\r
154\r
155//\r
156// Basic CPU information saved in Guided HOB.\r
157// Because the contents will be shard between PEI and DXE,\r
158// we need to make sure the each fields offset same in different\r
159// architecture.\r
160//\r
dd3fa0cd 161#pragma pack (1)\r
e59f8f6b 162typedef struct {\r
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163 UINT32 InitialApicId;\r
164 UINT32 ApicId;\r
165 UINT32 Health;\r
166 UINT64 ApTopOfStack;\r
e59f8f6b 167} CPU_INFO_IN_HOB;\r
dd3fa0cd 168#pragma pack ()\r
e59f8f6b 169\r
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170//\r
171// AP reset code information including code address and size,\r
172// this structure will be shared be C code and assembly code.\r
173// It is natural aligned by design.\r
174//\r
175typedef struct {\r
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176 UINT8 *RendezvousFunnelAddress;\r
177 UINTN ModeEntryOffset;\r
178 UINTN RendezvousFunnelSize;\r
179 UINT8 *RelocateApLoopFuncAddress;\r
180 UINTN RelocateApLoopFuncSize;\r
181 UINTN ModeTransitionOffset;\r
182 UINTN SwitchToRealSize;\r
183 UINTN SwitchToRealOffset;\r
184 UINTN SwitchToRealNoNxOffset;\r
185 UINTN SwitchToRealPM16ModeOffset;\r
186 UINTN SwitchToRealPM16ModeSize;\r
f7f85d83 187} MP_ASSEMBLY_ADDRESS_MAP;\r
3e8ad6bd 188\r
053e878b 189typedef struct _CPU_MP_DATA CPU_MP_DATA;\r
e59f8f6b 190\r
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191#pragma pack(1)\r
192\r
193//\r
194// MP CPU exchange information for AP reset code\r
195// This structure is required to be packed because fixed field offsets\r
196// into this structure are used in assembly code in this module\r
197//\r
198typedef struct {\r
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199 UINTN StackStart;\r
200 UINTN StackSize;\r
201 UINTN CFunction;\r
202 IA32_DESCRIPTOR GdtrProfile;\r
203 IA32_DESCRIPTOR IdtrProfile;\r
204 UINTN BufferStart;\r
205 UINTN ModeOffset;\r
206 UINTN ApIndex;\r
207 UINTN CodeSegment;\r
208 UINTN DataSegment;\r
209 UINTN EnableExecuteDisable;\r
210 UINTN Cr3;\r
211 UINTN InitFlag;\r
212 CPU_INFO_IN_HOB *CpuInfo;\r
213 UINTN NumApsExecuting;\r
214 CPU_MP_DATA *CpuMpData;\r
215 UINTN InitializeFloatingPointUnitsAddress;\r
216 UINT32 ModeTransitionMemory;\r
217 UINT16 ModeTransitionSegment;\r
218 UINT32 ModeHighMemory;\r
219 UINT16 ModeHighSegment;\r
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220 //\r
221 // Enable5LevelPaging indicates whether 5-level paging is enabled in long mode.\r
222 //\r
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223 BOOLEAN Enable5LevelPaging;\r
224 BOOLEAN SevEsIsEnabled;\r
225 UINTN GhcbBase;\r
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226} MP_CPU_EXCHANGE_INFO;\r
227\r
228#pragma pack()\r
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229\r
230//\r
231// CPU MP Data save in memory\r
232//\r
233struct _CPU_MP_DATA {\r
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234 UINT64 CpuInfoInHob;\r
235 UINT32 CpuCount;\r
236 UINT32 BspNumber;\r
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237 //\r
238 // The above fields data will be passed from PEI to DXE\r
239 // Please make sure the fields offset same in the different\r
240 // architecture.\r
241 //\r
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242 SPIN_LOCK MpLock;\r
243 UINTN Buffer;\r
244 UINTN CpuApStackSize;\r
245 MP_ASSEMBLY_ADDRESS_MAP AddressMap;\r
246 UINTN WakeupBuffer;\r
247 UINTN WakeupBufferHigh;\r
248 UINTN BackupBuffer;\r
249 UINTN BackupBufferSize;\r
250\r
251 volatile UINT32 FinishedCount;\r
252 UINT32 RunningCount;\r
253 BOOLEAN SingleThread;\r
254 EFI_AP_PROCEDURE Procedure;\r
255 VOID *ProcArguments;\r
256 BOOLEAN *Finished;\r
257 UINT64 ExpectedTime;\r
258 UINT64 CurrentTime;\r
259 UINT64 TotalTime;\r
260 EFI_EVENT WaitEvent;\r
261 UINTN **FailedCpuList;\r
262\r
263 AP_INIT_STATE InitFlag;\r
264 BOOLEAN SwitchBspFlag;\r
265 UINTN NewBspNumber;\r
266 CPU_EXCHANGE_ROLE_INFO BSPInfo;\r
267 CPU_EXCHANGE_ROLE_INFO APInfo;\r
268 MTRR_SETTINGS MtrrTable;\r
269 UINT8 ApLoopMode;\r
270 UINT8 ApTargetCState;\r
271 UINT16 PmCodeSegment;\r
272 UINT16 Pm16CodeSegment;\r
273 CPU_AP_DATA *CpuData;\r
274 volatile MP_CPU_EXCHANGE_INFO *MpCpuExchangeInfo;\r
275\r
276 UINT32 CurrentTimerCount;\r
277 UINTN DivideValue;\r
278 UINT8 Vector;\r
279 BOOLEAN PeriodicMode;\r
280 BOOLEAN TimerInterruptState;\r
281 UINT64 MicrocodePatchAddress;\r
282 UINT64 MicrocodePatchRegionSize;\r
2a089134 283\r
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284 //\r
285 // Whether need to use Init-Sipi-Sipi to wake up the APs.\r
286 // Two cases need to set this value to TRUE. One is in HLT\r
287 // loop mode, the other is resume from S3 which loop mode\r
e23d9c3e 288 // will be hardcode change to HLT mode by PiSmmCpuDxeSmm\r
58942277
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289 // driver.\r
290 //\r
053e878b 291 BOOLEAN WakeUpByInitSipiSipi;\r
e88a5b98 292\r
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293 BOOLEAN SevEsIsEnabled;\r
294 UINTN SevEsAPBuffer;\r
295 UINTN SevEsAPResetStackStart;\r
296 CPU_MP_DATA *NewCpuMpData;\r
7b7508ad 297\r
053e878b 298 UINT64 GhcbBase;\r
e59f8f6b 299};\r
93ca4c0f 300\r
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301#define AP_SAFE_STACK_SIZE 128\r
302#define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE\r
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303\r
304#pragma pack(1)\r
305\r
306typedef struct {\r
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307 UINT8 InsnBuffer[8];\r
308 UINT16 Rip;\r
309 UINT16 Segment;\r
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310} SEV_ES_AP_JMP_FAR;\r
311\r
312#pragma pack()\r
313\r
314/**\r
315 Assembly code to move an AP from long mode to real mode.\r
316\r
317 Move an AP from long mode to real mode in preparation to invoking\r
318 the reset vector. This is used for SEV-ES guests where a hypervisor\r
319 is not allowed to set the CS and RIP to point to the reset vector.\r
320\r
321 @param[in] BufferStart The reset vector target.\r
322 @param[in] Code16 16-bit protected mode code segment value.\r
323 @param[in] Code32 32-bit protected mode code segment value.\r
324 @param[in] StackStart The start of a stack to be used for transitioning\r
325 from long mode to real mode.\r
326**/\r
327typedef\r
e2289d19 328 VOID\r
053e878b 329(EFIAPI AP_RESET)(\r
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330 IN UINTN BufferStart,\r
331 IN UINT16 Code16,\r
332 IN UINT16 Code32,\r
333 IN UINTN StackStart\r
334 );\r
335\r
053e878b 336extern EFI_GUID mCpuInitMpLibHobGuid;\r
93ca4c0f 337\r
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338/**\r
339 Assembly code to place AP into safe loop mode.\r
340\r
341 Place AP into targeted C-State if MONITOR is supported, otherwise\r
342 place AP into hlt state.\r
343 Place AP in protected mode if the current is long mode. Due to AP maybe\r
344 wakeup by some hardware event. It could avoid accessing page table that\r
345 may not available during booting to OS.\r
346\r
347 @param[in] MwaitSupport TRUE indicates MONITOR is supported.\r
348 FALSE indicates MONITOR is not supported.\r
349 @param[in] ApTargetCState Target C-State value.\r
350 @param[in] PmCodeSegment Protected mode code segment value.\r
351**/\r
352typedef\r
e2289d19 353 VOID\r
053e878b 354(EFIAPI *ASM_RELOCATE_AP_LOOP)(\r
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355 IN BOOLEAN MwaitSupport,\r
356 IN UINTN ApTargetCState,\r
bf2786dc 357 IN UINTN PmCodeSegment,\r
9f91cb01 358 IN UINTN TopOfApStack,\r
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TL
359 IN UINTN NumberToFinish,\r
360 IN UINTN Pm16CodeSegment,\r
361 IN UINTN SevEsAPJumpTable,\r
362 IN UINTN WakeupBuffer\r
76157021 363 );\r
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364\r
365/**\r
366 Assembly code to get starting address and size of the rendezvous entry for APs.\r
367 Information for fixing a jump instruction in the code is also returned.\r
368\r
369 @param[out] AddressMap Output buffer for address map information.\r
370**/\r
371VOID\r
372EFIAPI\r
373AsmGetAddressMap (\r
053e878b 374 OUT MP_ASSEMBLY_ADDRESS_MAP *AddressMap\r
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375 );\r
376\r
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377/**\r
378 This function is called by both the BSP and the AP which is to become the BSP to\r
379 Exchange execution context including stack between them. After return from this\r
380 function, the BSP becomes AP and the AP becomes the BSP.\r
381\r
382 @param[in] MyInfo Pointer to buffer holding the exchanging information for the executing processor.\r
383 @param[in] OthersInfo Pointer to buffer holding the exchanging information for the peer.\r
384\r
385**/\r
386VOID\r
387EFIAPI\r
388AsmExchangeRole (\r
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389 IN CPU_EXCHANGE_ROLE_INFO *MyInfo,\r
390 IN CPU_EXCHANGE_ROLE_INFO *OthersInfo\r
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391 );\r
392\r
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393/**\r
394 Get the pointer to CPU MP Data structure.\r
395\r
396 @return The pointer to CPU MP Data structure.\r
397**/\r
398CPU_MP_DATA *\r
399GetCpuMpData (\r
400 VOID\r
401 );\r
402\r
403/**\r
404 Save the pointer to CPU MP Data structure.\r
405\r
406 @param[in] CpuMpData The pointer to CPU MP Data structure will be saved.\r
407**/\r
408VOID\r
409SaveCpuMpData (\r
053e878b 410 IN CPU_MP_DATA *CpuMpData\r
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411 );\r
412\r
ed66e0e3 413/**\r
a6b3d753 414 Get available system memory below 1MB by specified size.\r
ed66e0e3 415\r
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SZ
416 @param[in] WakeupBufferSize Wakeup buffer size required\r
417\r
418 @retval other Return wakeup buffer address below 1MB.\r
419 @retval -1 Cannot find free memory below 1MB.\r
ed66e0e3 420**/\r
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SZ
421UINTN\r
422GetWakeupBuffer (\r
053e878b 423 IN UINTN WakeupBufferSize\r
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424 );\r
425\r
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426/**\r
427 Get available EfiBootServicesCode memory below 4GB by specified size.\r
428\r
429 This buffer is required to safely transfer AP from real address mode to\r
430 protected mode or long mode, due to the fact that the buffer returned by\r
431 GetWakeupBuffer() may be marked as non-executable.\r
432\r
433 @param[in] BufferSize Wakeup transition buffer size.\r
434\r
435 @retval other Return wakeup transition buffer address below 4GB.\r
436 @retval 0 Cannot find free memory below 4GB.\r
437**/\r
438UINTN\r
439GetModeTransitionBuffer (\r
053e878b 440 IN UINTN BufferSize\r
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441 );\r
442\r
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443/**\r
444 Return the address of the SEV-ES AP jump table.\r
445\r
446 This buffer is required in order for an SEV-ES guest to transition from\r
447 UEFI into an OS.\r
448\r
449 @return Return SEV-ES AP jump table buffer\r
450**/\r
451UINTN\r
452GetSevEsAPMemory (\r
453 VOID\r
454 );\r
455\r
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456/**\r
457 This function will be called by BSP to wakeup AP.\r
458\r
459 @param[in] CpuMpData Pointer to CPU MP Data\r
460 @param[in] Broadcast TRUE: Send broadcast IPI to all APs\r
461 FALSE: Send IPI to AP by ApicId\r
462 @param[in] ProcessorNumber The handle number of specified processor\r
463 @param[in] Procedure The function to be invoked by AP\r
464 @param[in] ProcedureArgument The argument to be passed into AP function\r
cf4e79e4 465 @param[in] WakeUpDisabledAps Whether need to wake up disabled APs in broadcast mode.\r
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466**/\r
467VOID\r
468WakeUpAP (\r
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469 IN CPU_MP_DATA *CpuMpData,\r
470 IN BOOLEAN Broadcast,\r
471 IN UINTN ProcessorNumber,\r
472 IN EFI_AP_PROCEDURE Procedure OPTIONAL,\r
473 IN VOID *ProcedureArgument OPTIONAL,\r
474 IN BOOLEAN WakeUpDisabledAps OPTIONAL\r
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475 );\r
476\r
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477/**\r
478 Initialize global data for MP support.\r
479\r
480 @param[in] CpuMpData The pointer to CPU MP Data structure.\r
481**/\r
482VOID\r
483InitMpGlobalData (\r
053e878b 484 IN CPU_MP_DATA *CpuMpData\r
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485 );\r
486\r
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487/**\r
488 Worker function to execute a caller provided function on all enabled APs.\r
489\r
490 @param[in] Procedure A pointer to the function to be run on\r
491 enabled APs of the system.\r
492 @param[in] SingleThread If TRUE, then all the enabled APs execute\r
493 the function specified by Procedure one by\r
494 one, in ascending order of processor handle\r
495 number. If FALSE, then all the enabled APs\r
496 execute the function specified by Procedure\r
497 simultaneously.\r
ee0c39fa 498 @param[in] ExcludeBsp Whether let BSP also trig this task.\r
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499 @param[in] WaitEvent The event created by the caller with CreateEvent()\r
500 service.\r
367284e7 501 @param[in] TimeoutInMicroseconds Indicates the time limit in microseconds for\r
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502 APs to return from Procedure, either for\r
503 blocking or non-blocking mode.\r
504 @param[in] ProcedureArgument The parameter passed into Procedure for\r
505 all APs.\r
506 @param[out] FailedCpuList If all APs finish successfully, then its\r
507 content is set to NULL. If not all APs\r
508 finish before timeout expires, then its\r
509 content is set to address of the buffer\r
510 holding handle numbers of the failed APs.\r
511\r
512 @retval EFI_SUCCESS In blocking mode, all APs have finished before\r
513 the timeout expired.\r
514 @retval EFI_SUCCESS In non-blocking mode, function has been dispatched\r
515 to all enabled APs.\r
516 @retval others Failed to Startup all APs.\r
517\r
518**/\r
519EFI_STATUS\r
ee0c39fa 520StartupAllCPUsWorker (\r
053e878b
MK
521 IN EFI_AP_PROCEDURE Procedure,\r
522 IN BOOLEAN SingleThread,\r
523 IN BOOLEAN ExcludeBsp,\r
524 IN EFI_EVENT WaitEvent OPTIONAL,\r
525 IN UINTN TimeoutInMicroseconds,\r
526 IN VOID *ProcedureArgument OPTIONAL,\r
527 OUT UINTN **FailedCpuList OPTIONAL\r
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528 );\r
529\r
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530/**\r
531 Worker function to let the caller get one enabled AP to execute a caller-provided\r
532 function.\r
533\r
534 @param[in] Procedure A pointer to the function to be run on\r
535 enabled APs of the system.\r
536 @param[in] ProcessorNumber The handle number of the AP.\r
537 @param[in] WaitEvent The event created by the caller with CreateEvent()\r
538 service.\r
367284e7 539 @param[in] TimeoutInMicroseconds Indicates the time limit in microseconds for\r
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540 APs to return from Procedure, either for\r
541 blocking or non-blocking mode.\r
542 @param[in] ProcedureArgument The parameter passed into Procedure for\r
543 all APs.\r
544 @param[out] Finished If AP returns from Procedure before the\r
545 timeout expires, its content is set to TRUE.\r
546 Otherwise, the value is set to FALSE.\r
547\r
548 @retval EFI_SUCCESS In blocking mode, specified AP finished before\r
549 the timeout expires.\r
550 @retval others Failed to Startup AP.\r
551\r
552**/\r
553EFI_STATUS\r
554StartupThisAPWorker (\r
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MK
555 IN EFI_AP_PROCEDURE Procedure,\r
556 IN UINTN ProcessorNumber,\r
557 IN EFI_EVENT WaitEvent OPTIONAL,\r
558 IN UINTN TimeoutInMicroseconds,\r
559 IN VOID *ProcedureArgument OPTIONAL,\r
560 OUT BOOLEAN *Finished OPTIONAL\r
20ae5774
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561 );\r
562\r
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563/**\r
564 Worker function to switch the requested AP to be the BSP from that point onward.\r
565\r
566 @param[in] ProcessorNumber The handle number of AP that is to become the new BSP.\r
567 @param[in] EnableOldBSP If TRUE, then the old BSP will be listed as an\r
568 enabled AP. Otherwise, it will be disabled.\r
569\r
570 @retval EFI_SUCCESS BSP successfully switched.\r
7367cc6c 571 @retval others Failed to switch BSP.\r
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572\r
573**/\r
574EFI_STATUS\r
575SwitchBSPWorker (\r
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576 IN UINTN ProcessorNumber,\r
577 IN BOOLEAN EnableOldBSP\r
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578 );\r
579\r
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580/**\r
581 Worker function to let the caller enable or disable an AP from this point onward.\r
582 This service may only be called from the BSP.\r
583\r
584 @param[in] ProcessorNumber The handle number of AP.\r
585 @param[in] EnableAP Specifies the new state for the processor for\r
586 enabled, FALSE for disabled.\r
587 @param[in] HealthFlag If not NULL, a pointer to a value that specifies\r
588 the new health status of the AP.\r
589\r
590 @retval EFI_SUCCESS The specified AP was enabled or disabled successfully.\r
591 @retval others Failed to Enable/Disable AP.\r
592\r
593**/\r
594EFI_STATUS\r
595EnableDisableApWorker (\r
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MK
596 IN UINTN ProcessorNumber,\r
597 IN BOOLEAN EnableAP,\r
598 IN UINT32 *HealthFlag OPTIONAL\r
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JF
599 );\r
600\r
93ca4c0f
JF
601/**\r
602 Get pointer to CPU MP Data structure from GUIDed HOB.\r
603\r
604 @return The pointer to CPU MP Data structure.\r
605**/\r
606CPU_MP_DATA *\r
607GetCpuMpDataFromGuidedHob (\r
608 VOID\r
609 );\r
08085f08
JF
610\r
611/** Checks status of specified AP.\r
612\r
613 This function checks whether the specified AP has finished the task assigned\r
614 by StartupThisAP(), and whether timeout expires.\r
615\r
616 @param[in] ProcessorNumber The handle number of processor.\r
617\r
618 @retval EFI_SUCCESS Specified AP has finished task assigned by StartupThisAPs().\r
619 @retval EFI_TIMEOUT The timeout expires.\r
620 @retval EFI_NOT_READY Specified AP has not finished task and timeout has not expired.\r
621**/\r
622EFI_STATUS\r
623CheckThisAP (\r
053e878b 624 IN UINTN ProcessorNumber\r
08085f08
JF
625 );\r
626\r
627/**\r
628 Checks status of all APs.\r
629\r
630 This function checks whether all APs have finished task assigned by StartupAllAPs(),\r
631 and whether timeout expires.\r
632\r
633 @retval EFI_SUCCESS All APs have finished task assigned by StartupAllAPs().\r
634 @retval EFI_TIMEOUT The timeout expires.\r
635 @retval EFI_NOT_READY APs have not finished task and timeout has not expired.\r
636**/\r
637EFI_STATUS\r
638CheckAllAPs (\r
639 VOID\r
640 );\r
641\r
642/**\r
643 Checks APs status and updates APs status if needed.\r
644\r
645**/\r
646VOID\r
647CheckAndUpdateApsStatus (\r
648 VOID\r
649 );\r
650\r
94f63c76
JF
651/**\r
652 Detect whether specified processor can find matching microcode patch and load it.\r
653\r
e1ed5573
HW
654 @param[in] CpuMpData The pointer to CPU MP Data structure.\r
655 @param[in] ProcessorNumber The handle number of the processor. The range is\r
656 from 0 to the total number of logical processors\r
657 minus 1.\r
94f63c76
JF
658**/\r
659VOID\r
660MicrocodeDetect (\r
053e878b
MK
661 IN CPU_MP_DATA *CpuMpData,\r
662 IN UINTN ProcessorNumber\r
94f63c76
JF
663 );\r
664\r
d786a172 665/**\r
dd017041 666 Shadow the required microcode patches data into memory.\r
d786a172
HW
667\r
668 @param[in, out] CpuMpData The pointer to CPU MP Data structure.\r
669**/\r
670VOID\r
dd017041 671ShadowMicrocodeUpdatePatch (\r
053e878b 672 IN OUT CPU_MP_DATA *CpuMpData\r
d786a172
HW
673 );\r
674\r
348a34d9
HW
675/**\r
676 Get the cached microcode patch base address and size from the microcode patch\r
677 information cache HOB.\r
678\r
679 @param[out] Address Base address of the microcode patches data.\r
680 It will be updated if the microcode patch\r
681 information cache HOB is found.\r
682 @param[out] RegionSize Size of the microcode patches data.\r
683 It will be updated if the microcode patch\r
684 information cache HOB is found.\r
685\r
686 @retval TRUE The microcode patch information cache HOB is found.\r
687 @retval FALSE The microcode patch information cache HOB is not found.\r
688\r
689**/\r
690BOOLEAN\r
691GetMicrocodePatchInfoFromHob (\r
053e878b
MK
692 UINT64 *Address,\r
693 UINT64 *RegionSize\r
348a34d9
HW
694 );\r
695\r
4d3314f6
JF
696/**\r
697 Detect whether Mwait-monitor feature is supported.\r
698\r
699 @retval TRUE Mwait-monitor feature is supported.\r
700 @retval FALSE Mwait-monitor feature is not supported.\r
701**/\r
702BOOLEAN\r
703IsMwaitSupport (\r
704 VOID\r
705 );\r
706\r
43c9fdcc
JF
707/**\r
708 Enable Debug Agent to support source debugging on AP function.\r
709\r
710**/\r
711VOID\r
712EnableDebugAgent (\r
713 VOID\r
714 );\r
715\r
e1ed5573
HW
716/**\r
717 Find the current Processor number by APIC ID.\r
718\r
719 @param[in] CpuMpData Pointer to PEI CPU MP Data\r
720 @param[out] ProcessorNumber Return the pocessor number found\r
721\r
722 @retval EFI_SUCCESS ProcessorNumber is found and returned.\r
723 @retval EFI_NOT_FOUND ProcessorNumber is not found.\r
724**/\r
725EFI_STATUS\r
726GetProcessorNumber (\r
053e878b
MK
727 IN CPU_MP_DATA *CpuMpData,\r
728 OUT UINTN *ProcessorNumber\r
e1ed5573
HW
729 );\r
730\r
c788c2b1
SF
731/**\r
732 This funtion will try to invoke platform specific microcode shadow logic to\r
733 relocate microcode update patches into memory.\r
734\r
4ac82ea1 735 @param[in, out] CpuMpData The pointer to CPU MP Data structure.\r
c788c2b1
SF
736\r
737 @retval EFI_SUCCESS Shadow microcode success.\r
738 @retval EFI_OUT_OF_RESOURCES No enough resource to complete the operation.\r
739 @retval EFI_UNSUPPORTED Can't find platform specific microcode shadow\r
740 PPI/Protocol.\r
741**/\r
742EFI_STATUS\r
743PlatformShadowMicrocode (\r
053e878b 744 IN OUT CPU_MP_DATA *CpuMpData\r
c788c2b1
SF
745 );\r
746\r
e2289d19
BS
747/**\r
748 Allocate the SEV-ES AP jump table buffer.\r
749\r
750 @param[in, out] CpuMpData The pointer to CPU MP Data structure.\r
751**/\r
752VOID\r
753AllocateSevEsAPMemory (\r
754 IN OUT CPU_MP_DATA *CpuMpData\r
755 );\r
756\r
757/**\r
758 Program the SEV-ES AP jump table buffer.\r
759\r
760 @param[in] SipiVector The SIPI vector used for the AP Reset\r
761**/\r
762VOID\r
763SetSevEsJumpTable (\r
764 IN UINTN SipiVector\r
765 );\r
766\r
767/**\r
768 The function puts the AP in halt loop.\r
769\r
770 @param[in] CpuMpData The pointer to CPU MP Data structure.\r
771**/\r
772VOID\r
773SevEsPlaceApHlt (\r
774 CPU_MP_DATA *CpuMpData\r
775 );\r
776\r
b95908e0
BS
777/**\r
778 Check if the specified confidential computing attribute is active.\r
779\r
780 @retval TRUE The specified Attr is active.\r
781 @retval FALSE The specified Attr is not active.\r
782**/\r
783BOOLEAN\r
784EFIAPI\r
785ConfidentialComputingGuestHas (\r
786 CONFIDENTIAL_COMPUTING_GUEST_ATTR Attr\r
787 );\r
788\r
3e8ad6bd 789#endif\r