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529a5a86 MK |
1 | /** @file\r |
2 | Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r | |
3 | \r | |
e21e355e | 4 | Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r |
241f9149 LD |
5 | Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r |
6 | \r | |
529a5a86 MK |
7 | This program and the accompanying materials\r |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #include "PiSmmCpuDxeSmm.h"\r | |
18 | \r | |
19 | //\r | |
20 | // SMM CPU Private Data structure that contains SMM Configuration Protocol\r | |
21 | // along its supporting fields.\r | |
22 | //\r | |
23 | SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = {\r | |
24 | SMM_CPU_PRIVATE_DATA_SIGNATURE, // Signature\r | |
25 | NULL, // SmmCpuHandle\r | |
26 | NULL, // Pointer to ProcessorInfo array\r | |
27 | NULL, // Pointer to Operation array\r | |
28 | NULL, // Pointer to CpuSaveStateSize array\r | |
29 | NULL, // Pointer to CpuSaveState array\r | |
30 | { {0} }, // SmmReservedSmramRegion\r | |
31 | {\r | |
32 | SmmStartupThisAp, // SmmCoreEntryContext.SmmStartupThisAp\r | |
33 | 0, // SmmCoreEntryContext.CurrentlyExecutingCpu\r | |
34 | 0, // SmmCoreEntryContext.NumberOfCpus\r | |
35 | NULL, // SmmCoreEntryContext.CpuSaveStateSize\r | |
36 | NULL // SmmCoreEntryContext.CpuSaveState\r | |
37 | },\r | |
38 | NULL, // SmmCoreEntry\r | |
39 | {\r | |
40 | mSmmCpuPrivateData.SmmReservedSmramRegion, // SmmConfiguration.SmramReservedRegions\r | |
41 | RegisterSmmEntry // SmmConfiguration.RegisterSmmEntry\r | |
42 | },\r | |
43 | };\r | |
44 | \r | |
45 | CPU_HOT_PLUG_DATA mCpuHotPlugData = {\r | |
46 | CPU_HOT_PLUG_DATA_REVISION_1, // Revision\r | |
47 | 0, // Array Length of SmBase and APIC ID\r | |
48 | NULL, // Pointer to APIC ID array\r | |
49 | NULL, // Pointer to SMBASE array\r | |
50 | 0, // Reserved\r | |
51 | 0, // SmrrBase\r | |
52 | 0 // SmrrSize\r | |
53 | };\r | |
54 | \r | |
55 | //\r | |
56 | // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM\r | |
57 | //\r | |
58 | SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate = &mSmmCpuPrivateData;\r | |
59 | \r | |
60 | //\r | |
61 | // SMM Relocation variables\r | |
62 | //\r | |
63 | volatile BOOLEAN *mRebased;\r | |
64 | volatile BOOLEAN mIsBsp;\r | |
65 | \r | |
66 | ///\r | |
67 | /// Handle for the SMM CPU Protocol\r | |
68 | ///\r | |
69 | EFI_HANDLE mSmmCpuHandle = NULL;\r | |
70 | \r | |
71 | ///\r | |
72 | /// SMM CPU Protocol instance\r | |
73 | ///\r | |
74 | EFI_SMM_CPU_PROTOCOL mSmmCpu = {\r | |
75 | SmmReadSaveState,\r | |
76 | SmmWriteSaveState\r | |
77 | };\r | |
78 | \r | |
827330cc JW |
79 | ///\r |
80 | /// SMM Memory Attribute Protocol instance\r | |
81 | ///\r | |
82 | EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = {\r | |
83 | EdkiiSmmGetMemoryAttributes,\r | |
84 | EdkiiSmmSetMemoryAttributes,\r | |
85 | EdkiiSmmClearMemoryAttributes\r | |
86 | };\r | |
87 | \r | |
529a5a86 MK |
88 | EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];\r |
89 | \r | |
529a5a86 MK |
90 | //\r |
91 | // SMM stack information\r | |
92 | //\r | |
93 | UINTN mSmmStackArrayBase;\r | |
94 | UINTN mSmmStackArrayEnd;\r | |
95 | UINTN mSmmStackSize;\r | |
96 | \r | |
529a5a86 MK |
97 | UINTN mMaxNumberOfCpus = 1;\r |
98 | UINTN mNumberOfCpus = 1;\r | |
99 | \r | |
100 | //\r | |
101 | // SMM ready to lock flag\r | |
102 | //\r | |
103 | BOOLEAN mSmmReadyToLock = FALSE;\r | |
104 | \r | |
105 | //\r | |
106 | // Global used to cache PCD for SMM Code Access Check enable\r | |
107 | //\r | |
108 | BOOLEAN mSmmCodeAccessCheckEnable = FALSE;\r | |
109 | \r | |
241f9149 LD |
110 | //\r |
111 | // Global copy of the PcdPteMemoryEncryptionAddressOrMask\r | |
112 | //\r | |
113 | UINT64 mAddressEncMask = 0;\r | |
114 | \r | |
529a5a86 MK |
115 | //\r |
116 | // Spin lock used to serialize setting of SMM Code Access Check feature\r | |
117 | //\r | |
fe3a75bc | 118 | SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL;\r |
529a5a86 | 119 | \r |
7ed6f781 JF |
120 | //\r |
121 | // Saved SMM ranges information\r | |
122 | //\r | |
123 | EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;\r | |
124 | UINTN mSmmCpuSmramRangeCount;\r | |
125 | \r | |
51ce27fd SZ |
126 | UINT8 mPhysicalAddressBits;\r |
127 | \r | |
351b49c1 LE |
128 | //\r |
129 | // Control register contents saved for SMM S3 resume state initialization.\r | |
130 | //\r | |
f0053e83 | 131 | UINT32 mSmmCr0;\r |
351b49c1 LE |
132 | UINT32 mSmmCr4;\r |
133 | \r | |
529a5a86 MK |
134 | /**\r |
135 | Initialize IDT to setup exception handlers for SMM.\r | |
136 | \r | |
137 | **/\r | |
138 | VOID\r | |
139 | InitializeSmmIdt (\r | |
140 | VOID\r | |
141 | )\r | |
142 | {\r | |
143 | EFI_STATUS Status;\r | |
144 | BOOLEAN InterruptState;\r | |
145 | IA32_DESCRIPTOR DxeIdtr;\r | |
717fb604 JY |
146 | \r |
147 | //\r | |
148 | // There are 32 (not 255) entries in it since only processor\r | |
149 | // generated exceptions will be handled.\r | |
150 | //\r | |
151 | gcSmiIdtr.Limit = (sizeof(IA32_IDT_GATE_DESCRIPTOR) * 32) - 1;\r | |
152 | //\r | |
153 | // Allocate page aligned IDT, because it might be set as read only.\r | |
154 | //\r | |
155 | gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES(gcSmiIdtr.Limit + 1));\r | |
156 | ASSERT (gcSmiIdtr.Base != 0);\r | |
157 | ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1);\r | |
158 | \r | |
529a5a86 MK |
159 | //\r |
160 | // Disable Interrupt and save DXE IDT table\r | |
161 | //\r | |
162 | InterruptState = SaveAndDisableInterrupts ();\r | |
163 | AsmReadIdtr (&DxeIdtr);\r | |
164 | //\r | |
165 | // Load SMM temporary IDT table\r | |
166 | //\r | |
167 | AsmWriteIdtr (&gcSmiIdtr);\r | |
168 | //\r | |
169 | // Setup SMM default exception handlers, SMM IDT table\r | |
170 | // will be updated and saved in gcSmiIdtr\r | |
171 | //\r | |
172 | Status = InitializeCpuExceptionHandlers (NULL);\r | |
173 | ASSERT_EFI_ERROR (Status);\r | |
174 | //\r | |
175 | // Restore DXE IDT table and CPU interrupt\r | |
176 | //\r | |
177 | AsmWriteIdtr ((IA32_DESCRIPTOR *) &DxeIdtr);\r | |
178 | SetInterruptState (InterruptState);\r | |
179 | }\r | |
180 | \r | |
181 | /**\r | |
182 | Search module name by input IP address and output it.\r | |
183 | \r | |
184 | @param CallerIpAddress Caller instruction pointer.\r | |
185 | \r | |
186 | **/\r | |
187 | VOID\r | |
188 | DumpModuleInfoByIp (\r | |
189 | IN UINTN CallerIpAddress\r | |
190 | )\r | |
191 | {\r | |
192 | UINTN Pe32Data;\r | |
529a5a86 | 193 | VOID *PdbPointer;\r |
529a5a86 MK |
194 | \r |
195 | //\r | |
196 | // Find Image Base\r | |
197 | //\r | |
9e981317 | 198 | Pe32Data = PeCoffSearchImageBase (CallerIpAddress);\r |
529a5a86 | 199 | if (Pe32Data != 0) {\r |
b8caae19 | 200 | DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *) CallerIpAddress));\r |
529a5a86 MK |
201 | PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);\r |
202 | if (PdbPointer != NULL) {\r | |
b8caae19 | 203 | DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer));\r |
529a5a86 MK |
204 | }\r |
205 | }\r | |
206 | }\r | |
207 | \r | |
208 | /**\r | |
209 | Read information from the CPU save state.\r | |
210 | \r | |
211 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
212 | @param Width The number of bytes to read from the CPU save state.\r | |
213 | @param Register Specifies the CPU register to read form the save state.\r | |
214 | @param CpuIndex Specifies the zero-based index of the CPU save state.\r | |
215 | @param Buffer Upon return, this holds the CPU register value read from the save state.\r | |
216 | \r | |
217 | @retval EFI_SUCCESS The register was read from Save State\r | |
218 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
219 | @retval EFI_INVALID_PARAMTER This or Buffer is NULL.\r | |
220 | \r | |
221 | **/\r | |
222 | EFI_STATUS\r | |
223 | EFIAPI\r | |
224 | SmmReadSaveState (\r | |
225 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r | |
226 | IN UINTN Width,\r | |
227 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
228 | IN UINTN CpuIndex,\r | |
229 | OUT VOID *Buffer\r | |
230 | )\r | |
231 | {\r | |
232 | EFI_STATUS Status;\r | |
233 | \r | |
234 | //\r | |
235 | // Retrieve pointer to the specified CPU's SMM Save State buffer\r | |
236 | //\r | |
237 | if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {\r | |
238 | return EFI_INVALID_PARAMETER;\r | |
239 | }\r | |
240 | \r | |
241 | //\r | |
242 | // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID\r | |
243 | //\r | |
244 | if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {\r | |
245 | //\r | |
246 | // The pseudo-register only supports the 64-bit size specified by Width.\r | |
247 | //\r | |
248 | if (Width != sizeof (UINT64)) {\r | |
249 | return EFI_INVALID_PARAMETER;\r | |
250 | }\r | |
251 | //\r | |
252 | // If the processor is in SMM at the time the SMI occurred,\r | |
253 | // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.\r | |
254 | // Otherwise, EFI_NOT_FOUND is returned.\r | |
255 | //\r | |
ed3d5ecb | 256 | if (*(mSmmMpSyncData->CpuData[CpuIndex].Present)) {\r |
529a5a86 MK |
257 | *(UINT64 *)Buffer = gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId;\r |
258 | return EFI_SUCCESS;\r | |
259 | } else {\r | |
260 | return EFI_NOT_FOUND;\r | |
261 | }\r | |
262 | }\r | |
263 | \r | |
ed3d5ecb | 264 | if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) {\r |
529a5a86 MK |
265 | return EFI_INVALID_PARAMETER;\r |
266 | }\r | |
267 | \r | |
268 | Status = SmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register, Width, Buffer);\r | |
269 | if (Status == EFI_UNSUPPORTED) {\r | |
270 | Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer);\r | |
271 | }\r | |
272 | return Status;\r | |
273 | }\r | |
274 | \r | |
275 | /**\r | |
276 | Write data to the CPU save state.\r | |
277 | \r | |
278 | @param This EFI_SMM_CPU_PROTOCOL instance\r | |
279 | @param Width The number of bytes to read from the CPU save state.\r | |
280 | @param Register Specifies the CPU register to write to the save state.\r | |
281 | @param CpuIndex Specifies the zero-based index of the CPU save state\r | |
282 | @param Buffer Upon entry, this holds the new CPU register value.\r | |
283 | \r | |
284 | @retval EFI_SUCCESS The register was written from Save State\r | |
285 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor\r | |
286 | @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct\r | |
287 | \r | |
288 | **/\r | |
289 | EFI_STATUS\r | |
290 | EFIAPI\r | |
291 | SmmWriteSaveState (\r | |
292 | IN CONST EFI_SMM_CPU_PROTOCOL *This,\r | |
293 | IN UINTN Width,\r | |
294 | IN EFI_SMM_SAVE_STATE_REGISTER Register,\r | |
295 | IN UINTN CpuIndex,\r | |
296 | IN CONST VOID *Buffer\r | |
297 | )\r | |
298 | {\r | |
299 | EFI_STATUS Status;\r | |
300 | \r | |
301 | //\r | |
302 | // Retrieve pointer to the specified CPU's SMM Save State buffer\r | |
303 | //\r | |
304 | if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {\r | |
305 | return EFI_INVALID_PARAMETER;\r | |
306 | }\r | |
307 | \r | |
308 | //\r | |
309 | // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored\r | |
310 | //\r | |
311 | if (Register == EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID) {\r | |
312 | return EFI_SUCCESS;\r | |
313 | }\r | |
314 | \r | |
315 | if (!mSmmMpSyncData->CpuData[CpuIndex].Present) {\r | |
316 | return EFI_INVALID_PARAMETER;\r | |
317 | }\r | |
318 | \r | |
319 | Status = SmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register, Width, Buffer);\r | |
320 | if (Status == EFI_UNSUPPORTED) {\r | |
321 | Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer);\r | |
322 | }\r | |
323 | return Status;\r | |
324 | }\r | |
325 | \r | |
326 | \r | |
327 | /**\r | |
328 | C function for SMI handler. To change all processor's SMMBase Register.\r | |
329 | \r | |
330 | **/\r | |
331 | VOID\r | |
332 | EFIAPI\r | |
333 | SmmInitHandler (\r | |
334 | VOID\r | |
335 | )\r | |
336 | {\r | |
337 | UINT32 ApicId;\r | |
338 | UINTN Index;\r | |
339 | \r | |
340 | //\r | |
341 | // Update SMM IDT entries' code segment and load IDT\r | |
342 | //\r | |
343 | AsmWriteIdtr (&gcSmiIdtr);\r | |
344 | ApicId = GetApicId ();\r | |
345 | \r | |
bb767506 | 346 | ASSERT (mNumberOfCpus <= mMaxNumberOfCpus);\r |
529a5a86 MK |
347 | \r |
348 | for (Index = 0; Index < mNumberOfCpus; Index++) {\r | |
349 | if (ApicId == (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {\r | |
350 | //\r | |
351 | // Initialize SMM specific features on the currently executing CPU\r | |
352 | //\r | |
353 | SmmCpuFeaturesInitializeProcessor (\r | |
354 | Index,\r | |
355 | mIsBsp,\r | |
356 | gSmmCpuPrivate->ProcessorInfo,\r | |
357 | &mCpuHotPlugData\r | |
358 | );\r | |
359 | \r | |
a46a4c90 JF |
360 | if (!mSmmS3Flag) {\r |
361 | //\r | |
362 | // Check XD and BTS features on each processor on normal boot\r | |
363 | //\r | |
51773d49 | 364 | CheckFeatureSupported ();\r |
a46a4c90 JF |
365 | }\r |
366 | \r | |
529a5a86 MK |
367 | if (mIsBsp) {\r |
368 | //\r | |
369 | // BSP rebase is already done above.\r | |
370 | // Initialize private data during S3 resume\r | |
371 | //\r | |
372 | InitializeMpSyncData ();\r | |
373 | }\r | |
374 | \r | |
375 | //\r | |
376 | // Hook return after RSM to set SMM re-based flag\r | |
377 | //\r | |
378 | SemaphoreHook (Index, &mRebased[Index]);\r | |
379 | \r | |
380 | return;\r | |
381 | }\r | |
382 | }\r | |
383 | ASSERT (FALSE);\r | |
384 | }\r | |
385 | \r | |
386 | /**\r | |
387 | Relocate SmmBases for each processor.\r | |
388 | \r | |
389 | Execute on first boot and all S3 resumes\r | |
390 | \r | |
391 | **/\r | |
392 | VOID\r | |
393 | EFIAPI\r | |
394 | SmmRelocateBases (\r | |
395 | VOID\r | |
396 | )\r | |
397 | {\r | |
398 | UINT8 BakBuf[BACK_BUF_SIZE];\r | |
399 | SMRAM_SAVE_STATE_MAP BakBuf2;\r | |
400 | SMRAM_SAVE_STATE_MAP *CpuStatePtr;\r | |
401 | UINT8 *U8Ptr;\r | |
402 | UINT32 ApicId;\r | |
403 | UINTN Index;\r | |
404 | UINTN BspIndex;\r | |
405 | \r | |
406 | //\r | |
407 | // Make sure the reserved size is large enough for procedure SmmInitTemplate.\r | |
408 | //\r | |
409 | ASSERT (sizeof (BakBuf) >= gcSmmInitSize);\r | |
410 | \r | |
411 | //\r | |
412 | // Patch ASM code template with current CR0, CR3, and CR4 values\r | |
413 | //\r | |
f0053e83 LE |
414 | mSmmCr0 = (UINT32)AsmReadCr0 ();\r |
415 | PatchInstructionX86 (gPatchSmmCr0, mSmmCr0, 4);\r | |
6b0841c1 | 416 | PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);\r |
351b49c1 LE |
417 | mSmmCr4 = (UINT32)AsmReadCr4 ();\r |
418 | PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);\r | |
529a5a86 MK |
419 | \r |
420 | //\r | |
421 | // Patch GDTR for SMM base relocation\r | |
422 | //\r | |
423 | gcSmiInitGdtr.Base = gcSmiGdtr.Base;\r | |
424 | gcSmiInitGdtr.Limit = gcSmiGdtr.Limit;\r | |
425 | \r | |
426 | U8Ptr = (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);\r | |
427 | CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r | |
428 | \r | |
429 | //\r | |
430 | // Backup original contents at address 0x38000\r | |
431 | //\r | |
432 | CopyMem (BakBuf, U8Ptr, sizeof (BakBuf));\r | |
433 | CopyMem (&BakBuf2, CpuStatePtr, sizeof (BakBuf2));\r | |
434 | \r | |
435 | //\r | |
436 | // Load image for relocation\r | |
437 | //\r | |
438 | CopyMem (U8Ptr, gcSmmInitTemplate, gcSmmInitSize);\r | |
439 | \r | |
440 | //\r | |
441 | // Retrieve the local APIC ID of current processor\r | |
442 | //\r | |
443 | ApicId = GetApicId ();\r | |
444 | \r | |
445 | //\r | |
446 | // Relocate SM bases for all APs\r | |
447 | // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate\r | |
448 | //\r | |
449 | mIsBsp = FALSE;\r | |
450 | BspIndex = (UINTN)-1;\r | |
451 | for (Index = 0; Index < mNumberOfCpus; Index++) {\r | |
452 | mRebased[Index] = FALSE;\r | |
453 | if (ApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {\r | |
454 | SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);\r | |
455 | //\r | |
456 | // Wait for this AP to finish its 1st SMI\r | |
457 | //\r | |
458 | while (!mRebased[Index]);\r | |
459 | } else {\r | |
460 | //\r | |
461 | // BSP will be Relocated later\r | |
462 | //\r | |
463 | BspIndex = Index;\r | |
464 | }\r | |
465 | }\r | |
466 | \r | |
467 | //\r | |
468 | // Relocate BSP's SMM base\r | |
469 | //\r | |
470 | ASSERT (BspIndex != (UINTN)-1);\r | |
471 | mIsBsp = TRUE;\r | |
472 | SendSmiIpi (ApicId);\r | |
473 | //\r | |
474 | // Wait for the BSP to finish its 1st SMI\r | |
475 | //\r | |
476 | while (!mRebased[BspIndex]);\r | |
477 | \r | |
478 | //\r | |
479 | // Restore contents at address 0x38000\r | |
480 | //\r | |
481 | CopyMem (CpuStatePtr, &BakBuf2, sizeof (BakBuf2));\r | |
482 | CopyMem (U8Ptr, BakBuf, sizeof (BakBuf));\r | |
483 | }\r | |
484 | \r | |
529a5a86 MK |
485 | /**\r |
486 | SMM Ready To Lock event notification handler.\r | |
487 | \r | |
488 | The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to\r | |
489 | perform additional lock actions that must be performed from SMM on the next SMI.\r | |
490 | \r | |
491 | @param[in] Protocol Points to the protocol's unique identifier.\r | |
492 | @param[in] Interface Points to the interface instance.\r | |
493 | @param[in] Handle The handle on which the interface was installed.\r | |
494 | \r | |
495 | @retval EFI_SUCCESS Notification handler runs successfully.\r | |
496 | **/\r | |
497 | EFI_STATUS\r | |
498 | EFIAPI\r | |
499 | SmmReadyToLockEventNotify (\r | |
500 | IN CONST EFI_GUID *Protocol,\r | |
501 | IN VOID *Interface,\r | |
502 | IN EFI_HANDLE Handle\r | |
503 | )\r | |
504 | {\r | |
0bdc9e75 | 505 | GetAcpiCpuData ();\r |
529a5a86 | 506 | \r |
d2fc7711 JY |
507 | //\r |
508 | // Cache a copy of UEFI memory map before we start profiling feature.\r | |
509 | //\r | |
510 | GetUefiMemoryMap ();\r | |
511 | \r | |
529a5a86 MK |
512 | //\r |
513 | // Set SMM ready to lock flag and return\r | |
514 | //\r | |
515 | mSmmReadyToLock = TRUE;\r | |
516 | return EFI_SUCCESS;\r | |
517 | }\r | |
518 | \r | |
519 | /**\r | |
520 | The module Entry Point of the CPU SMM driver.\r | |
521 | \r | |
522 | @param ImageHandle The firmware allocated handle for the EFI image.\r | |
523 | @param SystemTable A pointer to the EFI System Table.\r | |
524 | \r | |
525 | @retval EFI_SUCCESS The entry point is executed successfully.\r | |
526 | @retval Other Some error occurs when executing this entry point.\r | |
527 | \r | |
528 | **/\r | |
529 | EFI_STATUS\r | |
530 | EFIAPI\r | |
531 | PiCpuSmmEntry (\r | |
532 | IN EFI_HANDLE ImageHandle,\r | |
533 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
534 | )\r | |
535 | {\r | |
536 | EFI_STATUS Status;\r | |
537 | EFI_MP_SERVICES_PROTOCOL *MpServices;\r | |
538 | UINTN NumberOfEnabledProcessors;\r | |
539 | UINTN Index;\r | |
540 | VOID *Buffer;\r | |
ae82a30b JY |
541 | UINTN BufferPages;\r |
542 | UINTN TileCodeSize;\r | |
543 | UINTN TileDataSize;\r | |
529a5a86 | 544 | UINTN TileSize;\r |
529a5a86 MK |
545 | UINT8 *Stacks;\r |
546 | VOID *Registration;\r | |
547 | UINT32 RegEax;\r | |
548 | UINT32 RegEdx;\r | |
549 | UINTN FamilyId;\r | |
550 | UINTN ModelId;\r | |
551 | UINT32 Cr3;\r | |
552 | \r | |
e21e355e LG |
553 | //\r |
554 | // Initialize address fixup\r | |
555 | //\r | |
556 | PiSmmCpuSmmInitFixupAddress ();\r | |
557 | PiSmmCpuSmiEntryFixupAddress ();\r | |
558 | \r | |
529a5a86 MK |
559 | //\r |
560 | // Initialize Debug Agent to support source level debug in SMM code\r | |
561 | //\r | |
562 | InitializeDebugAgent (DEBUG_AGENT_INIT_SMM, NULL, NULL);\r | |
563 | \r | |
564 | //\r | |
565 | // Report the start of CPU SMM initialization.\r | |
566 | //\r | |
567 | REPORT_STATUS_CODE (\r | |
568 | EFI_PROGRESS_CODE,\r | |
569 | EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT\r | |
570 | );\r | |
571 | \r | |
529a5a86 MK |
572 | //\r |
573 | // Find out SMRR Base and SMRR Size\r | |
574 | //\r | |
575 | FindSmramInfo (&mCpuHotPlugData.SmrrBase, &mCpuHotPlugData.SmrrSize);\r | |
576 | \r | |
577 | //\r | |
578 | // Get MP Services Protocol\r | |
579 | //\r | |
580 | Status = SystemTable->BootServices->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices);\r | |
581 | ASSERT_EFI_ERROR (Status);\r | |
582 | \r | |
583 | //\r | |
584 | // Use MP Services Protocol to retrieve the number of processors and number of enabled processors\r | |
585 | //\r | |
586 | Status = MpServices->GetNumberOfProcessors (MpServices, &mNumberOfCpus, &NumberOfEnabledProcessors);\r | |
587 | ASSERT_EFI_ERROR (Status);\r | |
588 | ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r | |
589 | \r | |
590 | //\r | |
591 | // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.\r | |
592 | // A constant BSP index makes no sense because it may be hot removed.\r | |
593 | //\r | |
594 | DEBUG_CODE (\r | |
595 | if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r | |
596 | \r | |
597 | ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));\r | |
598 | }\r | |
599 | );\r | |
600 | \r | |
601 | //\r | |
602 | // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.\r | |
603 | //\r | |
604 | mSmmCodeAccessCheckEnable = PcdGetBool (PcdCpuSmmCodeAccessCheckEnable);\r | |
605 | DEBUG ((EFI_D_INFO, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable));\r | |
606 | \r | |
241f9149 LD |
607 | //\r |
608 | // Save the PcdPteMemoryEncryptionAddressOrMask value into a global variable.\r | |
609 | // Make sure AddressEncMask is contained to smallest supported address field.\r | |
610 | //\r | |
611 | mAddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r | |
612 | DEBUG ((EFI_D_INFO, "mAddressEncMask = 0x%lx\n", mAddressEncMask));\r | |
613 | \r | |
529a5a86 MK |
614 | //\r |
615 | // If support CPU hot plug, we need to allocate resources for possibly hot-added processors\r | |
616 | //\r | |
617 | if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r | |
618 | mMaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r | |
619 | } else {\r | |
620 | mMaxNumberOfCpus = mNumberOfCpus;\r | |
621 | }\r | |
622 | gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus;\r | |
623 | \r | |
624 | //\r | |
625 | // The CPU save state and code for the SMI entry point are tiled within an SMRAM\r | |
626 | // allocated buffer. The minimum size of this buffer for a uniprocessor system\r | |
627 | // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area\r | |
628 | // just below SMBASE + 64KB. If more than one CPU is present in the platform,\r | |
629 | // then the SMI entry point and the CPU save state areas can be tiles to minimize\r | |
630 | // the total amount SMRAM required for all the CPUs. The tile size can be computed\r | |
631 | // by adding the // CPU save state size, any extra CPU specific context, and\r | |
632 | // the size of code that must be placed at the SMI entry point to transfer\r | |
633 | // control to a C function in the native SMM execution mode. This size is\r | |
634 | // rounded up to the nearest power of 2 to give the tile size for a each CPU.\r | |
635 | // The total amount of memory required is the maximum number of CPUs that\r | |
636 | // platform supports times the tile size. The picture below shows the tiling,\r | |
637 | // where m is the number of tiles that fit in 32KB.\r | |
638 | //\r | |
639 | // +-----------------------------+ <-- 2^n offset from Base of allocated buffer\r | |
640 | // | CPU m+1 Save State |\r | |
641 | // +-----------------------------+\r | |
642 | // | CPU m+1 Extra Data |\r | |
643 | // +-----------------------------+\r | |
644 | // | Padding |\r | |
645 | // +-----------------------------+\r | |
646 | // | CPU 2m SMI Entry |\r | |
647 | // +#############################+ <-- Base of allocated buffer + 64 KB\r | |
648 | // | CPU m-1 Save State |\r | |
649 | // +-----------------------------+\r | |
650 | // | CPU m-1 Extra Data |\r | |
651 | // +-----------------------------+\r | |
652 | // | Padding |\r | |
653 | // +-----------------------------+\r | |
654 | // | CPU 2m-1 SMI Entry |\r | |
655 | // +=============================+ <-- 2^n offset from Base of allocated buffer\r | |
656 | // | . . . . . . . . . . . . |\r | |
657 | // +=============================+ <-- 2^n offset from Base of allocated buffer\r | |
658 | // | CPU 2 Save State |\r | |
659 | // +-----------------------------+\r | |
660 | // | CPU 2 Extra Data |\r | |
661 | // +-----------------------------+\r | |
662 | // | Padding |\r | |
663 | // +-----------------------------+\r | |
664 | // | CPU m+1 SMI Entry |\r | |
665 | // +=============================+ <-- Base of allocated buffer + 32 KB\r | |
666 | // | CPU 1 Save State |\r | |
667 | // +-----------------------------+\r | |
668 | // | CPU 1 Extra Data |\r | |
669 | // +-----------------------------+\r | |
670 | // | Padding |\r | |
671 | // +-----------------------------+\r | |
672 | // | CPU m SMI Entry |\r | |
673 | // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB\r | |
674 | // | CPU 0 Save State |\r | |
675 | // +-----------------------------+\r | |
676 | // | CPU 0 Extra Data |\r | |
677 | // +-----------------------------+\r | |
678 | // | Padding |\r | |
679 | // +-----------------------------+\r | |
680 | // | CPU m-1 SMI Entry |\r | |
681 | // +=============================+ <-- 2^n offset from Base of allocated buffer\r | |
682 | // | . . . . . . . . . . . . |\r | |
683 | // +=============================+ <-- 2^n offset from Base of allocated buffer\r | |
684 | // | Padding |\r | |
685 | // +-----------------------------+\r | |
686 | // | CPU 1 SMI Entry |\r | |
687 | // +=============================+ <-- 2^n offset from Base of allocated buffer\r | |
688 | // | Padding |\r | |
689 | // +-----------------------------+\r | |
690 | // | CPU 0 SMI Entry |\r | |
691 | // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB\r | |
692 | //\r | |
693 | \r | |
694 | //\r | |
695 | // Retrieve CPU Family\r | |
696 | //\r | |
e9b3a6c9 | 697 | AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);\r |
529a5a86 MK |
698 | FamilyId = (RegEax >> 8) & 0xf;\r |
699 | ModelId = (RegEax >> 4) & 0xf;\r | |
700 | if (FamilyId == 0x06 || FamilyId == 0x0f) {\r | |
701 | ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r | |
702 | }\r | |
703 | \r | |
e9b3a6c9 MK |
704 | RegEdx = 0;\r |
705 | AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r | |
706 | if (RegEax >= CPUID_EXTENDED_CPU_SIG) {\r | |
707 | AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);\r | |
708 | }\r | |
529a5a86 MK |
709 | //\r |
710 | // Determine the mode of the CPU at the time an SMI occurs\r | |
711 | // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r | |
712 | // Volume 3C, Section 34.4.1.1\r | |
713 | //\r | |
714 | mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT;\r | |
715 | if ((RegEdx & BIT29) != 0) {\r | |
716 | mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;\r | |
717 | }\r | |
718 | if (FamilyId == 0x06) {\r | |
719 | if (ModelId == 0x17 || ModelId == 0x0f || ModelId == 0x1c) {\r | |
720 | mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;\r | |
721 | }\r | |
722 | }\r | |
723 | \r | |
724 | //\r | |
725 | // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU\r | |
f12367a0 MK |
726 | // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.\r |
727 | // This size is rounded up to nearest power of 2.\r | |
529a5a86 | 728 | //\r |
ae82a30b JY |
729 | TileCodeSize = GetSmiHandlerSize ();\r |
730 | TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);\r | |
f12367a0 | 731 | TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);\r |
ae82a30b JY |
732 | TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);\r |
733 | TileSize = TileDataSize + TileCodeSize - 1;\r | |
529a5a86 | 734 | TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);\r |
ae82a30b | 735 | DEBUG ((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));\r |
529a5a86 MK |
736 | \r |
737 | //\r | |
f12367a0 MK |
738 | // If the TileSize is larger than space available for the SMI Handler of\r |
739 | // CPU[i], the extra CPU specific context of CPU[i+1], and the SMRAM Save\r | |
740 | // State Map of CPU[i+1], then ASSERT(). If this ASSERT() is triggered, then\r | |
741 | // the SMI Handler size must be reduced or the size of the extra CPU specific\r | |
742 | // context must be reduced.\r | |
529a5a86 MK |
743 | //\r |
744 | ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));\r | |
745 | \r | |
746 | //\r | |
747 | // Allocate buffer for all of the tiles.\r | |
748 | //\r | |
749 | // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r | |
750 | // Volume 3C, Section 34.11 SMBASE Relocation\r | |
751 | // For Pentium and Intel486 processors, the SMBASE values must be\r | |
752 | // aligned on a 32-KByte boundary or the processor will enter shutdown\r | |
753 | // state during the execution of a RSM instruction.\r | |
754 | //\r | |
755 | // Intel486 processors: FamilyId is 4\r | |
756 | // Pentium processors : FamilyId is 5\r | |
757 | //\r | |
ae82a30b | 758 | BufferPages = EFI_SIZE_TO_PAGES (SIZE_32KB + TileSize * (mMaxNumberOfCpus - 1));\r |
529a5a86 | 759 | if ((FamilyId == 4) || (FamilyId == 5)) {\r |
717fb604 | 760 | Buffer = AllocateAlignedCodePages (BufferPages, SIZE_32KB);\r |
529a5a86 | 761 | } else {\r |
717fb604 | 762 | Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);\r |
529a5a86 MK |
763 | }\r |
764 | ASSERT (Buffer != NULL);\r | |
ae82a30b | 765 | DEBUG ((EFI_D_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE(BufferPages)));\r |
529a5a86 MK |
766 | \r |
767 | //\r | |
768 | // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.\r | |
769 | //\r | |
770 | gSmmCpuPrivate->ProcessorInfo = (EFI_PROCESSOR_INFORMATION *)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION) * mMaxNumberOfCpus);\r | |
771 | ASSERT (gSmmCpuPrivate->ProcessorInfo != NULL);\r | |
772 | \r | |
773 | gSmmCpuPrivate->Operation = (SMM_CPU_OPERATION *)AllocatePool (sizeof (SMM_CPU_OPERATION) * mMaxNumberOfCpus);\r | |
774 | ASSERT (gSmmCpuPrivate->Operation != NULL);\r | |
775 | \r | |
776 | gSmmCpuPrivate->CpuSaveStateSize = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);\r | |
777 | ASSERT (gSmmCpuPrivate->CpuSaveStateSize != NULL);\r | |
778 | \r | |
779 | gSmmCpuPrivate->CpuSaveState = (VOID **)AllocatePool (sizeof (VOID *) * mMaxNumberOfCpus);\r | |
780 | ASSERT (gSmmCpuPrivate->CpuSaveState != NULL);\r | |
781 | \r | |
782 | mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveStateSize = gSmmCpuPrivate->CpuSaveStateSize;\r | |
783 | mSmmCpuPrivateData.SmmCoreEntryContext.CpuSaveState = gSmmCpuPrivate->CpuSaveState;\r | |
529a5a86 MK |
784 | \r |
785 | //\r | |
786 | // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.\r | |
787 | //\r | |
788 | mCpuHotPlugData.ApicId = (UINT64 *)AllocatePool (sizeof (UINT64) * mMaxNumberOfCpus);\r | |
789 | ASSERT (mCpuHotPlugData.ApicId != NULL);\r | |
790 | mCpuHotPlugData.SmBase = (UINTN *)AllocatePool (sizeof (UINTN) * mMaxNumberOfCpus);\r | |
791 | ASSERT (mCpuHotPlugData.SmBase != NULL);\r | |
792 | mCpuHotPlugData.ArrayLength = (UINT32)mMaxNumberOfCpus;\r | |
793 | \r | |
794 | //\r | |
795 | // Retrieve APIC ID of each enabled processor from the MP Services protocol.\r | |
796 | // Also compute the SMBASE address, CPU Save State address, and CPU Save state\r | |
797 | // size for each CPU in the platform\r | |
798 | //\r | |
799 | for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r | |
800 | mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;\r | |
801 | gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof(SMRAM_SAVE_STATE_MAP);\r | |
802 | gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);\r | |
803 | gSmmCpuPrivate->Operation[Index] = SmmCpuNone;\r | |
804 | \r | |
805 | if (Index < mNumberOfCpus) {\r | |
806 | Status = MpServices->GetProcessorInfo (MpServices, Index, &gSmmCpuPrivate->ProcessorInfo[Index]);\r | |
807 | ASSERT_EFI_ERROR (Status);\r | |
808 | mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId;\r | |
809 | \r | |
810 | DEBUG ((EFI_D_INFO, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",\r | |
811 | Index,\r | |
812 | (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId,\r | |
813 | mCpuHotPlugData.SmBase[Index],\r | |
814 | gSmmCpuPrivate->CpuSaveState[Index],\r | |
815 | gSmmCpuPrivate->CpuSaveStateSize[Index]\r | |
816 | ));\r | |
817 | } else {\r | |
818 | gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = INVALID_APIC_ID;\r | |
819 | mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID;\r | |
820 | }\r | |
821 | }\r | |
822 | \r | |
823 | //\r | |
824 | // Allocate SMI stacks for all processors.\r | |
825 | //\r | |
826 | if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r | |
827 | //\r | |
828 | // 2 more pages is allocated for each processor.\r | |
829 | // one is guard page and the other is known good stack.\r | |
830 | //\r | |
831 | // +-------------------------------------------+-----+-------------------------------------------+\r | |
832 | // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |\r | |
833 | // +-------------------------------------------+-----+-------------------------------------------+\r | |
834 | // | | | |\r | |
835 | // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->|\r | |
836 | //\r | |
837 | mSmmStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2);\r | |
838 | Stacks = (UINT8 *) AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize)) + 2));\r | |
839 | ASSERT (Stacks != NULL);\r | |
840 | mSmmStackArrayBase = (UINTN)Stacks;\r | |
841 | mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize - 1;\r | |
842 | } else {\r | |
843 | mSmmStackSize = PcdGet32 (PcdCpuSmmStackSize);\r | |
844 | Stacks = (UINT8 *) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * mSmmStackSize));\r | |
845 | ASSERT (Stacks != NULL);\r | |
846 | }\r | |
847 | \r | |
848 | //\r | |
849 | // Set SMI stack for SMM base relocation\r | |
850 | //\r | |
5830d2c3 LE |
851 | PatchInstructionX86 (\r |
852 | gPatchSmmInitStack,\r | |
853 | (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)),\r | |
854 | sizeof (UINTN)\r | |
855 | );\r | |
529a5a86 MK |
856 | \r |
857 | //\r | |
858 | // Initialize IDT\r | |
859 | //\r | |
860 | InitializeSmmIdt ();\r | |
861 | \r | |
862 | //\r | |
863 | // Relocate SMM Base addresses to the ones allocated from SMRAM\r | |
864 | //\r | |
865 | mRebased = (BOOLEAN *)AllocateZeroPool (sizeof (BOOLEAN) * mMaxNumberOfCpus);\r | |
866 | ASSERT (mRebased != NULL);\r | |
867 | SmmRelocateBases ();\r | |
868 | \r | |
869 | //\r | |
870 | // Call hook for BSP to perform extra actions in normal mode after all\r | |
871 | // SMM base addresses have been relocated on all CPUs\r | |
872 | //\r | |
873 | SmmCpuFeaturesSmmRelocationComplete ();\r | |
874 | \r | |
717fb604 JY |
875 | DEBUG ((DEBUG_INFO, "mXdSupported - 0x%x\n", mXdSupported));\r |
876 | \r | |
529a5a86 MK |
877 | //\r |
878 | // SMM Time initialization\r | |
879 | //\r | |
880 | InitializeSmmTimer ();\r | |
881 | \r | |
882 | //\r | |
883 | // Initialize MP globals\r | |
884 | //\r | |
885 | Cr3 = InitializeMpServiceData (Stacks, mSmmStackSize);\r | |
886 | \r | |
887 | //\r | |
888 | // Fill in SMM Reserved Regions\r | |
889 | //\r | |
890 | gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedStart = 0;\r | |
891 | gSmmCpuPrivate->SmmReservedSmramRegion[0].SmramReservedSize = 0;\r | |
892 | \r | |
893 | //\r | |
894 | // Install the SMM Configuration Protocol onto a new handle on the handle database.\r | |
895 | // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer\r | |
896 | // to an SMRAM address will be present in the handle database\r | |
897 | //\r | |
898 | Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (\r | |
899 | &gSmmCpuPrivate->SmmCpuHandle,\r | |
900 | &gEfiSmmConfigurationProtocolGuid, &gSmmCpuPrivate->SmmConfiguration,\r | |
901 | NULL\r | |
902 | );\r | |
903 | ASSERT_EFI_ERROR (Status);\r | |
904 | \r | |
905 | //\r | |
906 | // Install the SMM CPU Protocol into SMM protocol database\r | |
907 | //\r | |
908 | Status = gSmst->SmmInstallProtocolInterface (\r | |
909 | &mSmmCpuHandle,\r | |
910 | &gEfiSmmCpuProtocolGuid,\r | |
911 | EFI_NATIVE_INTERFACE,\r | |
912 | &mSmmCpu\r | |
913 | );\r | |
914 | ASSERT_EFI_ERROR (Status);\r | |
915 | \r | |
827330cc JW |
916 | //\r |
917 | // Install the SMM Memory Attribute Protocol into SMM protocol database\r | |
918 | //\r | |
919 | Status = gSmst->SmmInstallProtocolInterface (\r | |
920 | &mSmmCpuHandle,\r | |
921 | &gEdkiiSmmMemoryAttributeProtocolGuid,\r | |
922 | EFI_NATIVE_INTERFACE,\r | |
923 | &mSmmMemoryAttribute\r | |
924 | );\r | |
925 | ASSERT_EFI_ERROR (Status);\r | |
926 | \r | |
529a5a86 MK |
927 | //\r |
928 | // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.\r | |
929 | //\r | |
930 | if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r | |
9838b016 MK |
931 | Status = PcdSet64S (PcdCpuHotPlugDataAddress, (UINT64)(UINTN)&mCpuHotPlugData);\r |
932 | ASSERT_EFI_ERROR (Status);\r | |
529a5a86 MK |
933 | }\r |
934 | \r | |
935 | //\r | |
936 | // Initialize SMM CPU Services Support\r | |
937 | //\r | |
938 | Status = InitializeSmmCpuServices (mSmmCpuHandle);\r | |
939 | ASSERT_EFI_ERROR (Status);\r | |
940 | \r | |
529a5a86 MK |
941 | //\r |
942 | // register SMM Ready To Lock Protocol notification\r | |
943 | //\r | |
944 | Status = gSmst->SmmRegisterProtocolNotify (\r | |
945 | &gEfiSmmReadyToLockProtocolGuid,\r | |
946 | SmmReadyToLockEventNotify,\r | |
947 | &Registration\r | |
948 | );\r | |
949 | ASSERT_EFI_ERROR (Status);\r | |
950 | \r | |
529a5a86 MK |
951 | //\r |
952 | // Initialize SMM Profile feature\r | |
953 | //\r | |
954 | InitSmmProfile (Cr3);\r | |
955 | \r | |
b10d5ddc | 956 | GetAcpiS3EnableFlag ();\r |
0bdc9e75 | 957 | InitSmmS3ResumeState (Cr3);\r |
529a5a86 MK |
958 | \r |
959 | DEBUG ((EFI_D_INFO, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));\r | |
960 | \r | |
961 | return EFI_SUCCESS;\r | |
962 | }\r | |
963 | \r | |
964 | /**\r | |
965 | \r | |
966 | Find out SMRAM information including SMRR base and SMRR size.\r | |
967 | \r | |
968 | @param SmrrBase SMRR base\r | |
969 | @param SmrrSize SMRR size\r | |
970 | \r | |
971 | **/\r | |
972 | VOID\r | |
973 | FindSmramInfo (\r | |
974 | OUT UINT32 *SmrrBase,\r | |
975 | OUT UINT32 *SmrrSize\r | |
976 | )\r | |
977 | {\r | |
978 | EFI_STATUS Status;\r | |
979 | UINTN Size;\r | |
980 | EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;\r | |
981 | EFI_SMRAM_DESCRIPTOR *CurrentSmramRange;\r | |
529a5a86 MK |
982 | UINTN Index;\r |
983 | UINT64 MaxSize;\r | |
984 | BOOLEAN Found;\r | |
985 | \r | |
986 | //\r | |
987 | // Get SMM Access Protocol\r | |
988 | //\r | |
989 | Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **)&SmmAccess);\r | |
990 | ASSERT_EFI_ERROR (Status);\r | |
991 | \r | |
992 | //\r | |
993 | // Get SMRAM information\r | |
994 | //\r | |
995 | Size = 0;\r | |
996 | Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);\r | |
997 | ASSERT (Status == EFI_BUFFER_TOO_SMALL);\r | |
998 | \r | |
7ed6f781 JF |
999 | mSmmCpuSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);\r |
1000 | ASSERT (mSmmCpuSmramRanges != NULL);\r | |
529a5a86 | 1001 | \r |
7ed6f781 | 1002 | Status = SmmAccess->GetCapabilities (SmmAccess, &Size, mSmmCpuSmramRanges);\r |
529a5a86 MK |
1003 | ASSERT_EFI_ERROR (Status);\r |
1004 | \r | |
7ed6f781 | 1005 | mSmmCpuSmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);\r |
529a5a86 MK |
1006 | \r |
1007 | //\r | |
1008 | // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size\r | |
1009 | //\r | |
1010 | CurrentSmramRange = NULL;\r | |
7ed6f781 | 1011 | for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < mSmmCpuSmramRangeCount; Index++) {\r |
529a5a86 MK |
1012 | //\r |
1013 | // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization\r | |
1014 | //\r | |
7ed6f781 | 1015 | if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {\r |
529a5a86 MK |
1016 | continue;\r |
1017 | }\r | |
1018 | \r | |
7ed6f781 JF |
1019 | if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {\r |
1020 | if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) {\r | |
1021 | if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {\r | |
1022 | MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;\r | |
1023 | CurrentSmramRange = &mSmmCpuSmramRanges[Index];\r | |
529a5a86 MK |
1024 | }\r |
1025 | }\r | |
1026 | }\r | |
1027 | }\r | |
1028 | \r | |
1029 | ASSERT (CurrentSmramRange != NULL);\r | |
1030 | \r | |
1031 | *SmrrBase = (UINT32)CurrentSmramRange->CpuStart;\r | |
1032 | *SmrrSize = (UINT32)CurrentSmramRange->PhysicalSize;\r | |
1033 | \r | |
1034 | do {\r | |
1035 | Found = FALSE;\r | |
7ed6f781 JF |
1036 | for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {\r |
1037 | if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase &&\r | |
1038 | *SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)) {\r | |
1039 | *SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;\r | |
1040 | *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);\r | |
529a5a86 | 1041 | Found = TRUE;\r |
7ed6f781 JF |
1042 | } else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart && mSmmCpuSmramRanges[Index].PhysicalSize > 0) {\r |
1043 | *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);\r | |
529a5a86 MK |
1044 | Found = TRUE;\r |
1045 | }\r | |
1046 | }\r | |
1047 | } while (Found);\r | |
1048 | \r | |
1049 | DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize));\r | |
1050 | }\r | |
1051 | \r | |
1052 | /**\r | |
1053 | Configure SMM Code Access Check feature on an AP.\r | |
1054 | SMM Feature Control MSR will be locked after configuration.\r | |
1055 | \r | |
1056 | @param[in,out] Buffer Pointer to private data buffer.\r | |
1057 | **/\r | |
1058 | VOID\r | |
1059 | EFIAPI\r | |
1060 | ConfigSmmCodeAccessCheckOnCurrentProcessor (\r | |
1061 | IN OUT VOID *Buffer\r | |
1062 | )\r | |
1063 | {\r | |
1064 | UINTN CpuIndex;\r | |
1065 | UINT64 SmmFeatureControlMsr;\r | |
1066 | UINT64 NewSmmFeatureControlMsr;\r | |
1067 | \r | |
1068 | //\r | |
1069 | // Retrieve the CPU Index from the context passed in\r | |
1070 | //\r | |
1071 | CpuIndex = *(UINTN *)Buffer;\r | |
1072 | \r | |
1073 | //\r | |
1074 | // Get the current SMM Feature Control MSR value\r | |
1075 | //\r | |
1076 | SmmFeatureControlMsr = SmmCpuFeaturesGetSmmRegister (CpuIndex, SmmRegFeatureControl);\r | |
1077 | \r | |
1078 | //\r | |
1079 | // Compute the new SMM Feature Control MSR value\r | |
1080 | //\r | |
1081 | NewSmmFeatureControlMsr = SmmFeatureControlMsr;\r | |
1082 | if (mSmmCodeAccessCheckEnable) {\r | |
1083 | NewSmmFeatureControlMsr |= SMM_CODE_CHK_EN_BIT;\r | |
f6bc3a6d JF |
1084 | if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock)) {\r |
1085 | NewSmmFeatureControlMsr |= SMM_FEATURE_CONTROL_LOCK_BIT;\r | |
1086 | }\r | |
529a5a86 MK |
1087 | }\r |
1088 | \r | |
1089 | //\r | |
1090 | // Only set the SMM Feature Control MSR value if the new value is different than the current value\r | |
1091 | //\r | |
1092 | if (NewSmmFeatureControlMsr != SmmFeatureControlMsr) {\r | |
1093 | SmmCpuFeaturesSetSmmRegister (CpuIndex, SmmRegFeatureControl, NewSmmFeatureControlMsr);\r | |
1094 | }\r | |
1095 | \r | |
1096 | //\r | |
1097 | // Release the spin lock user to serialize the updates to the SMM Feature Control MSR\r | |
1098 | //\r | |
fe3a75bc | 1099 | ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);\r |
529a5a86 MK |
1100 | }\r |
1101 | \r | |
1102 | /**\r | |
1103 | Configure SMM Code Access Check feature for all processors.\r | |
1104 | SMM Feature Control MSR will be locked after configuration.\r | |
1105 | **/\r | |
1106 | VOID\r | |
1107 | ConfigSmmCodeAccessCheck (\r | |
1108 | VOID\r | |
1109 | )\r | |
1110 | {\r | |
1111 | UINTN Index;\r | |
1112 | EFI_STATUS Status;\r | |
1113 | \r | |
1114 | //\r | |
1115 | // Check to see if the Feature Control MSR is supported on this CPU\r | |
1116 | //\r | |
f6b0cb17 | 1117 | Index = gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu;\r |
529a5a86 MK |
1118 | if (!SmmCpuFeaturesIsSmmRegisterSupported (Index, SmmRegFeatureControl)) {\r |
1119 | mSmmCodeAccessCheckEnable = FALSE;\r | |
1120 | return;\r | |
1121 | }\r | |
1122 | \r | |
1123 | //\r | |
1124 | // Check to see if the CPU supports the SMM Code Access Check feature\r | |
1125 | // Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r | |
1126 | //\r | |
1127 | if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) == 0) {\r | |
1128 | mSmmCodeAccessCheckEnable = FALSE;\r | |
529a5a86 MK |
1129 | return;\r |
1130 | }\r | |
1131 | \r | |
1132 | //\r | |
1133 | // Initialize the lock used to serialize the MSR programming in BSP and all APs\r | |
1134 | //\r | |
fe3a75bc | 1135 | InitializeSpinLock (mConfigSmmCodeAccessCheckLock);\r |
529a5a86 MK |
1136 | \r |
1137 | //\r | |
1138 | // Acquire Config SMM Code Access Check spin lock. The BSP will release the\r | |
1139 | // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().\r | |
1140 | //\r | |
fe3a75bc | 1141 | AcquireSpinLock (mConfigSmmCodeAccessCheckLock);\r |
529a5a86 MK |
1142 | \r |
1143 | //\r | |
1144 | // Enable SMM Code Access Check feature on the BSP.\r | |
1145 | //\r | |
1146 | ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index);\r | |
1147 | \r | |
1148 | //\r | |
1149 | // Enable SMM Code Access Check feature for the APs.\r | |
1150 | //\r | |
1151 | for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {\r | |
f6b0cb17 | 1152 | if (Index != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {\r |
b7025df8 JF |
1153 | if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {\r |
1154 | //\r | |
1155 | // If this processor does not exist\r | |
1156 | //\r | |
1157 | continue;\r | |
1158 | }\r | |
529a5a86 MK |
1159 | //\r |
1160 | // Acquire Config SMM Code Access Check spin lock. The AP will release the\r | |
1161 | // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().\r | |
1162 | //\r | |
fe3a75bc | 1163 | AcquireSpinLock (mConfigSmmCodeAccessCheckLock);\r |
529a5a86 MK |
1164 | \r |
1165 | //\r | |
1166 | // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.\r | |
1167 | //\r | |
1168 | Status = gSmst->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor, Index, &Index);\r | |
1169 | ASSERT_EFI_ERROR (Status);\r | |
1170 | \r | |
1171 | //\r | |
1172 | // Wait for the AP to release the Config SMM Code Access Check spin lock.\r | |
1173 | //\r | |
fe3a75bc | 1174 | while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock)) {\r |
529a5a86 MK |
1175 | CpuPause ();\r |
1176 | }\r | |
1177 | \r | |
1178 | //\r | |
1179 | // Release the Config SMM Code Access Check spin lock.\r | |
1180 | //\r | |
fe3a75bc | 1181 | ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);\r |
529a5a86 MK |
1182 | }\r |
1183 | }\r | |
1184 | }\r | |
1185 | \r | |
21c17193 JY |
1186 | /**\r |
1187 | This API provides a way to allocate memory for page table.\r | |
1188 | \r | |
1189 | This API can be called more once to allocate memory for page tables.\r | |
1190 | \r | |
1191 | Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the\r | |
1192 | allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL\r | |
1193 | is returned. If there is not enough memory remaining to satisfy the request, then NULL is\r | |
1194 | returned.\r | |
1195 | \r | |
1196 | @param Pages The number of 4 KB pages to allocate.\r | |
1197 | \r | |
1198 | @return A pointer to the allocated buffer or NULL if allocation fails.\r | |
1199 | \r | |
1200 | **/\r | |
1201 | VOID *\r | |
1202 | AllocatePageTableMemory (\r | |
1203 | IN UINTN Pages\r | |
1204 | )\r | |
1205 | {\r | |
1206 | VOID *Buffer;\r | |
1207 | \r | |
1208 | Buffer = SmmCpuFeaturesAllocatePageTableMemory (Pages);\r | |
1209 | if (Buffer != NULL) {\r | |
1210 | return Buffer;\r | |
1211 | }\r | |
1212 | return AllocatePages (Pages);\r | |
1213 | }\r | |
1214 | \r | |
717fb604 JY |
1215 | /**\r |
1216 | Allocate pages for code.\r | |
1217 | \r | |
1218 | @param[in] Pages Number of pages to be allocated.\r | |
1219 | \r | |
1220 | @return Allocated memory.\r | |
1221 | **/\r | |
1222 | VOID *\r | |
1223 | AllocateCodePages (\r | |
1224 | IN UINTN Pages\r | |
1225 | )\r | |
1226 | {\r | |
1227 | EFI_STATUS Status;\r | |
1228 | EFI_PHYSICAL_ADDRESS Memory;\r | |
1229 | \r | |
1230 | if (Pages == 0) {\r | |
1231 | return NULL;\r | |
1232 | }\r | |
1233 | \r | |
1234 | Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory);\r | |
1235 | if (EFI_ERROR (Status)) {\r | |
1236 | return NULL;\r | |
1237 | }\r | |
1238 | return (VOID *) (UINTN) Memory;\r | |
1239 | }\r | |
1240 | \r | |
1241 | /**\r | |
1242 | Allocate aligned pages for code.\r | |
1243 | \r | |
1244 | @param[in] Pages Number of pages to be allocated.\r | |
1245 | @param[in] Alignment The requested alignment of the allocation.\r | |
1246 | Must be a power of two.\r | |
1247 | If Alignment is zero, then byte alignment is used.\r | |
1248 | \r | |
1249 | @return Allocated memory.\r | |
1250 | **/\r | |
1251 | VOID *\r | |
1252 | AllocateAlignedCodePages (\r | |
1253 | IN UINTN Pages,\r | |
1254 | IN UINTN Alignment\r | |
1255 | )\r | |
1256 | {\r | |
1257 | EFI_STATUS Status;\r | |
1258 | EFI_PHYSICAL_ADDRESS Memory;\r | |
1259 | UINTN AlignedMemory;\r | |
1260 | UINTN AlignmentMask;\r | |
1261 | UINTN UnalignedPages;\r | |
1262 | UINTN RealPages;\r | |
1263 | \r | |
1264 | //\r | |
1265 | // Alignment must be a power of two or zero.\r | |
1266 | //\r | |
1267 | ASSERT ((Alignment & (Alignment - 1)) == 0);\r | |
1268 | \r | |
1269 | if (Pages == 0) {\r | |
1270 | return NULL;\r | |
1271 | }\r | |
1272 | if (Alignment > EFI_PAGE_SIZE) {\r | |
1273 | //\r | |
1274 | // Calculate the total number of pages since alignment is larger than page size.\r | |
1275 | //\r | |
1276 | AlignmentMask = Alignment - 1;\r | |
1277 | RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);\r | |
1278 | //\r | |
1279 | // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.\r | |
1280 | //\r | |
1281 | ASSERT (RealPages > Pages);\r | |
1282 | \r | |
1283 | Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory);\r | |
1284 | if (EFI_ERROR (Status)) {\r | |
1285 | return NULL;\r | |
1286 | }\r | |
1287 | AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;\r | |
1288 | UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);\r | |
1289 | if (UnalignedPages > 0) {\r | |
1290 | //\r | |
1291 | // Free first unaligned page(s).\r | |
1292 | //\r | |
1293 | Status = gSmst->SmmFreePages (Memory, UnalignedPages);\r | |
1294 | ASSERT_EFI_ERROR (Status);\r | |
1295 | }\r | |
8491e302 | 1296 | Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);\r |
717fb604 JY |
1297 | UnalignedPages = RealPages - Pages - UnalignedPages;\r |
1298 | if (UnalignedPages > 0) {\r | |
1299 | //\r | |
1300 | // Free last unaligned page(s).\r | |
1301 | //\r | |
1302 | Status = gSmst->SmmFreePages (Memory, UnalignedPages);\r | |
1303 | ASSERT_EFI_ERROR (Status);\r | |
1304 | }\r | |
1305 | } else {\r | |
1306 | //\r | |
1307 | // Do not over-allocate pages in this case.\r | |
1308 | //\r | |
1309 | Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, Pages, &Memory);\r | |
1310 | if (EFI_ERROR (Status)) {\r | |
1311 | return NULL;\r | |
1312 | }\r | |
1313 | AlignedMemory = (UINTN) Memory;\r | |
1314 | }\r | |
1315 | return (VOID *) AlignedMemory;\r | |
1316 | }\r | |
1317 | \r | |
529a5a86 MK |
1318 | /**\r |
1319 | Perform the remaining tasks.\r | |
1320 | \r | |
1321 | **/\r | |
1322 | VOID\r | |
1323 | PerformRemainingTasks (\r | |
1324 | VOID\r | |
1325 | )\r | |
1326 | {\r | |
1327 | if (mSmmReadyToLock) {\r | |
1328 | //\r | |
1329 | // Start SMM Profile feature\r | |
1330 | //\r | |
1331 | if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r | |
1332 | SmmProfileStart ();\r | |
1333 | }\r | |
1334 | //\r | |
1335 | // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.\r | |
1336 | //\r | |
1337 | InitPaging ();\r | |
717fb604 JY |
1338 | \r |
1339 | //\r | |
1340 | // Mark critical region to be read-only in page table\r | |
1341 | //\r | |
d2fc7711 JY |
1342 | SetMemMapAttributes ();\r |
1343 | \r | |
1344 | //\r | |
1345 | // For outside SMRAM, we only map SMM communication buffer or MMIO.\r | |
1346 | //\r | |
1347 | SetUefiMemMapAttributes ();\r | |
717fb604 JY |
1348 | \r |
1349 | //\r | |
1350 | // Set page table itself to be read-only\r | |
1351 | //\r | |
1352 | SetPageTableAttributes ();\r | |
1353 | \r | |
529a5a86 MK |
1354 | //\r |
1355 | // Configure SMM Code Access Check feature if available.\r | |
1356 | //\r | |
1357 | ConfigSmmCodeAccessCheck ();\r | |
1358 | \r | |
21c17193 JY |
1359 | SmmCpuFeaturesCompleteSmmReadyToLock ();\r |
1360 | \r | |
529a5a86 MK |
1361 | //\r |
1362 | // Clean SMM ready to lock flag\r | |
1363 | //\r | |
1364 | mSmmReadyToLock = FALSE;\r | |
1365 | }\r | |
1366 | }\r | |
9f419739 JY |
1367 | \r |
1368 | /**\r | |
1369 | Perform the pre tasks.\r | |
1370 | \r | |
1371 | **/\r | |
1372 | VOID\r | |
1373 | PerformPreTasks (\r | |
1374 | VOID\r | |
1375 | )\r | |
1376 | {\r | |
0bdc9e75 | 1377 | RestoreSmmConfigurationInS3 ();\r |
9f419739 | 1378 | }\r |