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1 | /** @file\r |
2 | Scan the entire PCI bus for root bridges to support coreboot UEFI payload.\r | |
3 | \r | |
4 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
5 | \r | |
6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | \r | |
8 | **/\r | |
9 | \r | |
10 | #include <PiDxe.h>\r | |
11 | #include <IndustryStandard/Pci.h>\r | |
12 | #include <Protocol/PciHostBridgeResourceAllocation.h>\r | |
13 | #include <Protocol/PciRootBridgeIo.h>\r | |
14 | #include <Library/BaseMemoryLib.h>\r | |
15 | #include <Library/DebugLib.h>\r | |
16 | #include <Library/MemoryAllocationLib.h>\r | |
17 | #include <Library/PciHostBridgeLib.h>\r | |
18 | #include <Library/PciLib.h>\r | |
19 | #include "PciHostBridge.h"\r | |
20 | \r | |
21 | /**\r | |
22 | Adjust the collected PCI resource.\r | |
23 | \r | |
24 | @param[in] Io IO aperture.\r | |
25 | \r | |
26 | @param[in] Mem MMIO aperture.\r | |
27 | \r | |
28 | @param[in] MemAbove4G MMIO aperture above 4G.\r | |
29 | \r | |
30 | @param[in] PMem Prefetchable MMIO aperture.\r | |
31 | \r | |
32 | @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r | |
33 | **/\r | |
34 | VOID\r | |
35 | AdjustRootBridgeResource (\r | |
36 | IN PCI_ROOT_BRIDGE_APERTURE *Io,\r | |
37 | IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r | |
38 | IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r | |
39 | IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r | |
40 | IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r | |
41 | )\r | |
42 | {\r | |
43 | UINT64 Mask;\r | |
44 | \r | |
45 | //\r | |
46 | // For now try to downgrade everything into MEM32 since\r | |
47 | // - coreboot does not assign resource above 4GB\r | |
48 | // - coreboot might allocate interleaved MEM32 and PMEM32 resource\r | |
49 | // in some cases\r | |
50 | //\r | |
51 | if (PMem->Base < Mem->Base) {\r | |
52 | Mem->Base = PMem->Base;\r | |
53 | }\r | |
54 | \r | |
55 | if (PMem->Limit > Mem->Limit) {\r | |
56 | Mem->Limit = PMem->Limit;\r | |
57 | }\r | |
58 | \r | |
59 | PMem->Base = MAX_UINT64;\r | |
60 | PMem->Limit = 0;\r | |
61 | \r | |
62 | if (MemAbove4G->Base < 0x100000000ULL) {\r | |
63 | if (MemAbove4G->Base < Mem->Base) {\r | |
64 | Mem->Base = MemAbove4G->Base;\r | |
65 | }\r | |
66 | if (MemAbove4G->Limit > Mem->Limit) {\r | |
67 | Mem->Limit = MemAbove4G->Limit;\r | |
68 | }\r | |
69 | MemAbove4G->Base = MAX_UINT64;\r | |
70 | MemAbove4G->Limit = 0;\r | |
71 | }\r | |
72 | \r | |
73 | if (PMemAbove4G->Base < 0x100000000ULL) {\r | |
74 | if (PMemAbove4G->Base < Mem->Base) {\r | |
75 | Mem->Base = PMemAbove4G->Base;\r | |
76 | }\r | |
77 | if (PMemAbove4G->Limit > Mem->Limit) {\r | |
78 | Mem->Limit = PMemAbove4G->Limit;\r | |
79 | }\r | |
80 | PMemAbove4G->Base = MAX_UINT64;\r | |
81 | PMemAbove4G->Limit = 0;\r | |
82 | }\r | |
83 | \r | |
84 | //\r | |
85 | // Align IO resource at 4K boundary\r | |
86 | //\r | |
87 | Mask = 0xFFFULL;\r | |
88 | Io->Limit = ((Io->Limit + Mask) & ~Mask) - 1;\r | |
89 | if (Io->Base != MAX_UINT64) {\r | |
90 | Io->Base &= ~Mask;\r | |
91 | }\r | |
92 | \r | |
93 | //\r | |
94 | // Align MEM resource at 1MB boundary\r | |
95 | //\r | |
96 | Mask = 0xFFFFFULL;\r | |
97 | Mem->Limit = ((Mem->Limit + Mask) & ~Mask) - 1;\r | |
98 | if (Mem->Base != MAX_UINT64) {\r | |
99 | Mem->Base &= ~Mask;\r | |
100 | }\r | |
101 | }\r | |
102 | \r | |
103 | /**\r | |
104 | Probe a bar is existed or not.\r | |
105 | \r | |
106 | @param[in] Address PCI address for the BAR.\r | |
107 | @param[out] OriginalValue The original bar value returned.\r | |
108 | @param[out] Value The probed bar value returned.\r | |
109 | **/\r | |
110 | STATIC\r | |
111 | VOID\r | |
112 | PcatPciRootBridgeBarExisted (\r | |
113 | IN UINT64 Address,\r | |
114 | OUT UINT32 *OriginalValue,\r | |
115 | OUT UINT32 *Value\r | |
116 | )\r | |
117 | {\r | |
118 | UINTN PciAddress;\r | |
119 | \r | |
120 | PciAddress = (UINTN)Address;\r | |
121 | \r | |
122 | //\r | |
123 | // Preserve the original value\r | |
124 | //\r | |
125 | *OriginalValue = PciRead32 (PciAddress);\r | |
126 | \r | |
127 | //\r | |
128 | // Disable timer interrupt while the BAR is probed\r | |
129 | //\r | |
130 | DisableInterrupts ();\r | |
131 | \r | |
132 | PciWrite32 (PciAddress, 0xFFFFFFFF);\r | |
133 | *Value = PciRead32 (PciAddress);\r | |
134 | PciWrite32 (PciAddress, *OriginalValue);\r | |
135 | \r | |
136 | //\r | |
137 | // Enable interrupt\r | |
138 | //\r | |
139 | EnableInterrupts ();\r | |
140 | }\r | |
141 | \r | |
142 | /**\r | |
143 | Parse PCI bar and collect the assigned PCI resource information.\r | |
144 | \r | |
145 | @param[in] Command Supported attributes.\r | |
146 | \r | |
147 | @param[in] Bus PCI bus number.\r | |
148 | \r | |
149 | @param[in] Device PCI device number.\r | |
150 | \r | |
151 | @param[in] Function PCI function number.\r | |
152 | \r | |
153 | @param[in] BarOffsetBase PCI bar start offset.\r | |
154 | \r | |
155 | @param[in] BarOffsetEnd PCI bar end offset.\r | |
156 | \r | |
157 | @param[in] Io IO aperture.\r | |
158 | \r | |
159 | @param[in] Mem MMIO aperture.\r | |
160 | \r | |
161 | @param[in] MemAbove4G MMIO aperture above 4G.\r | |
162 | \r | |
163 | @param[in] PMem Prefetchable MMIO aperture.\r | |
164 | \r | |
165 | @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r | |
166 | **/\r | |
167 | STATIC\r | |
168 | VOID\r | |
169 | PcatPciRootBridgeParseBars (\r | |
170 | IN UINT16 Command,\r | |
171 | IN UINTN Bus,\r | |
172 | IN UINTN Device,\r | |
173 | IN UINTN Function,\r | |
174 | IN UINTN BarOffsetBase,\r | |
175 | IN UINTN BarOffsetEnd,\r | |
176 | IN PCI_ROOT_BRIDGE_APERTURE *Io,\r | |
177 | IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r | |
178 | IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r | |
179 | IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r | |
180 | IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r | |
181 | \r | |
182 | )\r | |
183 | {\r | |
184 | UINT32 OriginalValue;\r | |
185 | UINT32 Value;\r | |
186 | UINT32 OriginalUpperValue;\r | |
187 | UINT32 UpperValue;\r | |
188 | UINT64 Mask;\r | |
189 | UINTN Offset;\r | |
190 | UINTN LowBit;\r | |
191 | UINT64 Base;\r | |
192 | UINT64 Length;\r | |
193 | UINT64 Limit;\r | |
194 | PCI_ROOT_BRIDGE_APERTURE *MemAperture;\r | |
195 | \r | |
196 | for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {\r | |
197 | PcatPciRootBridgeBarExisted (\r | |
198 | PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r | |
199 | &OriginalValue, &Value\r | |
200 | );\r | |
201 | if (Value == 0) {\r | |
202 | continue;\r | |
203 | }\r | |
204 | if ((Value & BIT0) == BIT0) {\r | |
205 | //\r | |
206 | // IO Bar\r | |
207 | //\r | |
208 | if (Command & EFI_PCI_COMMAND_IO_SPACE) {\r | |
209 | Mask = 0xfffffffc;\r | |
210 | Base = OriginalValue & Mask;\r | |
211 | Length = ((~(Value & Mask)) & Mask) + 0x04;\r | |
212 | if (!(Value & 0xFFFF0000)) {\r | |
213 | Length &= 0x0000FFFF;\r | |
214 | }\r | |
215 | Limit = Base + Length - 1;\r | |
216 | \r | |
217 | if ((Base > 0) && (Base < Limit)) {\r | |
218 | if (Io->Base > Base) {\r | |
219 | Io->Base = Base;\r | |
220 | }\r | |
221 | if (Io->Limit < Limit) {\r | |
222 | Io->Limit = Limit;\r | |
223 | }\r | |
224 | }\r | |
225 | }\r | |
226 | } else {\r | |
227 | //\r | |
228 | // Mem Bar\r | |
229 | //\r | |
230 | if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {\r | |
231 | \r | |
232 | Mask = 0xfffffff0;\r | |
233 | Base = OriginalValue & Mask;\r | |
234 | Length = Value & Mask;\r | |
235 | \r | |
236 | if ((Value & (BIT1 | BIT2)) == 0) {\r | |
237 | //\r | |
238 | // 32bit\r | |
239 | //\r | |
240 | Length = ((~Length) + 1) & 0xffffffff;\r | |
241 | \r | |
242 | if ((Value & BIT3) == BIT3) {\r | |
243 | MemAperture = PMem;\r | |
244 | } else {\r | |
245 | MemAperture = Mem;\r | |
246 | }\r | |
247 | } else {\r | |
248 | //\r | |
249 | // 64bit\r | |
250 | //\r | |
251 | Offset += 4;\r | |
252 | PcatPciRootBridgeBarExisted (\r | |
253 | PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r | |
254 | &OriginalUpperValue,\r | |
255 | &UpperValue\r | |
256 | );\r | |
257 | \r | |
258 | Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);\r | |
259 | Length = Length | LShiftU64 ((UINT64) UpperValue, 32);\r | |
260 | if (Length != 0) {\r | |
261 | LowBit = LowBitSet64 (Length);\r | |
262 | Length = LShiftU64 (1ULL, LowBit);\r | |
263 | }\r | |
264 | \r | |
265 | if ((Value & BIT3) == BIT3) {\r | |
266 | MemAperture = PMemAbove4G;\r | |
267 | } else {\r | |
268 | MemAperture = MemAbove4G;\r | |
269 | }\r | |
270 | }\r | |
271 | \r | |
272 | Limit = Base + Length - 1;\r | |
273 | if ((Base > 0) && (Base < Limit)) {\r | |
274 | if (MemAperture->Base > Base) {\r | |
275 | MemAperture->Base = Base;\r | |
276 | }\r | |
277 | if (MemAperture->Limit < Limit) {\r | |
278 | MemAperture->Limit = Limit;\r | |
279 | }\r | |
280 | }\r | |
281 | }\r | |
282 | }\r | |
283 | }\r | |
284 | }\r | |
285 | \r | |
286 | /**\r | |
287 | Scan for all root bridges in platform.\r | |
288 | \r | |
289 | @param[out] NumberOfRootBridges Number of root bridges detected\r | |
290 | \r | |
291 | @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.\r | |
292 | **/\r | |
293 | PCI_ROOT_BRIDGE *\r | |
294 | ScanForRootBridges (\r | |
295 | OUT UINTN *NumberOfRootBridges\r | |
296 | )\r | |
297 | {\r | |
298 | UINTN PrimaryBus;\r | |
299 | UINTN SubBus;\r | |
300 | UINT8 Device;\r | |
301 | UINT8 Function;\r | |
302 | UINTN NumberOfDevices;\r | |
303 | UINTN Address;\r | |
304 | PCI_TYPE01 Pci;\r | |
305 | UINT64 Attributes;\r | |
306 | UINT64 Base;\r | |
307 | UINT64 Limit;\r | |
308 | UINT64 Value;\r | |
309 | PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;\r | |
310 | PCI_ROOT_BRIDGE *RootBridges;\r | |
311 | UINTN BarOffsetEnd;\r | |
312 | \r | |
313 | \r | |
314 | *NumberOfRootBridges = 0;\r | |
315 | RootBridges = NULL;\r | |
316 | \r | |
317 | //\r | |
318 | // After scanning all the PCI devices on the PCI root bridge's primary bus,\r | |
319 | // update the Primary Bus Number for the next PCI root bridge to be this PCI\r | |
320 | // root bridge's subordinate bus number + 1.\r | |
321 | //\r | |
322 | for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {\r | |
323 | SubBus = PrimaryBus;\r | |
324 | Attributes = 0;\r | |
325 | \r | |
326 | ZeroMem (&Io, sizeof (Io));\r | |
327 | ZeroMem (&Mem, sizeof (Mem));\r | |
328 | ZeroMem (&MemAbove4G, sizeof (MemAbove4G));\r | |
329 | ZeroMem (&PMem, sizeof (PMem));\r | |
330 | ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));\r | |
331 | Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;\r | |
332 | //\r | |
333 | // Scan all the PCI devices on the primary bus of the PCI root bridge\r | |
334 | //\r | |
335 | for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {\r | |
336 | \r | |
337 | for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {\r | |
338 | \r | |
339 | //\r | |
340 | // Compute the PCI configuration address of the PCI device to probe\r | |
341 | //\r | |
342 | Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);\r | |
343 | \r | |
344 | //\r | |
345 | // Read the Vendor ID from the PCI Configuration Header\r | |
346 | //\r | |
347 | if (PciRead16 (Address) == MAX_UINT16) {\r | |
348 | if (Function == 0) {\r | |
349 | //\r | |
350 | // If the PCI Configuration Read fails, or a PCI device does not\r | |
351 | // exist, then skip this entire PCI device\r | |
352 | //\r | |
353 | break;\r | |
354 | } else {\r | |
355 | //\r | |
356 | // If PCI function != 0, VendorId == 0xFFFF, we continue to search\r | |
357 | // PCI function.\r | |
358 | //\r | |
359 | continue;\r | |
360 | }\r | |
361 | }\r | |
362 | \r | |
363 | //\r | |
364 | // Read the entire PCI Configuration Header\r | |
365 | //\r | |
366 | PciReadBuffer (Address, sizeof (Pci), &Pci);\r | |
367 | \r | |
368 | //\r | |
369 | // Increment the number of PCI device found on the primary bus of the\r | |
370 | // PCI root bridge\r | |
371 | //\r | |
372 | NumberOfDevices++;\r | |
373 | \r | |
374 | //\r | |
375 | // Look for devices with the VGA Palette Snoop enabled in the COMMAND\r | |
376 | // register of the PCI Config Header\r | |
377 | //\r | |
378 | if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {\r | |
379 | Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r | |
380 | Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r | |
381 | }\r | |
382 | \r | |
383 | BarOffsetEnd = 0;\r | |
384 | \r | |
385 | //\r | |
386 | // PCI-PCI Bridge\r | |
387 | //\r | |
388 | if (IS_PCI_BRIDGE (&Pci)) {\r | |
389 | //\r | |
390 | // Get the Bus range that the PPB is decoding\r | |
391 | //\r | |
392 | if (Pci.Bridge.SubordinateBus > SubBus) {\r | |
393 | //\r | |
394 | // If the subordinate bus number of the PCI-PCI bridge is greater\r | |
395 | // than the PCI root bridge's current subordinate bus number,\r | |
396 | // then update the PCI root bridge's subordinate bus number\r | |
397 | //\r | |
398 | SubBus = Pci.Bridge.SubordinateBus;\r | |
399 | }\r | |
400 | \r | |
401 | //\r | |
402 | // Get the I/O range that the PPB is decoding\r | |
403 | //\r | |
404 | Value = Pci.Bridge.IoBase & 0x0f;\r | |
405 | Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;\r | |
406 | Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;\r | |
407 | if (Value == BIT0) {\r | |
408 | Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);\r | |
409 | Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);\r | |
410 | }\r | |
411 | if ((Base > 0) && (Base < Limit)) {\r | |
412 | if (Io.Base > Base) {\r | |
413 | Io.Base = Base;\r | |
414 | }\r | |
415 | if (Io.Limit < Limit) {\r | |
416 | Io.Limit = Limit;\r | |
417 | }\r | |
418 | }\r | |
419 | \r | |
420 | //\r | |
421 | // Get the Memory range that the PPB is decoding\r | |
422 | //\r | |
423 | Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;\r | |
424 | Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;\r | |
425 | if ((Base > 0) && (Base < Limit)) {\r | |
426 | if (Mem.Base > Base) {\r | |
427 | Mem.Base = Base;\r | |
428 | }\r | |
429 | if (Mem.Limit < Limit) {\r | |
430 | Mem.Limit = Limit;\r | |
431 | }\r | |
432 | }\r | |
433 | \r | |
434 | //\r | |
435 | // Get the Prefetchable Memory range that the PPB is decoding\r | |
436 | //\r | |
437 | Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;\r | |
438 | Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r | |
439 | Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)\r | |
440 | << 16) | 0xfffff;\r | |
441 | MemAperture = &PMem;\r | |
442 | if (Value == BIT0) {\r | |
443 | Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r | |
444 | Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r | |
445 | MemAperture = &PMemAbove4G;\r | |
446 | }\r | |
447 | if ((Base > 0) && (Base < Limit)) {\r | |
448 | if (MemAperture->Base > Base) {\r | |
449 | MemAperture->Base = Base;\r | |
450 | }\r | |
451 | if (MemAperture->Limit < Limit) {\r | |
452 | MemAperture->Limit = Limit;\r | |
453 | }\r | |
454 | }\r | |
455 | \r | |
456 | //\r | |
457 | // Look at the PPB Configuration for legacy decoding attributes\r | |
458 | //\r | |
459 | if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)\r | |
460 | == EFI_PCI_BRIDGE_CONTROL_ISA) {\r | |
461 | Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r | |
462 | Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r | |
463 | Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r | |
464 | }\r | |
465 | if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)\r | |
466 | == EFI_PCI_BRIDGE_CONTROL_VGA) {\r | |
467 | Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r | |
468 | Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r | |
469 | Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r | |
470 | if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)\r | |
471 | != 0) {\r | |
472 | Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r | |
473 | Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r | |
474 | }\r | |
475 | }\r | |
476 | \r | |
477 | BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);\r | |
478 | } else {\r | |
479 | //\r | |
480 | // Parse the BARs of the PCI device to get what I/O Ranges, Memory\r | |
481 | // Ranges, and Prefetchable Memory Ranges the device is decoding\r | |
482 | //\r | |
483 | if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {\r | |
484 | BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);\r | |
485 | }\r | |
486 | }\r | |
487 | \r | |
488 | PcatPciRootBridgeParseBars (\r | |
489 | Pci.Hdr.Command,\r | |
490 | PrimaryBus,\r | |
491 | Device,\r | |
492 | Function,\r | |
493 | OFFSET_OF (PCI_TYPE00, Device.Bar),\r | |
494 | BarOffsetEnd,\r | |
495 | &Io,\r | |
496 | &Mem, &MemAbove4G,\r | |
497 | &PMem, &PMemAbove4G\r | |
498 | );\r | |
499 | \r | |
500 | //\r | |
501 | // See if the PCI device is an IDE controller\r | |
502 | //\r | |
503 | if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,\r | |
504 | PCI_CLASS_MASS_STORAGE_IDE)) {\r | |
505 | if (Pci.Hdr.ClassCode[0] & 0x80) {\r | |
506 | Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r | |
507 | Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r | |
508 | }\r | |
509 | if (Pci.Hdr.ClassCode[0] & 0x01) {\r | |
510 | Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r | |
511 | }\r | |
512 | if (Pci.Hdr.ClassCode[0] & 0x04) {\r | |
513 | Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r | |
514 | }\r | |
515 | }\r | |
516 | \r | |
517 | //\r | |
518 | // See if the PCI device is a legacy VGA controller or\r | |
519 | // a standard VGA controller\r | |
520 | //\r | |
521 | if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||\r | |
522 | IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)\r | |
523 | ) {\r | |
524 | Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r | |
525 | Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r | |
526 | Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r | |
527 | Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r | |
528 | Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r | |
529 | }\r | |
530 | \r | |
531 | //\r | |
532 | // See if the PCI Device is a PCI - ISA or PCI - EISA\r | |
533 | // or ISA_POSITIVE_DECODE Bridge device\r | |
534 | //\r | |
535 | if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {\r | |
536 | if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||\r | |
537 | Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||\r | |
538 | Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {\r | |
539 | Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r | |
540 | Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r | |
541 | Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r | |
542 | }\r | |
543 | }\r | |
544 | \r | |
545 | //\r | |
546 | // If this device is not a multi function device, then skip the rest\r | |
547 | // of this PCI device\r | |
548 | //\r | |
549 | if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r | |
550 | break;\r | |
551 | }\r | |
552 | }\r | |
553 | }\r | |
554 | \r | |
555 | //\r | |
556 | // If at least one PCI device was found on the primary bus of this PCI\r | |
557 | // root bridge, then the PCI root bridge exists.\r | |
558 | //\r | |
559 | if (NumberOfDevices > 0) {\r | |
560 | RootBridges = ReallocatePool (\r | |
561 | (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),\r | |
562 | (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),\r | |
563 | RootBridges\r | |
564 | );\r | |
565 | ASSERT (RootBridges != NULL);\r | |
566 | \r | |
567 | AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G);\r | |
568 | \r | |
569 | InitRootBridge (\r | |
570 | Attributes, Attributes, 0,\r | |
571 | (UINT8) PrimaryBus, (UINT8) SubBus,\r | |
572 | &Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,\r | |
573 | &RootBridges[*NumberOfRootBridges]\r | |
574 | );\r | |
575 | RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;\r | |
576 | //\r | |
577 | // Increment the index for the next PCI Root Bridge\r | |
578 | //\r | |
579 | (*NumberOfRootBridges)++;\r | |
580 | }\r | |
581 | }\r | |
582 | \r | |
583 | return RootBridges;\r | |
584 | }\r |