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1 | /*++\r |
2 | \r | |
3 | Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r | |
4 | \r | |
5 | This program and the accompanying materials are licensed and made available under\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution.\r | |
7 | The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php.\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | \r | |
14 | \r | |
15 | Module Name:\r | |
16 | \r | |
17 | IgdOpRn.ASL\r | |
18 | \r | |
19 | Abstract:\r | |
20 | \r | |
21 | IGD OpRegion/Software SCI Reference Code for the Baytrail Family.\r | |
22 | This file contains the interrupt handler code for the Integrated\r | |
23 | Graphics Device (IGD) OpRegion/Software SCI mechanism.\r | |
24 | \r | |
25 | --*/\r | |
26 | \r | |
27 | \r | |
28 | //NOTES:\r | |
29 | //\r | |
30 | // (1) The code contained in this file inherits the scope in which it\r | |
31 | // was included. So BIOS developers must be sure to include this\r | |
32 | // file in the scope associated with the graphics device\r | |
33 | // (ex. \_SB.PCI0.GFX0).\r | |
34 | // (2) Create a _L06 method under the GPE scope to handle the event\r | |
35 | // generated by the graphics driver. The _L06 method must call\r | |
36 | // the GSCI method in this file.\r | |
37 | // (3) The MCHP operation region assumes that _ADR and _BBN names\r | |
38 | // corresponding to bus 0, device0, function 0 have been declared\r | |
39 | // under the PCI0 scope.\r | |
40 | // (4) Before the first execution of the GSCI method, the base address\r | |
41 | // of the GMCH SCI OpRegion must be programmed where the driver can\r | |
42 | // access it. A 32bit scratch register at 0xFC in the IGD PCI\r | |
43 | // configuration space (B0/D2/F0/R0FCh) is used for this purpose.\r | |
44 | \r | |
45 | // Define an OperationRegion to cover the GMCH PCI configuration space as\r | |
46 | // described in the IGD OpRegion specificiation.\r | |
47 | \r | |
48 | // Define an OperationRegion to cover the IGD PCI configuration space as\r | |
49 | // described in the IGD OpRegion specificiation.\r | |
50 | \r | |
51 | OperationRegion(IGDP, PCI_Config,0x00,0x100)\r | |
52 | Field(IGDP, AnyAcc, NoLock, Preserve)\r | |
53 | {\r | |
54 | Offset(0x10), // GTTMMADR\r | |
55 | MADR, 32,\r | |
56 | Offset(0x50), // GMCH Graphics Control Register\r | |
57 | , 1,\r | |
58 | GIVD, 1, // IGD VGA disable bit\r | |
59 | , 1,\r | |
60 | GUMA, 5, // Stolen memory size\r | |
61 | , 8,\r | |
62 | Offset(0x54),\r | |
63 | , 4,\r | |
64 | GMFN, 1, // Gfx function 1 enable\r | |
65 | , 27,\r | |
66 | Offset(0x5C), // Stolen Memory Base Address\r | |
67 | GSTM, 32,\r | |
68 | Offset(0xE0), // Reg 0xE8, SWSCI control register\r | |
69 | GSSE, 1, // Graphics SCI event (1=event pending)\r | |
70 | GSSB, 14, // Graphics SCI scratchpad bits\r | |
71 | GSES, 1, // Graphics event select (1=SCI)\r | |
72 | Offset(0xE4),\r | |
73 | ASLE, 8, // Reg 0xE4, ASLE interrupt register\r | |
74 | , 24, // Only use first byte of ASLE reg\r | |
75 | Offset(0xFC),\r | |
76 | ASLS, 32, // Reg 0xFC, Address of the IGD OpRegion\r | |
77 | }\r | |
78 | \r | |
79 | Method (MCHK, 0, Serialized)\r | |
80 | {\r | |
81 | \r | |
82 | If (LNotEqual (MADR, 0xFFFFFFFF))\r | |
83 | {\r | |
84 | OperationRegion(IGMM,SystemMemory,MADR,0x3000)\r | |
85 | Field(IGMM,AnyAcc, NoLock, Preserve)\r | |
86 | {\r | |
87 | Offset(0X20C8),\r | |
88 | , 4,\r | |
89 | DCFE, 4, // DISPLAY_CLOCK_FREQUENCY_ENCODING\r | |
90 | }\r | |
91 | }\r | |
92 | }\r | |
93 | \r | |
94 | \r | |
95 | // Define an OperationRegion to cover the IGD OpRegion layout.\r | |
96 | \r | |
97 | OperationRegion(IGDM, SystemMemory, ASLB, 0x2000)\r | |
98 | Field(IGDM, AnyAcc, NoLock, Preserve)\r | |
99 | {\r | |
100 | \r | |
101 | // OpRegion Header\r | |
102 | \r | |
103 | SIGN, 128, // Signature-"IntelGraphicsMem"\r | |
104 | SIZE, 32, // OpRegion Size\r | |
105 | OVER, 32, // OpRegion Version\r | |
106 | SVER, 256, // System BIOS Version\r | |
107 | VVER, 128, // VBIOS Version\r | |
108 | GVER, 128, // Driver version\r | |
109 | MBOX, 32, // Mailboxes supported\r | |
110 | DMOD, 32, // Driver Model\r | |
111 | PCON, 32, // 96, Platform Configuration\r | |
112 | \r | |
113 | // OpRegion Mailbox 1 (Public ACPI Methods)\r | |
114 | // Note: Mailbox 1 is normally reserved for desktop platforms.\r | |
115 | \r | |
116 | Offset(0x100),\r | |
117 | DRDY, 32, // Driver readiness (ACPI notification)\r | |
118 | CSTS, 32, // Notification status\r | |
119 | CEVT, 32, // Current event\r | |
120 | Offset(0x120),\r | |
121 | DIDL, 32, // Supported display device ID list\r | |
122 | DDL2, 32, // Allows for 8 devices\r | |
123 | DDL3, 32,\r | |
124 | DDL4, 32,\r | |
125 | DDL5, 32,\r | |
126 | DDL6, 32,\r | |
127 | DDL7, 32,\r | |
128 | DDL8, 32,\r | |
129 | CPDL, 32, // Currently present display list\r | |
130 | CPL2, 32, // Allows for 8 devices\r | |
131 | CPL3, 32,\r | |
132 | CPL4, 32,\r | |
133 | CPL5, 32,\r | |
134 | CPL6, 32,\r | |
135 | CPL7, 32,\r | |
136 | CPL8, 32,\r | |
137 | CAD1, 32, // Currently active display list\r | |
138 | CAL2, 32, // Allows for 8 devices\r | |
139 | CAL3, 32,\r | |
140 | CAL4, 32,\r | |
141 | CAL5, 32,\r | |
142 | CAL6, 32,\r | |
143 | CAL7, 32,\r | |
144 | CAL8, 32,\r | |
145 | NADL, 32, // Next active display list\r | |
146 | NDL2, 32, // Allows for 8 devices\r | |
147 | NDL3, 32,\r | |
148 | NDL4, 32,\r | |
149 | NDL5, 32,\r | |
150 | NDL6, 32,\r | |
151 | NDL7, 32,\r | |
152 | NDL8, 32,\r | |
153 | ASLP, 32, // ASL sleep timeout\r | |
154 | TIDX, 32, // Toggle table index\r | |
155 | CHPD, 32, // Current hot plug enable indicator\r | |
156 | CLID, 32, // Current lid state indicator\r | |
157 | CDCK, 32, // Current docking state indicator\r | |
158 | SXSW, 32, // Display switch notify on resume\r | |
159 | EVTS, 32, // Events supported by ASL (diag only)\r | |
160 | CNOT, 32, // Current OS notifications (diag only)\r | |
161 | NRDY, 32,\r | |
162 | \r | |
163 | // OpRegion Mailbox 2 (Software SCI Interface)\r | |
164 | \r | |
165 | Offset(0x200), // SCIC\r | |
166 | SCIE, 1, // SCI entry bit (1=call unserviced)\r | |
167 | GEFC, 4, // Entry function code\r | |
168 | GXFC, 3, // Exit result\r | |
169 | GESF, 8, // Entry/exit sub-function/parameter\r | |
170 | , 16, // SCIC[31:16] reserved\r | |
171 | Offset(0x204), // PARM\r | |
172 | PARM, 32, // PARM register (extra parameters)\r | |
173 | DSLP, 32, // Driver sleep time out\r | |
174 | \r | |
175 | // OpRegion Mailbox 3 (BIOS to Driver Notification)\r | |
176 | // Note: Mailbox 3 is normally reserved for desktop platforms.\r | |
177 | \r | |
178 | Offset(0x300),\r | |
179 | ARDY, 32, // Driver readiness (power conservation)\r | |
180 | ASLC, 32, // ASLE interrupt command/status\r | |
181 | TCHE, 32, // Technology enabled indicator\r | |
182 | ALSI, 32, // Current ALS illuminance reading\r | |
183 | BCLP, 32, // Backlight brightness\r | |
184 | PFIT, 32, // Panel fitting state or request\r | |
185 | CBLV, 32, // Current brightness level\r | |
186 | BCLM, 320, // Backlight brightness level duty cycle mapping table\r | |
187 | CPFM, 32, // Current panel fitting mode\r | |
188 | EPFM, 32, // Enabled panel fitting modes\r | |
189 | PLUT, 592, // Optional. 74-byte Panel LUT Table\r | |
190 | PFMB, 32, // Optional. PWM Frequency and Minimum Brightness\r | |
191 | CCDV, 32, // Optional. Gamma, Brightness, Contrast values.\r | |
192 | PCFT, 32, // Optional. Power Conservation Features\r | |
193 | \r | |
194 | Offset(0x3B6),\r | |
195 | STAT, 32, // Status register\r | |
196 | \r | |
197 | // OpRegion Mailbox 4 (VBT)\r | |
198 | \r | |
199 | Offset(0x400),\r | |
200 | GVD1, 0xC000, // 6K bytes maximum VBT image\r | |
201 | \r | |
202 | // OpRegion Mailbox 5 (BIOS to Driver Notification Extension)\r | |
203 | \r | |
204 | Offset(0x1C00),\r | |
205 | PHED, 32, // Panel Header\r | |
206 | BDDC, 2048, // Panel EDID (Max 256 bytes)\r | |
207 | \r | |
208 | }\r | |
209 | \r | |
210 | \r | |
211 | \r | |
212 | // Convert boot display type into a port mask.\r | |
213 | \r | |
214 | Name (DBTB, Package()\r | |
215 | {\r | |
216 | 0x0000, // Automatic\r | |
217 | 0x0007, // Port-0 : Integrated CRT\r | |
218 | 0x0038, // Port-1 : DVO-A, or Integrated LVDS\r | |
219 | 0x01C0, // Port-2 : SDVO-B, or SDVO-B/C\r | |
220 | 0x0E00, // Port-3 : SDVO-C\r | |
221 | 0x003F, // [CRT + DVO-A / Integrated LVDS]\r | |
222 | 0x01C7, // [CRT + SDVO-B] or [CRT + SDVO-B/C]\r | |
223 | 0x0E07, // [CRT + SDVO-C]\r | |
224 | 0x01F8, // [DVO-A / Integrated LVDS + SDVO-B]\r | |
225 | 0x0E38, // [DVO-A / Integrated LVDS + SDVO-C]\r | |
226 | 0x0FC0, // [SDVO-B + SDVO-C]\r | |
227 | 0x0000, // Reserved\r | |
228 | 0x0000, // Reserved\r | |
229 | 0x0000, // Reserved\r | |
230 | 0x0000, // Reserved\r | |
231 | 0x0000, // Reserved\r | |
232 | 0x7000, // Port-4: Integrated TV\r | |
233 | 0x7007, // [Integrated TV + CRT]\r | |
234 | 0x7038, // [Integrated TV + LVDS]\r | |
235 | 0x71C0, // [Integrated TV + DVOB]\r | |
236 | 0x7E00 // [Integrated TV + DVOC]\r | |
237 | })\r | |
238 | \r | |
239 | // Core display clock value table.\r | |
240 | \r | |
241 | Name (CDCT, Package()\r | |
242 | {\r | |
243 | Package() {160},\r | |
244 | Package() {200},\r | |
245 | Package() {267},\r | |
246 | Package() {320},\r | |
247 | Package() {356},\r | |
248 | Package() {400},\r | |
249 | })\r | |
250 | \r | |
251 | // Defined exit result values:\r | |
252 | \r | |
253 | Name (SUCC, 1) // Exit result: Success\r | |
254 | Name (NVLD, 2) // Exit result: Invalid parameter\r | |
255 | Name (CRIT, 4) // Exit result: Critical failure\r | |
256 | Name (NCRT, 6) // Exit result: Non-critical failure\r | |
257 | \r | |
258 | \r | |
259 | /************************************************************************;\r | |
260 | ;*\r | |
261 | ;* Name: GSCI\r | |
262 | ;*\r | |
263 | ;* Description: Handles an SCI generated by the graphics driver. The\r | |
264 | ;* PARM and SCIC input fields are parsed to determine the\r | |
265 | ;* functionality requested by the driver. GBDA or SBCB\r | |
266 | ;* is called based on the input data in SCIC.\r | |
267 | ;*\r | |
268 | ;* Usage: The method must be called in response to a GPE 06 event\r | |
269 | ;* which will be generated by the graphics driver.\r | |
270 | ;* Ex: Method(\_GPE._L06) {Return(\_SB.PCI0.GFX0.GSCI())}\r | |
271 | ;*\r | |
272 | ;* Input: PARM and SCIC are indirect inputs\r | |
273 | ;*\r | |
274 | ;* Output: PARM and SIC are indirect outputs\r | |
275 | ;*\r | |
276 | ;* References: GBDA (Get BIOS Data method), SBCB (System BIOS Callback\r | |
277 | ;* method)\r | |
278 | ;*\r | |
279 | ;************************************************************************/\r | |
280 | \r | |
281 | Method (GSCI, 0, Serialized)\r | |
282 | {\r | |
283 | Include("IgdOGBDA.ASL") // "Get BIOS Data" Functions\r | |
284 | Include("IgdOSBCB.ASL") // "System BIOS CallBacks"\r | |
285 | \r | |
286 | If (LEqual(GEFC, 4))\r | |
287 | {\r | |
288 | Store(GBDA(), GXFC) // Process Get BIOS Data functions\r | |
289 | }\r | |
290 | \r | |
291 | If (LEqual(GEFC, 6))\r | |
292 | {\r | |
293 | Store(SBCB(), GXFC) // Process BIOS Callback functions\r | |
294 | }\r | |
295 | \r | |
296 | Store(0, GEFC) // Wipe out the entry function code\r | |
297 | Store(1, SCIS) // Clear the GUNIT SCI status bit in PCH ACPI I/O space.\r | |
298 | Store(0, GSSE) // Clear the SCI generation bit in PCI space.\r | |
299 | Store(0, SCIE) // Clr SCI serviced bit to signal completion\r | |
300 | \r | |
301 | Return(Zero)\r | |
302 | }\r | |
303 | \r | |
304 | // Include MOBLFEAT.ASL for mobile systems only. Remove for desktop.\r | |
305 | Include("IgdOMOBF.ASL") // IGD SCI mobile features\r |