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1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __I2C_HOST_H__\r | |
17 | #define __I2C_HOST_H__\r | |
18 | \r | |
19 | #include <Protocol/I2cMasterMcg.h>\r | |
20 | \r | |
21 | /**\r | |
22 | Declare the forward references\r | |
23 | \r | |
24 | **/\r | |
25 | typedef struct _EFI_I2C_HOST_PROTOCOL EFI_I2C_HOST_PROTOCOL;\r | |
26 | typedef struct _EFI_I2C_HOST_CALLBACKS EFI_I2C_HOST_CALLBACKS;\r | |
27 | \r | |
28 | \r | |
29 | /**\r | |
30 | Queue an I2C operation for execution on the I2C controller.\r | |
31 | \r | |
32 | This routine must be called at or below TPL_NOTIFY. For synchronous\r | |
33 | requests this routine must be called at or below TPL_CALLBACK.\r | |
34 | \r | |
35 | N.B. The typical consumers of this API are the I2C bus driver and\r | |
36 | on rare occasions the I2C test application. Extreme care must be\r | |
37 | taken by other consumers of this API to prevent confusing the\r | |
38 | third party I2C drivers due to a state change at the I2C device\r | |
39 | which the third party I2C drivers did not initiate. I2C platform\r | |
40 | drivers may use this API within these guidelines.\r | |
41 | \r | |
42 | This layer uses the concept of I2C bus configurations to describe\r | |
43 | the I2C bus. An I2C bus configuration is defined as a unique\r | |
44 | setting of the multiplexers and switches in the I2C bus which\r | |
45 | enable access to one or more I2C devices. When using a switch\r | |
46 | to divide a bus, due to speed differences, the I2C platform layer\r | |
47 | would define an I2C bus configuration for the I2C devices on each\r | |
48 | side of the switch. When using a multiplexer, the I2C platform\r | |
49 | layer defines an I2C bus configuration for each of the selector\r | |
50 | values required to control the multiplexer. See Figure 1 in the\r | |
51 | <a href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I<sup>2</sup>C\r | |
52 | Specification</a> for a complex I2C bus configuration.\r | |
53 | \r | |
54 | The I2C host driver processes all operations in FIFO order. Prior to\r | |
55 | performing the operation, the I2C host driver calls the I2C platform\r | |
56 | driver to reconfigure the switches and multiplexers in the I2C bus\r | |
57 | enabling access to the specified I2C device. The I2C platform driver\r | |
58 | also selects the maximum bus speed for the device. After the I2C bus\r | |
59 | is configured, the I2C host driver calls the I2C port driver to\r | |
60 | initialize the I2C controller and start the I2C operation.\r | |
61 | \r | |
62 | @param[in] This Address of an EFI_I2C_HOST_PROTOCOL instance.\r | |
63 | @param[in] I2cBusConfiguration I2C bus configuration to access the I2C\r | |
64 | device.\r | |
65 | @param[in] SlaveAddress Address of the device on the I2C bus.\r | |
66 | @param[in] Event Event to set for asynchronous operations,\r | |
67 | NULL for synchronous operations\r | |
68 | @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET\r | |
69 | structure describing the I2C operation\r | |
70 | @param[out] I2cStatus Optional buffer to receive the I2C operation\r | |
71 | completion status\r | |
72 | \r | |
73 | @retval EFI_SUCCESS The operation completed successfully.\r | |
74 | @retval EFI_ABORTED The request did not complete because the driver\r | |
75 | was shutdown.\r | |
76 | @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large.\r | |
77 | @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation.\r | |
78 | This could indicate the slave device is not present.\r | |
79 | @retval EFI_INVALID_PARAMETER RequestPacket is NULL\r | |
80 | @retval EFI_INVALID_PARAMETER TPL is too high\r | |
81 | @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value\r | |
82 | @retval EFI_NO_RESPONSE The I2C device is not responding to the\r | |
83 | slave address. EFI_DEVICE_ERROR may also be\r | |
84 | returned if the controller cannot distinguish\r | |
85 | when the NACK occurred.\r | |
86 | @retval EFI_NOT_FOUND I2C slave address exceeds maximum address\r | |
87 | @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for\r | |
88 | the event and then read status pointed to by\r | |
89 | the request packet.\r | |
90 | @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation\r | |
91 | @retval EFI_TIMEOUT The transaction did not complete within an internally\r | |
92 | specified timeout period.\r | |
93 | \r | |
94 | **/\r | |
95 | typedef\r | |
96 | EFI_STATUS\r | |
97 | (EFIAPI *EFI_I2C_HOST_QUEUE_REQUEST) (\r | |
98 | IN CONST EFI_I2C_HOST_PROTOCOL *This,\r | |
99 | IN UINTN I2cBusConfiguration,\r | |
100 | IN UINTN SlaveAddress,\r | |
101 | IN EFI_EVENT Event OPTIONAL,\r | |
102 | IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,\r | |
103 | OUT EFI_STATUS *I2cStatus OPTIONAL\r | |
104 | );\r | |
105 | \r | |
106 | ///\r | |
107 | /// Host access to the I2C bus.\r | |
108 | ///\r | |
109 | struct _EFI_I2C_HOST_PROTOCOL {\r | |
110 | ///\r | |
111 | /// Queue an operation for execution on the I2C bus\r | |
112 | ///\r | |
113 | EFI_I2C_HOST_QUEUE_REQUEST QueueRequest;\r | |
114 | \r | |
115 | ///\r | |
116 | /// The maximum number of I2C bus configurations\r | |
117 | ///\r | |
118 | UINTN I2cBusConfigurationCount;\r | |
119 | \r | |
120 | ///\r | |
121 | /// The maximum number of bytes the I2C host controller\r | |
122 | /// is able to receive from the I2C bus.\r | |
123 | ///\r | |
124 | UINT32 MaximumReceiveBytes;\r | |
125 | \r | |
126 | ///\r | |
127 | /// The maximum number of bytes the I2C host controller\r | |
128 | /// is able to send on the I2C bus.\r | |
129 | ///\r | |
130 | UINT32 MaximumTransmitBytes;\r | |
131 | \r | |
132 | ///\r | |
133 | /// The maximum number of bytes in the I2C bus transaction.\r | |
134 | ///\r | |
135 | UINT32 MaximumTotalBytes;\r | |
136 | };\r | |
137 | \r | |
138 | ///\r | |
139 | /// GUID for the EFI_I2C_HOST_PROTOCOL\r | |
140 | ///\r | |
141 | extern EFI_GUID gEfiI2cHostProtocolGuid;\r | |
142 | \r | |
143 | #endif // __I2C_HOST_H__\r |