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1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | \r | |
14 | Module Name:\r | |
15 | \r | |
16 | SioInit.c\r | |
17 | \r | |
18 | Abstract:\r | |
19 | \r | |
20 | Functions for LpcSio initialization\r | |
21 | \r | |
22 | --*/\r | |
23 | \r | |
24 | #include "PlatformSerialPortLib.h"\r | |
25 | #include "SioInit.h"\r | |
26 | \r | |
27 | typedef struct {\r | |
28 | UINT8 Register;\r | |
29 | UINT8 Value;\r | |
30 | } EFI_SIO_TABLE;\r | |
31 | \r | |
32 | EFI_SIO_TABLE mSioTableWpcn381u[] = {\r | |
33 | {0x29, 0x0A0},\r | |
34 | {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device\r | |
35 | {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB\r | |
36 | {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB\r | |
37 | {WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4\r | |
38 | {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r | |
39 | {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device\r | |
40 | {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB\r | |
41 | {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB\r | |
42 | {WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3\r | |
43 | {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r | |
44 | {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device\r | |
45 | {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB\r | |
46 | {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB\r | |
47 | {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r | |
48 | {0x21, 0x001}, // Global Device Enable\r | |
49 | {0x26, 0x000}\r | |
50 | };\r | |
51 | \r | |
52 | EFI_SIO_TABLE mSioTableWdcp376[] = {\r | |
53 | {0x29, 0x0A0},\r | |
54 | {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0}, // Select UART0 device\r | |
55 | {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)}, // Set Base Address MSB\r | |
56 | {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB\r | |
57 | {WPCN381U_IRQ1_REGISTER, 0x014}, // Set to IRQ4\r | |
58 | {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r | |
59 | {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1}, // Select UART1 device\r | |
60 | {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)}, // Set Base Address MSB\r | |
61 | {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB\r | |
62 | {WPCN381U_IRQ1_REGISTER, 0x013}, // Set to IRQ3\r | |
63 | {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r | |
64 | {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO}, // Select GPIO device\r | |
65 | {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)}, // Set Base Address MSB\r | |
66 | {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)}, // Set Base Address LSB\r | |
67 | {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r | |
68 | {0x21, 0x001}, // Global Device Enable\r | |
69 | {0x26, 0x000},\r | |
70 | {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2K}, // Select PS2 Keyboard\r | |
71 | {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS >> 8)}, // Set Base Address MSB\r | |
72 | {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS & 0x00FF)}, // Set Base Address LSB\r | |
73 | {WPCN381U_BASE2_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS >> 8)}, // Set Base Address MSB\r | |
74 | {WPCN381U_BASE2_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS & 0x00FF)}, // Set Base Address LSB\r | |
75 | {WPCN381U_IRQ1_REGISTER, 0x011}, // Set to IRQ1\r | |
76 | {0xF0, (SIO_KBC_CLOCK << 6)}, // Select KBC Clock Source\r | |
77 | {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}, // Enable it with Activation bit\r | |
78 | {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2M}, // Select PS2 Mouse\r | |
79 | {WPCN381U_IRQ1_REGISTER, 0x01c}, // Set to IRQ12\r | |
80 | {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE} // Enable it with Activation bit\r | |
81 | };\r | |
82 | \r | |
83 | /**\r | |
84 | Initialization for SIO.\r | |
85 | \r | |
86 | @param FfsHeader FV this PEIM was loaded from.\r | |
87 | @param PeiServices General purpose services available to every PEIM.\r | |
88 | \r | |
89 | None\r | |
90 | \r | |
91 | **/\r | |
92 | VOID\r | |
93 | InitializeSio (\r | |
94 | VOID\r | |
95 | )\r | |
96 | {\r | |
97 | UINT16 Index;\r | |
98 | UINT16 IndexPort;\r | |
99 | UINT16 DataPort;\r | |
100 | \r | |
101 | //\r | |
102 | // Super I/O initialization for Winbond WPCN381U\r | |
103 | //\r | |
104 | IndexPort = WPCN381U_CONFIG_INDEX;\r | |
105 | DataPort = WPCN381U_CONFIG_DATA;\r | |
106 | \r | |
107 | //\r | |
108 | // Check for Winbond WPCN381U\r | |
109 | //\r | |
110 | IoWrite8 (IndexPort, WPCN381U_DEV_ID_REGISTER); // Winbond WPCN381U Device ID register is 0x20\r | |
111 | \r | |
112 | if (IoRead8 (DataPort) == WPCN381U_CHIP_ID) { // Winbond WPCN381U Device ID is 0xF4\r | |
113 | //\r | |
114 | // Configure WPCN381U SIO\r | |
115 | //\r | |
116 | for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {\r | |
117 | IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);\r | |
118 | IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);\r | |
119 | }\r | |
120 | }\r | |
121 | \r | |
122 | if (IoRead8 (DataPort) == WDCP376_CHIP_ID) { // Winbond WDCP376 Device ID is 0xF1\r | |
123 | //\r | |
124 | // Configure WDCP376 SIO\r | |
125 | //\r | |
126 | for (Index = 0; Index < sizeof (mSioTableWdcp376) / sizeof (EFI_SIO_TABLE); Index++) {\r | |
127 | IoWrite8 (IndexPort, mSioTableWdcp376[Index].Register);\r | |
128 | IoWrite8 (DataPort, mSioTableWdcp376[Index].Value);\r | |
129 | }\r | |
130 | }\r | |
131 | return;\r | |
132 | }\r |