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3cbfba02 DW |
1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | \r | |
17 | #ifndef _EFI_PCI_BUS_H_\r | |
18 | #define _EFI_PCI_BUS_H_\r | |
19 | \r | |
20 | #include <PiDxe.h>\r | |
21 | \r | |
22 | #include <Protocol/LoadedImage.h>\r | |
23 | #include <Protocol/PciHostBridgeResourceAllocation.h>\r | |
24 | #include <Protocol/PciIo.h>\r | |
25 | #include <Protocol/LoadFile2.h>\r | |
26 | #include <Protocol/PciRootBridgeIo.h>\r | |
27 | #include <Protocol/PciHotPlugRequest.h>\r | |
28 | #include <Protocol/DevicePath.h>\r | |
29 | #include <Protocol/PciPlatform.h>\r | |
30 | #include <Protocol/PciHotPlugInit.h>\r | |
31 | #include <Protocol/Decompress.h>\r | |
32 | #include <Protocol/BusSpecificDriverOverride.h>\r | |
33 | #include <Protocol/IncompatiblePciDeviceSupport.h>\r | |
34 | #include <Protocol/PciOverride.h>\r | |
35 | #include <Protocol/PciEnumerationComplete.h>\r | |
36 | \r | |
37 | #include <Library/DebugLib.h>\r | |
38 | #include <Library/UefiDriverEntryPoint.h>\r | |
39 | #include <Library/BaseLib.h>\r | |
40 | #include <Library/UefiLib.h>\r | |
41 | #include <Library/BaseMemoryLib.h>\r | |
42 | #include <Library/ReportStatusCodeLib.h>\r | |
43 | #include <Library/MemoryAllocationLib.h>\r | |
44 | #include <Library/UefiBootServicesTableLib.h>\r | |
45 | #include <Library/DevicePathLib.h>\r | |
46 | #include <Library/PcdLib.h>\r | |
47 | #include <Library/PeCoffLib.h>\r | |
48 | \r | |
49 | #include <IndustryStandard/Pci.h>\r | |
50 | #include <IndustryStandard/PeImage.h>\r | |
51 | #include <IndustryStandard/Acpi.h>\r | |
52 | \r | |
53 | typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE;\r | |
54 | typedef struct _PCI_BAR PCI_BAR;\r | |
55 | \r | |
56 | #define EFI_PCI_RID(Bus, Device, Function) (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)\r | |
57 | #define EFI_PCI_BUS_OF_RID(RID) ((UINT32)RID >> 8)\r | |
58 | \r | |
59 | #define EFI_PCI_IOV_POLICY_ARI 0x0001\r | |
60 | #define EFI_PCI_IOV_POLICY_SRIOV 0x0002\r | |
61 | #define EFI_PCI_IOV_POLICY_MRIOV 0x0004\r | |
62 | \r | |
63 | typedef enum {\r | |
64 | PciBarTypeUnknown = 0,\r | |
65 | PciBarTypeIo16,\r | |
66 | PciBarTypeIo32,\r | |
67 | PciBarTypeMem32,\r | |
68 | PciBarTypePMem32,\r | |
69 | PciBarTypeMem64,\r | |
70 | PciBarTypePMem64,\r | |
71 | PciBarTypeIo,\r | |
72 | PciBarTypeMem,\r | |
73 | PciBarTypeMaxType\r | |
74 | } PCI_BAR_TYPE;\r | |
75 | \r | |
76 | \r | |
77 | #define VGABASE1 0x3B0\r | |
78 | #define VGALIMIT1 0x3BB\r | |
79 | \r | |
80 | #define VGABASE2 0x3C0\r | |
81 | #define VGALIMIT2 0x3DF\r | |
82 | \r | |
83 | #define ISABASE 0x100\r | |
84 | #define ISALIMIT 0x3FF\r | |
85 | \r | |
86 | //\r | |
87 | // PCI BAR parameters\r | |
88 | //\r | |
89 | struct _PCI_BAR {\r | |
90 | UINT64 BaseAddress;\r | |
91 | UINT64 Length;\r | |
92 | UINT64 Alignment;\r | |
93 | PCI_BAR_TYPE BarType;\r | |
94 | BOOLEAN Prefetchable;\r | |
95 | UINT8 MemType;\r | |
96 | UINT16 Offset;\r | |
97 | };\r | |
98 | \r | |
99 | //\r | |
100 | // defined in PCI Card Specification, 8.0\r | |
101 | //\r | |
102 | #define PCI_CARD_MEMORY_BASE_0 0x1C\r | |
103 | #define PCI_CARD_MEMORY_LIMIT_0 0x20\r | |
104 | #define PCI_CARD_MEMORY_BASE_1 0x24\r | |
105 | #define PCI_CARD_MEMORY_LIMIT_1 0x28\r | |
106 | #define PCI_CARD_IO_BASE_0_LOWER 0x2C\r | |
107 | #define PCI_CARD_IO_BASE_0_UPPER 0x2E\r | |
108 | #define PCI_CARD_IO_LIMIT_0_LOWER 0x30\r | |
109 | #define PCI_CARD_IO_LIMIT_0_UPPER 0x32\r | |
110 | #define PCI_CARD_IO_BASE_1_LOWER 0x34\r | |
111 | #define PCI_CARD_IO_BASE_1_UPPER 0x36\r | |
112 | #define PCI_CARD_IO_LIMIT_1_LOWER 0x38\r | |
113 | #define PCI_CARD_IO_LIMIT_1_UPPER 0x3A\r | |
114 | #define PCI_CARD_BRIDGE_CONTROL 0x3E\r | |
115 | \r | |
116 | #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r | |
117 | #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r | |
118 | \r | |
119 | #define PPB_BAR_0 0\r | |
120 | #define PPB_BAR_1 1\r | |
121 | #define PPB_IO_RANGE 2\r | |
122 | #define PPB_MEM32_RANGE 3\r | |
123 | #define PPB_PMEM32_RANGE 4\r | |
124 | #define PPB_PMEM64_RANGE 5\r | |
125 | #define PPB_MEM64_RANGE 0xFF\r | |
126 | \r | |
127 | #define P2C_BAR_0 0\r | |
128 | #define P2C_MEM_1 1\r | |
129 | #define P2C_MEM_2 2\r | |
130 | #define P2C_IO_1 3\r | |
131 | #define P2C_IO_2 4\r | |
132 | \r | |
133 | #define EFI_BRIDGE_IO32_DECODE_SUPPORTED 0x0001\r | |
134 | #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED 0x0002\r | |
135 | #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED 0x0004\r | |
136 | #define EFI_BRIDGE_IO16_DECODE_SUPPORTED 0x0008\r | |
137 | #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r | |
138 | #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED 0x0020\r | |
139 | #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED 0x0040\r | |
140 | \r | |
141 | #define PCI_MAX_HOST_BRIDGE_NUM 0x0010\r | |
142 | \r | |
143 | //\r | |
144 | // Define option for attribute\r | |
145 | //\r | |
146 | #define EFI_SET_SUPPORTS 0\r | |
147 | #define EFI_SET_ATTRIBUTES 1\r | |
148 | \r | |
149 | #define PCI_IO_DEVICE_SIGNATURE SIGNATURE_32 ('p', 'c', 'i', 'o')\r | |
150 | \r | |
151 | struct _PCI_IO_DEVICE {\r | |
152 | UINT32 Signature;\r | |
153 | EFI_HANDLE Handle;\r | |
154 | EFI_PCI_IO_PROTOCOL PciIo;\r | |
155 | LIST_ENTRY Link;\r | |
156 | \r | |
157 | EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r | |
158 | EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r | |
159 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r | |
160 | EFI_LOAD_FILE2_PROTOCOL LoadFile2;\r | |
161 | \r | |
162 | //\r | |
163 | // PCI configuration space header type\r | |
164 | //\r | |
165 | PCI_TYPE00 Pci;\r | |
166 | \r | |
167 | //\r | |
168 | // Bus number, Device number, Function number\r | |
169 | //\r | |
170 | UINT8 BusNumber;\r | |
171 | UINT8 DeviceNumber;\r | |
172 | UINT8 FunctionNumber;\r | |
173 | \r | |
174 | //\r | |
175 | // BAR for this PCI Device\r | |
176 | //\r | |
177 | PCI_BAR PciBar[PCI_MAX_BAR];\r | |
178 | \r | |
179 | //\r | |
180 | // The bridge device this pci device is subject to\r | |
181 | //\r | |
182 | PCI_IO_DEVICE *Parent;\r | |
183 | \r | |
184 | //\r | |
185 | // A linked list for children Pci Device if it is bridge device\r | |
186 | //\r | |
187 | LIST_ENTRY ChildList;\r | |
188 | \r | |
189 | //\r | |
2e182e30 | 190 | // TRUE if the PCI bus driver creates the handle for this PCI device\r |
3cbfba02 DW |
191 | //\r |
192 | BOOLEAN Registered;\r | |
193 | \r | |
194 | //\r | |
195 | // TRUE if the PCI bus driver successfully allocates the resource required by\r | |
196 | // this PCI device\r | |
197 | //\r | |
198 | BOOLEAN Allocated;\r | |
199 | \r | |
200 | //\r | |
201 | // The attribute this PCI device currently set\r | |
202 | //\r | |
203 | UINT64 Attributes;\r | |
204 | \r | |
205 | //\r | |
206 | // The attributes this PCI device actually supports\r | |
207 | //\r | |
208 | UINT64 Supports;\r | |
209 | \r | |
210 | //\r | |
211 | // The resource decode the bridge supports\r | |
212 | //\r | |
213 | UINT32 Decodes;\r | |
214 | \r | |
215 | //\r | |
216 | // TRUE if the ROM image is from the PCI Option ROM BAR\r | |
217 | //\r | |
218 | BOOLEAN EmbeddedRom;\r | |
219 | \r | |
220 | //\r | |
221 | // The OptionRom Size\r | |
222 | //\r | |
223 | UINT64 RomSize;\r | |
224 | \r | |
225 | //\r | |
226 | // The OptionRom Size\r | |
227 | //\r | |
228 | UINT64 RomBase;\r | |
229 | \r | |
230 | //\r | |
231 | // TRUE if all OpROM (in device or in platform specific position) have been processed\r | |
232 | //\r | |
233 | BOOLEAN AllOpRomProcessed;\r | |
234 | \r | |
235 | //\r | |
236 | // TRUE if there is any EFI driver in the OptionRom\r | |
237 | //\r | |
238 | BOOLEAN BusOverride;\r | |
239 | \r | |
240 | //\r | |
241 | // A list tracking reserved resource on a bridge device\r | |
242 | //\r | |
243 | LIST_ENTRY ReservedResourceList;\r | |
244 | \r | |
245 | //\r | |
246 | // A list tracking image handle of platform specific overriding driver\r | |
247 | //\r | |
248 | LIST_ENTRY OptionRomDriverList;\r | |
249 | \r | |
250 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ResourcePaddingDescriptors;\r | |
251 | EFI_HPC_PADDING_ATTRIBUTES PaddingAttributes;\r | |
252 | \r | |
253 | BOOLEAN IsPciExp;\r | |
254 | \r | |
255 | //\r | |
256 | // For SR-IOV\r | |
257 | //\r | |
258 | UINT8 PciExpressCapabilityOffset;\r | |
259 | UINT32 AriCapabilityOffset;\r | |
260 | UINT32 SrIovCapabilityOffset;\r | |
261 | UINT32 MrIovCapabilityOffset;\r | |
262 | PCI_BAR VfPciBar[PCI_MAX_BAR];\r | |
263 | UINT32 SystemPageSize;\r | |
264 | UINT16 InitialVFs;\r | |
265 | UINT16 ReservedBusNum;\r | |
266 | \r | |
267 | //\r | |
268 | // Per PCI to PCI Bridge spec, I/O window is 4K aligned,\r | |
2e182e30 | 269 | // but some chipsets support non-standard I/O window alignments less than 4K.\r |
3cbfba02 DW |
270 | // This field is used to support this case.\r |
271 | //\r | |
272 | UINT16 BridgeIoAlignment;\r | |
273 | };\r | |
274 | \r | |
275 | #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r | |
276 | CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r | |
277 | \r | |
278 | #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r | |
279 | CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r | |
280 | \r | |
281 | #define PCI_IO_DEVICE_FROM_LINK(a) \\r | |
282 | CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r | |
283 | \r | |
284 | #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r | |
285 | CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r | |
286 | \r | |
287 | \r | |
288 | \r | |
289 | //\r | |
290 | // Global Variables\r | |
291 | //\r | |
292 | extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;\r | |
293 | extern EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding;\r | |
294 | extern EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName;\r | |
295 | extern EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2;\r | |
296 | extern BOOLEAN gFullEnumeration;\r | |
297 | extern UINTN gPciHostBridgeNumber;\r | |
298 | extern EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r | |
299 | extern UINT64 gAllOne;\r | |
300 | extern UINT64 gAllZero;\r | |
301 | extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol;\r | |
302 | extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol;\r | |
303 | extern BOOLEAN mReserveIsaAliases;\r | |
304 | extern BOOLEAN mReserveVgaAliases;\r | |
305 | \r | |
306 | /**\r | |
307 | Macro that checks whether device is a GFX device.\r | |
308 | \r | |
309 | @param _p Specified device.\r | |
310 | \r | |
2e182e30 GL |
311 | @retval TRUE Device is a GFX device.\r |
312 | @retval FALSE Device is not a GFX device.\r | |
3cbfba02 DW |
313 | \r |
314 | **/\r | |
315 | #define IS_PCI_GFX(_p) IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r | |
316 | \r | |
317 | /**\r | |
318 | Test to see if this driver supports ControllerHandle. Any ControllerHandle\r | |
319 | than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r | |
320 | \r | |
321 | @param This Protocol instance pointer.\r | |
322 | @param Controller Handle of device to test.\r | |
2e182e30 | 323 | @param RemainingDevicePath Optional parameter use to pick a specific child\r |
3cbfba02 DW |
324 | device to start.\r |
325 | \r | |
326 | @retval EFI_SUCCESS This driver supports this device.\r | |
327 | @retval EFI_ALREADY_STARTED This driver is already running on this device.\r | |
328 | @retval other This driver does not support this device.\r | |
329 | \r | |
330 | **/\r | |
331 | EFI_STATUS\r | |
332 | EFIAPI\r | |
333 | PciBusDriverBindingSupported (\r | |
334 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
335 | IN EFI_HANDLE Controller,\r | |
336 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
337 | );\r | |
338 | \r | |
339 | /**\r | |
340 | Start this driver on ControllerHandle and enumerate Pci bus and start\r | |
341 | all device under PCI bus.\r | |
342 | \r | |
343 | @param This Protocol instance pointer.\r | |
344 | @param Controller Handle of device to bind driver to.\r | |
2e182e30 | 345 | @param RemainingDevicePath Optional parameter use to pick a specific child\r |
3cbfba02 DW |
346 | device to start.\r |
347 | \r | |
348 | @retval EFI_SUCCESS This driver is added to ControllerHandle.\r | |
349 | @retval EFI_ALREADY_STARTED This driver is already running on ControllerHandle.\r | |
350 | @retval other This driver does not support this device.\r | |
351 | \r | |
352 | **/\r | |
353 | EFI_STATUS\r | |
354 | EFIAPI\r | |
355 | PciBusDriverBindingStart (\r | |
356 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
357 | IN EFI_HANDLE Controller,\r | |
358 | IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r | |
359 | );\r | |
360 | \r | |
361 | /**\r | |
2e182e30 | 362 | Stop this driver on ControllerHandle. Support stopping any child handles\r |
3cbfba02 DW |
363 | created by this driver.\r |
364 | \r | |
365 | @param This Protocol instance pointer.\r | |
366 | @param Controller Handle of device to stop driver on.\r | |
367 | @param NumberOfChildren Number of Handles in ChildHandleBuffer. If number of\r | |
368 | children is zero stop the entire bus driver.\r | |
369 | @param ChildHandleBuffer List of Child Handles to Stop.\r | |
370 | \r | |
371 | @retval EFI_SUCCESS This driver is removed ControllerHandle.\r | |
372 | @retval other This driver was not removed from this device.\r | |
373 | \r | |
374 | **/\r | |
375 | EFI_STATUS\r | |
376 | EFIAPI\r | |
377 | PciBusDriverBindingStop (\r | |
378 | IN EFI_DRIVER_BINDING_PROTOCOL *This,\r | |
379 | IN EFI_HANDLE Controller,\r | |
380 | IN UINTN NumberOfChildren,\r | |
381 | IN EFI_HANDLE *ChildHandleBuffer\r | |
382 | );\r | |
383 | \r | |
384 | #endif\r |