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1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | \r | |
14 | Module Name:\r | |
15 | \r | |
16 | MemoryCallback.c\r | |
17 | \r | |
18 | Abstract:\r | |
19 | \r | |
20 | EFI 2.0 PEIM to provide the platform support functionality on the Bridgeport.\r | |
21 | \r | |
22 | --*/\r | |
23 | \r | |
24 | #include "PlatformEarlyInit.h"\r | |
25 | \r | |
26 | \r | |
27 | VOID\r | |
28 | UpdateDefaultSetupValue (\r | |
29 | IN EFI_PLATFORM_INFO_HOB *PlatformInfo\r | |
30 | )\r | |
31 | {\r | |
32 | return;\r | |
33 | }\r | |
34 | \r | |
35 | /**\r | |
36 | PEI termination callback.\r | |
37 | \r | |
38 | @param PeiServices General purpose services available to every PEIM.\r | |
39 | @param NotifyDescriptor Not uesed.\r | |
40 | @param Ppi Not uesed.\r | |
41 | \r | |
42 | @retval EFI_SUCCESS If the interface could be successfully\r | |
43 | installed.\r | |
44 | \r | |
45 | **/\r | |
46 | EFI_STATUS\r | |
47 | EFIAPI \r | |
48 | EndOfPeiPpiNotifyCallback (\r | |
49 | IN CONST EFI_PEI_SERVICES **PeiServices,\r | |
50 | IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r | |
51 | IN VOID *Ppi\r | |
52 | )\r | |
53 | {\r | |
54 | EFI_STATUS Status;\r | |
55 | UINT64 MemoryTop;\r | |
56 | UINT64 LowUncableBase;\r | |
57 | EFI_PLATFORM_INFO_HOB *PlatformInfo;\r | |
58 | UINT32 HecBaseHigh;\r | |
59 | EFI_BOOT_MODE BootMode;\r | |
60 | EFI_PEI_HOB_POINTERS Hob;\r | |
61 | \r | |
62 | Status = (*PeiServices)->GetBootMode(\r | |
63 | PeiServices,\r | |
64 | &BootMode\r | |
65 | );\r | |
66 | \r | |
67 | ASSERT_EFI_ERROR (Status);\r | |
68 | \r | |
69 | //\r | |
70 | // Set the some PCI and chipset range as UC\r | |
71 | // And align to 1M at leaset\r | |
72 | //\r | |
73 | Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r | |
74 | ASSERT (Hob.Raw != NULL);\r | |
75 | PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r | |
76 | \r | |
77 | UpdateDefaultSetupValue (PlatformInfo);\r | |
78 | \r | |
79 | DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", PlatformInfo->MemData.MemTolm));\r | |
80 | DEBUG ((EFI_D_ERROR, "PCIE OSBASE: %lX\n", PlatformInfo->PciData.PciExpressBase));\r | |
81 | DEBUG (\r | |
82 | (EFI_D_ERROR,\r | |
83 | "PCIE BASE: %lX Size : %X\n",\r | |
84 | PlatformInfo->PciData.PciExpressBase,\r | |
85 | PlatformInfo->PciData.PciExpressSize)\r | |
86 | );\r | |
87 | DEBUG (\r | |
88 | (EFI_D_ERROR,\r | |
89 | "PCI32 BASE: %X Limit: %X\n",\r | |
90 | PlatformInfo->PciData.PciResourceMem32Base,\r | |
91 | PlatformInfo->PciData.PciResourceMem32Limit)\r | |
92 | );\r | |
93 | DEBUG (\r | |
94 | (EFI_D_ERROR,\r | |
95 | "PCI64 BASE: %lX Limit: %lX\n",\r | |
96 | PlatformInfo->PciData.PciResourceMem64Base,\r | |
97 | PlatformInfo->PciData.PciResourceMem64Limit)\r | |
98 | );\r | |
99 | DEBUG ((EFI_D_ERROR, "UC START: %lX End : %lX\n", PlatformInfo->MemData.MemMir0, PlatformInfo->MemData.MemMir1));\r | |
100 | \r | |
101 | LowUncableBase = PlatformInfo->MemData.MemMaxTolm;\r | |
102 | LowUncableBase &= (0x0FFF00000);\r | |
103 | MemoryTop = (0x100000000);\r | |
104 | \r | |
105 | if (BootMode != BOOT_ON_S3_RESUME) {\r | |
106 | //\r | |
107 | // In BIOS, HECBASE will be always below 4GB\r | |
108 | //\r | |
109 | HecBaseHigh = (UINT32) RShiftU64 (PlatformInfo->PciData.PciExpressBase, 28);\r | |
110 | ASSERT (HecBaseHigh < 16);\r | |
111 | }\r | |
112 | \r | |
113 | return Status;\r | |
114 | }\r | |
115 | \r | |
116 | /**\r | |
117 | Install Firmware Volume Hob's once there is main memory\r | |
118 | \r | |
119 | @param PeiServices General purpose services available to every PEIM.\r | |
120 | @param NotifyDescriptor Notify that this module published.\r | |
121 | @param Ppi PPI that was installed.\r | |
122 | \r | |
123 | @retval EFI_SUCCESS The function completed successfully.\r | |
124 | \r | |
125 | **/\r | |
126 | EFI_STATUS\r | |
127 | EFIAPI\r | |
128 | MemoryDiscoveredPpiNotifyCallback (\r | |
129 | IN CONST EFI_PEI_SERVICES **PeiServices,\r | |
130 | IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r | |
131 | IN VOID *Ppi\r | |
132 | )\r | |
133 | {\r | |
134 | EFI_STATUS Status;\r | |
135 | EFI_BOOT_MODE BootMode;\r | |
136 | EFI_CPUID_REGISTER FeatureInfo;\r | |
137 | UINT8 CpuAddressWidth;\r | |
138 | UINT16 Pm1Cnt;\r | |
139 | EFI_PEI_HOB_POINTERS Hob;\r | |
140 | EFI_PLATFORM_INFO_HOB *PlatformInfo;\r | |
141 | UINT32 RootComplexBar;\r | |
142 | UINT32 PmcBase;\r | |
143 | UINT32 IoBase;\r | |
144 | UINT32 IlbBase;\r | |
145 | UINT32 SpiBase;\r | |
146 | UINT32 MphyBase;\r | |
147 | \r | |
148 | //\r | |
149 | // Get Platform Info HOB\r | |
150 | //\r | |
151 | Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r | |
152 | ASSERT (Hob.Raw != NULL);\r | |
153 | PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r | |
154 | \r | |
155 | Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);\r | |
156 | \r | |
157 | //\r | |
158 | // Check if user wants to turn off in PEI phase\r | |
159 | //\r | |
160 | if ((BootMode != BOOT_ON_S3_RESUME) && (BootMode != BOOT_ON_FLASH_UPDATE)) {\r | |
161 | CheckPowerOffNow();\r | |
162 | } else {\r | |
163 | Pm1Cnt = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);\r | |
164 | Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;\r | |
165 | IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r | |
166 | }\r | |
167 | \r | |
168 | #ifndef MINNOW2_FSP_BUILD\r | |
169 | //\r | |
170 | // Set PEI cache mode here\r | |
171 | //\r | |
172 | SetPeiCacheMode (PeiServices);\r | |
173 | #endif\r | |
174 | \r | |
175 | //\r | |
176 | // Pulish memory tyoe info\r | |
177 | //\r | |
178 | PublishMemoryTypeInfo ();\r | |
179 | \r | |
180 | //\r | |
181 | // Work done if on a S3 resume\r | |
182 | //\r | |
183 | if (BootMode == BOOT_ON_S3_RESUME) {\r | |
184 | //\r | |
185 | //Program the side band packet register to send a sideband message to Punit\r | |
186 | //To indicate that DRAM has been initialized and PUNIT FW base address in memory.\r | |
187 | //\r | |
188 | return EFI_SUCCESS;\r | |
189 | }\r | |
190 | \r | |
191 | RootComplexBar = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA ) & B_PCH_LPC_RCBA_BAR;\r | |
192 | BuildResourceDescriptorHob (\r | |
193 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
194 | (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r | |
195 | RootComplexBar,\r | |
196 | 0x1000\r | |
197 | );\r | |
198 | DEBUG ((EFI_D_INFO, "RootComplexBar : 0x%x\n", RootComplexBar));\r | |
199 | \r | |
200 | PmcBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE ) & B_PCH_LPC_PMC_BASE_BAR;\r | |
201 | BuildResourceDescriptorHob (\r | |
202 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
203 | (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r | |
204 | PmcBase,\r | |
205 | 0x1000\r | |
206 | );\r | |
207 | DEBUG ((EFI_D_INFO, "PmcBase : 0x%x\n", PmcBase));\r | |
208 | \r | |
209 | IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR;\r | |
210 | BuildResourceDescriptorHob (\r | |
211 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
212 | (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r | |
213 | IoBase,\r | |
214 | 0x4000\r | |
215 | );\r | |
216 | DEBUG ((EFI_D_INFO, "IoBase : 0x%x\n", IoBase));\r | |
217 | \r | |
218 | IlbBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE ) & B_PCH_LPC_ILB_BASE_BAR;\r | |
219 | BuildResourceDescriptorHob (\r | |
220 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
221 | (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r | |
222 | IlbBase,\r | |
223 | 0x1000\r | |
224 | );\r | |
225 | DEBUG ((EFI_D_INFO, "IlbBase : 0x%x\n", IlbBase));\r | |
226 | \r | |
227 | SpiBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE ) & B_PCH_LPC_SPI_BASE_BAR;\r | |
228 | BuildResourceDescriptorHob (\r | |
229 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
230 | (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r | |
231 | SpiBase,\r | |
232 | 0x1000\r | |
233 | );\r | |
234 | DEBUG ((EFI_D_INFO, "SpiBase : 0x%x\n", SpiBase));\r | |
235 | \r | |
236 | MphyBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE ) & B_PCH_LPC_MPHY_BASE_BAR;\r | |
237 | BuildResourceDescriptorHob (\r | |
238 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
239 | (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r | |
240 | MphyBase,\r | |
241 | 0x100000\r | |
242 | );\r | |
243 | DEBUG ((EFI_D_INFO, "MphyBase : 0x%x\n", MphyBase));\r | |
244 | \r | |
245 | //\r | |
246 | // Local APIC\r | |
247 | //\r | |
248 | BuildResourceDescriptorHob (\r | |
249 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
250 | (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r | |
251 | LOCAL_APIC_ADDRESS,\r | |
252 | 0x1000\r | |
253 | );\r | |
254 | DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS));\r | |
255 | \r | |
256 | //\r | |
257 | // IO APIC\r | |
258 | //\r | |
259 | BuildResourceDescriptorHob (\r | |
260 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
261 | (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r | |
262 | IO_APIC_ADDRESS,\r | |
263 | 0x1000\r | |
264 | );\r | |
265 | DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS : 0x%x\n", IO_APIC_ADDRESS));\r | |
266 | \r | |
267 | //\r | |
268 | // Adding the PCIE Express area to the E820 memory table as type 2 memory.\r | |
269 | //\r | |
270 | BuildResourceDescriptorHob (\r | |
271 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
272 | (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r | |
273 | PlatformInfo->PciData.PciExpressBase,\r | |
274 | PlatformInfo->PciData.PciExpressSize\r | |
275 | );\r | |
276 | DEBUG ((EFI_D_INFO, "PciExpressBase : 0x%x\n", PlatformInfo->PciData.PciExpressBase));\r | |
277 | \r | |
278 | //\r | |
279 | // Adding the Flashpart to the E820 memory table as type 2 memory.\r | |
280 | //\r | |
281 | BuildResourceDescriptorHob (\r | |
282 | EFI_RESOURCE_FIRMWARE_DEVICE,\r | |
283 | (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r | |
284 | FixedPcdGet32 (PcdFlashAreaBaseAddress),\r | |
285 | FixedPcdGet32 (PcdFlashAreaSize)\r | |
286 | );\r | |
287 | DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress)));\r | |
288 | \r | |
289 | //\r | |
290 | // Create a CPU hand-off information\r | |
291 | //\r | |
292 | CpuAddressWidth = 32;\r | |
293 | AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);\r | |
294 | if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) {\r | |
295 | AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);\r | |
296 | CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF);\r | |
297 | }\r | |
298 | \r | |
299 | BuildCpuHob(CpuAddressWidth, 16);\r | |
300 | ASSERT_EFI_ERROR (Status);\r | |
301 | \r | |
302 | return Status;\r | |
303 | \r | |
304 | }\r | |
305 | \r | |
306 | \r | |
307 | EFI_STATUS\r | |
308 | ValidateFvHeader (\r | |
309 | IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader\r | |
310 | )\r | |
311 | {\r | |
312 | UINT16 *Ptr;\r | |
313 | UINT16 HeaderLength;\r | |
314 | UINT16 Checksum;\r | |
315 | \r | |
316 | //\r | |
317 | // Verify the header revision, header signature, length\r | |
318 | // Length of FvBlock cannot be 2**64-1\r | |
319 | // HeaderLength cannot be an odd number\r | |
320 | //\r | |
321 | if ((FwVolHeader->Revision != EFI_FVH_REVISION) ||\r | |
322 | (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||\r | |
323 | (FwVolHeader->FvLength == ((UINT64) -1)) ||\r | |
324 | ((FwVolHeader->HeaderLength & 0x01) != 0)\r | |
325 | ) {\r | |
326 | return EFI_NOT_FOUND;\r | |
327 | }\r | |
328 | \r | |
329 | //\r | |
330 | // Verify the header checksum\r | |
331 | //\r | |
332 | HeaderLength = (UINT16) (FwVolHeader->HeaderLength / 2);\r | |
333 | Ptr = (UINT16 *) FwVolHeader;\r | |
334 | Checksum = 0;\r | |
335 | while (HeaderLength > 0) {\r | |
336 | Checksum = *Ptr++;\r | |
337 | HeaderLength--;\r | |
338 | }\r | |
339 | \r | |
340 | if (Checksum != 0) {\r | |
341 | return EFI_NOT_FOUND;\r | |
342 | }\r | |
343 | \r | |
344 | return EFI_SUCCESS;\r | |
345 | }\r |