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3cbfba02 DW |
1 | /*++\r |
2 | \r | |
3 | Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | \r | |
14 | \r | |
15 | Module Name:\r | |
16 | \r | |
17 | MiscProcessorCacheFunction.c\r | |
18 | \r | |
19 | Abstract:\r | |
20 | \r | |
21 | BIOS processor cache details.\r | |
22 | Misc. subclass type 7.\r | |
23 | SMBIOS type 7.\r | |
24 | \r | |
25 | --*/\r | |
26 | #include "CommonHeader.h"\r | |
27 | #include "MiscSubclassDriver.h"\r | |
28 | #include <Protocol/DataHub.h>\r | |
29 | #include <Guid/DataHubRecords.h>\r | |
30 | \r | |
31 | \r | |
32 | extern SMBIOS_TABLE_TYPE7 *SmbiosRecordL1;\r | |
33 | extern SMBIOS_TABLE_TYPE7 *SmbiosRecordL2;\r | |
34 | extern SMBIOS_TABLE_TYPE7 *SmbiosRecordL3;\r | |
35 | \r | |
36 | \r | |
37 | UINT32\r | |
38 | ConvertBase2ToRaw (\r | |
39 | IN EFI_EXP_BASE2_DATA *Data)\r | |
40 | {\r | |
41 | UINTN Index;\r | |
42 | UINT32 RawData;\r | |
43 | \r | |
44 | RawData = Data->Value;\r | |
45 | for (Index = 0; Index < (UINTN) Data->Exponent; Index++) {\r | |
46 | RawData <<= 1;\r | |
47 | }\r | |
48 | \r | |
49 | return RawData;\r | |
50 | }\r | |
51 | \r | |
52 | \r | |
53 | MISC_SMBIOS_TABLE_FUNCTION(MiscProcessorCache)\r | |
54 | {\r | |
55 | EFI_SMBIOS_HANDLE SmbiosHandle;\r | |
56 | SMBIOS_TABLE_TYPE7 *SmbiosRecordL1;\r | |
57 | SMBIOS_TABLE_TYPE7 *SmbiosRecordL2;\r | |
58 | \r | |
59 | EFI_CACHE_SRAM_TYPE_DATA CacheSramType;\r | |
60 | CHAR16 *SocketDesignation;\r | |
61 | CHAR8 *OptionalStrStart;\r | |
62 | UINTN SocketStrLen;\r | |
63 | STRING_REF TokenToGet;\r | |
64 | EFI_DATA_HUB_PROTOCOL *DataHub;\r | |
65 | UINT64 MonotonicCount;\r | |
66 | EFI_DATA_RECORD_HEADER *Record;\r | |
67 | EFI_SUBCLASS_TYPE1_HEADER *DataHeader;\r | |
68 | UINT8 *SrcData;\r | |
3cbfba02 DW |
69 | EFI_STATUS Status;\r |
70 | \r | |
71 | //\r | |
72 | // Memory Device LOcator\r | |
73 | //\r | |
74 | DEBUG ((EFI_D_ERROR, "type 7\n"));\r | |
75 | \r | |
76 | TokenToGet = STRING_TOKEN (STR_SOCKET_DESIGNATION);\r | |
77 | SocketDesignation = SmbiosMiscGetString (TokenToGet);\r | |
78 | SocketStrLen = StrLen(SocketDesignation);\r | |
79 | if (SocketStrLen > SMBIOS_STRING_MAX_LENGTH) {\r | |
80 | return EFI_UNSUPPORTED;\r | |
81 | }\r | |
82 | \r | |
83 | SmbiosRecordL1 = AllocatePool(sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);\r | |
84 | ASSERT (SmbiosRecordL1 != NULL);\r | |
85 | ZeroMem(SmbiosRecordL1, sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);\r | |
86 | \r | |
87 | SmbiosRecordL2 = AllocatePool(sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);\r | |
88 | ASSERT (SmbiosRecordL2 != NULL);\r | |
89 | ZeroMem(SmbiosRecordL2, sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);\r | |
90 | \r | |
91 | //\r | |
92 | // Get the Data Hub Protocol. Assume only one instance\r | |
93 | //\r | |
94 | Status = gBS->LocateProtocol (\r | |
95 | &gEfiDataHubProtocolGuid,\r | |
96 | NULL,\r | |
97 | (VOID **)&DataHub\r | |
98 | );\r | |
99 | ASSERT_EFI_ERROR(Status);\r | |
100 | \r | |
101 | MonotonicCount = 0;\r | |
102 | Record = NULL;\r | |
103 | \r | |
104 | do {\r | |
105 | Status = DataHub->GetNextRecord (\r | |
106 | DataHub,\r | |
107 | &MonotonicCount,\r | |
108 | NULL,\r | |
109 | &Record\r | |
110 | );\r | |
111 | if (!EFI_ERROR(Status)) {\r | |
112 | if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) {\r | |
113 | DataHeader = (EFI_SUBCLASS_TYPE1_HEADER *)(Record + 1);\r | |
114 | SrcData = (UINT8 *)(DataHeader + 1);\r | |
3cbfba02 DW |
115 | if (CompareGuid(&Record->DataRecordGuid, &gEfiCacheSubClassGuid) && (DataHeader->RecordType == CacheSizeRecordType)) {\r |
116 | if (DataHeader->SubInstance == EFI_CACHE_L1) {\r | |
117 | SmbiosRecordL1->InstalledSize += (UINT16) (ConvertBase2ToRaw((EFI_EXP_BASE2_DATA *)SrcData) >> 10);\r | |
118 | SmbiosRecordL1->MaximumCacheSize = SmbiosRecordL1->InstalledSize;\r | |
119 | }\r | |
120 | else if (DataHeader->SubInstance == EFI_CACHE_L2) {\r | |
121 | SmbiosRecordL2->InstalledSize += (UINT16) (ConvertBase2ToRaw((EFI_EXP_BASE2_DATA *)SrcData) >> 10);\r | |
122 | SmbiosRecordL2->MaximumCacheSize = SmbiosRecordL2->InstalledSize;\r | |
123 | } else {\r | |
124 | continue;\r | |
125 | }\r | |
126 | }\r | |
127 | }\r | |
128 | }\r | |
129 | } while (!EFI_ERROR(Status) && (MonotonicCount != 0));\r | |
130 | \r | |
131 | //\r | |
132 | //Filling SMBIOS type 7 information for different cache levels.\r | |
133 | //\r | |
134 | \r | |
135 | SmbiosRecordL1->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;\r | |
136 | SmbiosRecordL1->Hdr.Length = (UINT8) sizeof (SMBIOS_TABLE_TYPE7);\r | |
137 | SmbiosRecordL1->Hdr.Handle = 0;\r | |
138 | \r | |
139 | SmbiosRecordL1->Associativity = CacheAssociativity8Way;\r | |
140 | SmbiosRecordL1->SystemCacheType = CacheTypeUnknown;\r | |
141 | SmbiosRecordL1->SocketDesignation = 0x01;\r | |
142 | SmbiosRecordL1->CacheSpeed = 0;\r | |
143 | SmbiosRecordL1->CacheConfiguration = 0x0180;\r | |
144 | ZeroMem (&CacheSramType, sizeof (EFI_CACHE_SRAM_TYPE_DATA));\r | |
145 | CacheSramType.Synchronous = 1;\r | |
146 | CopyMem(&SmbiosRecordL1->SupportedSRAMType, &CacheSramType, 2);\r | |
147 | CopyMem(&SmbiosRecordL1->CurrentSRAMType, &CacheSramType, 2);\r | |
148 | SmbiosRecordL1->ErrorCorrectionType = EfiCacheErrorSingleBit;\r | |
149 | \r | |
150 | \r | |
151 | SmbiosRecordL2->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;\r | |
152 | SmbiosRecordL2->Hdr.Length = (UINT8) sizeof (SMBIOS_TABLE_TYPE7);\r | |
153 | SmbiosRecordL2->Hdr.Handle = 0;\r | |
154 | \r | |
155 | SmbiosRecordL2->Associativity = CacheAssociativity16Way;\r | |
156 | SmbiosRecordL2->SystemCacheType = CacheTypeInstruction;\r | |
157 | SmbiosRecordL2->SocketDesignation = 0x01;\r | |
158 | SmbiosRecordL2->CacheSpeed = 0;\r | |
159 | SmbiosRecordL2->CacheConfiguration = 0x0281;\r | |
160 | ZeroMem (&CacheSramType, sizeof (EFI_CACHE_SRAM_TYPE_DATA));\r | |
161 | CacheSramType.Synchronous = 1;\r | |
162 | CopyMem(&SmbiosRecordL2->SupportedSRAMType, &CacheSramType, 2);\r | |
163 | CopyMem(&SmbiosRecordL2->CurrentSRAMType, &CacheSramType, 2);\r | |
164 | SmbiosRecordL2->ErrorCorrectionType = EfiCacheErrorSingleBit;\r | |
165 | \r | |
166 | \r | |
167 | \r | |
168 | //\r | |
169 | //Adding SMBIOS type 7 records to SMBIOS table.\r | |
170 | //\r | |
171 | SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r | |
172 | OptionalStrStart = (CHAR8 *)(SmbiosRecordL1 + 1);\r | |
173 | UnicodeStrToAsciiStr(SocketDesignation, OptionalStrStart);\r | |
174 | \r | |
175 | Smbios-> Add(\r | |
176 | Smbios,\r | |
177 | NULL,\r | |
178 | &SmbiosHandle,\r | |
179 | (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecordL1\r | |
180 | );\r | |
181 | \r | |
182 | //\r | |
183 | //VLV2 incorporates two SLM modules (quad cores) in the SoC. 2 cores share BIU/L2 cache\r | |
184 | //\r | |
185 | SmbiosRecordL2->InstalledSize = (SmbiosRecordL2->InstalledSize)/2;\r | |
186 | SmbiosRecordL2->MaximumCacheSize = SmbiosRecordL2->InstalledSize;\r | |
187 | SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r | |
188 | \r | |
189 | OptionalStrStart = (CHAR8 *)(SmbiosRecordL2 + 1);\r | |
190 | UnicodeStrToAsciiStr(SocketDesignation, OptionalStrStart);\r | |
191 | \r | |
192 | Smbios-> Add(\r | |
193 | Smbios,\r | |
194 | NULL,\r | |
195 | &SmbiosHandle,\r | |
196 | (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecordL2\r | |
197 | );\r | |
198 | \r | |
199 | return EFI_SUCCESS;\r | |
200 | }\r |