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Commit | Line | Data |
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d19893da FB |
1 | /* |
2 | * Host code generation | |
5fafdf24 | 3 | * |
d19893da FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
d19893da | 18 | */ |
5b6dd868 BS |
19 | #ifdef _WIN32 |
20 | #include <windows.h> | |
5b6dd868 | 21 | #endif |
7b31bbc2 | 22 | #include "qemu/osdep.h" |
d19893da | 23 | |
2054396a | 24 | |
5b6dd868 | 25 | #include "qemu-common.h" |
af5ad107 | 26 | #define NO_CPU_IO_DEFS |
d3eead2e | 27 | #include "cpu.h" |
244f1441 | 28 | #include "trace.h" |
76cad711 | 29 | #include "disas/disas.h" |
63c91552 | 30 | #include "exec/exec-all.h" |
57fec1fe | 31 | #include "tcg.h" |
5b6dd868 BS |
32 | #if defined(CONFIG_USER_ONLY) |
33 | #include "qemu.h" | |
34 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) | |
35 | #include <sys/param.h> | |
36 | #if __FreeBSD_version >= 700104 | |
37 | #define HAVE_KINFO_GETVMMAP | |
38 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ | |
5b6dd868 BS |
39 | #include <sys/proc.h> |
40 | #include <machine/profile.h> | |
41 | #define _KERNEL | |
42 | #include <sys/user.h> | |
43 | #undef _KERNEL | |
44 | #undef sigqueue | |
45 | #include <libutil.h> | |
46 | #endif | |
47 | #endif | |
0bc3cd62 PB |
48 | #else |
49 | #include "exec/address-spaces.h" | |
5b6dd868 BS |
50 | #endif |
51 | ||
022c62cb | 52 | #include "exec/cputlb.h" |
e1b89321 | 53 | #include "exec/tb-hash.h" |
5b6dd868 | 54 | #include "translate-all.h" |
510a647f | 55 | #include "qemu/bitmap.h" |
61a67f71 | 56 | #include "qemu/error-report.h" |
0aa09897 | 57 | #include "qemu/timer.h" |
8d04fb55 | 58 | #include "qemu/main-loop.h" |
508127e2 | 59 | #include "exec/log.h" |
d2528bdc | 60 | #include "sysemu/cpus.h" |
5b6dd868 | 61 | |
955939a2 AB |
62 | /* #define DEBUG_TB_INVALIDATE */ |
63 | /* #define DEBUG_TB_FLUSH */ | |
5b6dd868 | 64 | /* make various TB consistency checks */ |
955939a2 | 65 | /* #define DEBUG_TB_CHECK */ |
5b6dd868 | 66 | |
dae9e03a EC |
67 | #ifdef DEBUG_TB_INVALIDATE |
68 | #define DEBUG_TB_INVALIDATE_GATE 1 | |
69 | #else | |
70 | #define DEBUG_TB_INVALIDATE_GATE 0 | |
71 | #endif | |
72 | ||
424079c1 EC |
73 | #ifdef DEBUG_TB_FLUSH |
74 | #define DEBUG_TB_FLUSH_GATE 1 | |
75 | #else | |
76 | #define DEBUG_TB_FLUSH_GATE 0 | |
77 | #endif | |
78 | ||
5b6dd868 BS |
79 | #if !defined(CONFIG_USER_ONLY) |
80 | /* TB consistency checks only implemented for usermode emulation. */ | |
81 | #undef DEBUG_TB_CHECK | |
82 | #endif | |
83 | ||
6eb062ab EC |
84 | #ifdef DEBUG_TB_CHECK |
85 | #define DEBUG_TB_CHECK_GATE 1 | |
86 | #else | |
87 | #define DEBUG_TB_CHECK_GATE 0 | |
88 | #endif | |
89 | ||
301e40ed AB |
90 | /* Access to the various translations structures need to be serialised via locks |
91 | * for consistency. This is automatic for SoftMMU based system | |
92 | * emulation due to its single threaded nature. In user-mode emulation | |
93 | * access to the memory related structures are protected with the | |
94 | * mmap_lock. | |
95 | */ | |
301e40ed | 96 | #ifdef CONFIG_SOFTMMU |
2f169606 | 97 | #define assert_memory_lock() tcg_debug_assert(have_tb_lock) |
301e40ed | 98 | #else |
6ac3d7e8 | 99 | #define assert_memory_lock() tcg_debug_assert(have_mmap_lock()) |
301e40ed AB |
100 | #endif |
101 | ||
5b6dd868 BS |
102 | #define SMC_BITMAP_USE_THRESHOLD 10 |
103 | ||
5b6dd868 BS |
104 | typedef struct PageDesc { |
105 | /* list of TBs intersecting this ram page */ | |
1e05197f | 106 | uintptr_t first_tb; |
6fad459c | 107 | #ifdef CONFIG_SOFTMMU |
5b6dd868 BS |
108 | /* in order to optimize self modifying code, we count the number |
109 | of lookups we do to a given page to use a bitmap */ | |
110 | unsigned int code_write_count; | |
510a647f | 111 | unsigned long *code_bitmap; |
6fad459c | 112 | #else |
5b6dd868 BS |
113 | unsigned long flags; |
114 | #endif | |
115 | } PageDesc; | |
116 | ||
1e05197f EC |
117 | /* list iterators for lists of tagged pointers in TranslationBlock */ |
118 | #define TB_FOR_EACH_TAGGED(head, tb, n, field) \ | |
119 | for (n = (head) & 1, tb = (TranslationBlock *)((head) & ~1); \ | |
120 | tb; tb = (TranslationBlock *)tb->field[n], n = (uintptr_t)tb & 1, \ | |
121 | tb = (TranslationBlock *)((uintptr_t)tb & ~1)) | |
122 | ||
123 | #define PAGE_FOR_EACH_TB(pagedesc, tb, n) \ | |
124 | TB_FOR_EACH_TAGGED((pagedesc)->first_tb, tb, n, page_next) | |
125 | ||
5b6dd868 BS |
126 | /* In system mode we want L1_MAP to be based on ram offsets, |
127 | while in user mode we want it to be based on virtual addresses. */ | |
128 | #if !defined(CONFIG_USER_ONLY) | |
129 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS | |
130 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS | |
131 | #else | |
132 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS | |
133 | #endif | |
134 | #else | |
135 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS | |
136 | #endif | |
137 | ||
03f49957 PB |
138 | /* Size of the L2 (and L3, etc) page tables. */ |
139 | #define V_L2_BITS 10 | |
140 | #define V_L2_SIZE (1 << V_L2_BITS) | |
141 | ||
61a67f71 LV |
142 | /* Make sure all possible CPU event bits fit in tb->trace_vcpu_dstate */ |
143 | QEMU_BUILD_BUG_ON(CPU_TRACE_DSTATE_MAX_EVENTS > | |
144 | sizeof(((TranslationBlock *)0)->trace_vcpu_dstate) | |
145 | * BITS_PER_BYTE); | |
146 | ||
66ec9f49 VK |
147 | /* |
148 | * L1 Mapping properties | |
149 | */ | |
150 | static int v_l1_size; | |
151 | static int v_l1_shift; | |
152 | static int v_l2_levels; | |
153 | ||
154 | /* The bottom level has pointers to PageDesc, and is indexed by | |
155 | * anything from 4 to (V_L2_BITS + 3) bits, depending on target page size. | |
156 | */ | |
157 | #define V_L1_MIN_BITS 4 | |
158 | #define V_L1_MAX_BITS (V_L2_BITS + 3) | |
159 | #define V_L1_MAX_SIZE (1 << V_L1_MAX_BITS) | |
160 | ||
161 | static void *l1_map[V_L1_MAX_SIZE]; | |
5b6dd868 | 162 | |
57fec1fe | 163 | /* code generation context */ |
b1311c4a | 164 | TCGContext tcg_init_ctx; |
3468b59e | 165 | __thread TCGContext *tcg_ctx; |
44ded3d0 | 166 | TBContext tb_ctx; |
fdbc2b57 | 167 | bool parallel_cpus; |
d19893da | 168 | |
677ef623 | 169 | /* translation block context */ |
13e10947 | 170 | static __thread int have_tb_lock; |
677ef623 | 171 | |
66ec9f49 VK |
172 | static void page_table_config_init(void) |
173 | { | |
174 | uint32_t v_l1_bits; | |
175 | ||
176 | assert(TARGET_PAGE_BITS); | |
177 | /* The bits remaining after N lower levels of page tables. */ | |
178 | v_l1_bits = (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % V_L2_BITS; | |
179 | if (v_l1_bits < V_L1_MIN_BITS) { | |
180 | v_l1_bits += V_L2_BITS; | |
181 | } | |
182 | ||
183 | v_l1_size = 1 << v_l1_bits; | |
184 | v_l1_shift = L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - v_l1_bits; | |
185 | v_l2_levels = v_l1_shift / V_L2_BITS - 1; | |
186 | ||
187 | assert(v_l1_bits <= V_L1_MAX_BITS); | |
188 | assert(v_l1_shift % V_L2_BITS == 0); | |
189 | assert(v_l2_levels >= 0); | |
190 | } | |
191 | ||
6ac3d7e8 PK |
192 | #define assert_tb_locked() tcg_debug_assert(have_tb_lock) |
193 | #define assert_tb_unlocked() tcg_debug_assert(!have_tb_lock) | |
6ac3d7e8 | 194 | |
677ef623 FK |
195 | void tb_lock(void) |
196 | { | |
6ac3d7e8 | 197 | assert_tb_unlocked(); |
44ded3d0 | 198 | qemu_mutex_lock(&tb_ctx.tb_lock); |
677ef623 | 199 | have_tb_lock++; |
677ef623 FK |
200 | } |
201 | ||
202 | void tb_unlock(void) | |
203 | { | |
6ac3d7e8 | 204 | assert_tb_locked(); |
677ef623 | 205 | have_tb_lock--; |
44ded3d0 | 206 | qemu_mutex_unlock(&tb_ctx.tb_lock); |
677ef623 FK |
207 | } |
208 | ||
209 | void tb_lock_reset(void) | |
210 | { | |
677ef623 | 211 | if (have_tb_lock) { |
44ded3d0 | 212 | qemu_mutex_unlock(&tb_ctx.tb_lock); |
677ef623 FK |
213 | have_tb_lock = 0; |
214 | } | |
677ef623 FK |
215 | } |
216 | ||
57fec1fe FB |
217 | void cpu_gen_init(void) |
218 | { | |
b1311c4a | 219 | tcg_context_init(&tcg_init_ctx); |
57fec1fe FB |
220 | } |
221 | ||
fca8a500 RH |
222 | /* Encode VAL as a signed leb128 sequence at P. |
223 | Return P incremented past the encoded value. */ | |
224 | static uint8_t *encode_sleb128(uint8_t *p, target_long val) | |
225 | { | |
226 | int more, byte; | |
227 | ||
228 | do { | |
229 | byte = val & 0x7f; | |
230 | val >>= 7; | |
231 | more = !((val == 0 && (byte & 0x40) == 0) | |
232 | || (val == -1 && (byte & 0x40) != 0)); | |
233 | if (more) { | |
234 | byte |= 0x80; | |
235 | } | |
236 | *p++ = byte; | |
237 | } while (more); | |
238 | ||
239 | return p; | |
240 | } | |
241 | ||
242 | /* Decode a signed leb128 sequence at *PP; increment *PP past the | |
243 | decoded value. Return the decoded value. */ | |
244 | static target_long decode_sleb128(uint8_t **pp) | |
245 | { | |
246 | uint8_t *p = *pp; | |
247 | target_long val = 0; | |
248 | int byte, shift = 0; | |
249 | ||
250 | do { | |
251 | byte = *p++; | |
252 | val |= (target_ulong)(byte & 0x7f) << shift; | |
253 | shift += 7; | |
254 | } while (byte & 0x80); | |
255 | if (shift < TARGET_LONG_BITS && (byte & 0x40)) { | |
256 | val |= -(target_ulong)1 << shift; | |
257 | } | |
258 | ||
259 | *pp = p; | |
260 | return val; | |
261 | } | |
262 | ||
263 | /* Encode the data collected about the instructions while compiling TB. | |
264 | Place the data at BLOCK, and return the number of bytes consumed. | |
265 | ||
55bbc861 | 266 | The logical table consists of TARGET_INSN_START_WORDS target_ulong's, |
fca8a500 RH |
267 | which come from the target's insn_start data, followed by a uintptr_t |
268 | which comes from the host pc of the end of the code implementing the insn. | |
269 | ||
270 | Each line of the table is encoded as sleb128 deltas from the previous | |
e7e168f4 | 271 | line. The seed for the first line is { tb->pc, 0..., tb->tc.ptr }. |
fca8a500 RH |
272 | That is, the first column is seeded with the guest pc, the last column |
273 | with the host pc, and the middle columns with zeros. */ | |
274 | ||
275 | static int encode_search(TranslationBlock *tb, uint8_t *block) | |
276 | { | |
b1311c4a | 277 | uint8_t *highwater = tcg_ctx->code_gen_highwater; |
fca8a500 RH |
278 | uint8_t *p = block; |
279 | int i, j, n; | |
280 | ||
fca8a500 RH |
281 | for (i = 0, n = tb->icount; i < n; ++i) { |
282 | target_ulong prev; | |
283 | ||
284 | for (j = 0; j < TARGET_INSN_START_WORDS; ++j) { | |
285 | if (i == 0) { | |
286 | prev = (j == 0 ? tb->pc : 0); | |
287 | } else { | |
b1311c4a | 288 | prev = tcg_ctx->gen_insn_data[i - 1][j]; |
fca8a500 | 289 | } |
b1311c4a | 290 | p = encode_sleb128(p, tcg_ctx->gen_insn_data[i][j] - prev); |
fca8a500 | 291 | } |
b1311c4a EC |
292 | prev = (i == 0 ? 0 : tcg_ctx->gen_insn_end_off[i - 1]); |
293 | p = encode_sleb128(p, tcg_ctx->gen_insn_end_off[i] - prev); | |
b125f9dc RH |
294 | |
295 | /* Test for (pending) buffer overflow. The assumption is that any | |
296 | one row beginning below the high water mark cannot overrun | |
297 | the buffer completely. Thus we can test for overflow after | |
298 | encoding a row without having to check during encoding. */ | |
299 | if (unlikely(p > highwater)) { | |
300 | return -1; | |
301 | } | |
fca8a500 RH |
302 | } |
303 | ||
304 | return p - block; | |
305 | } | |
306 | ||
7d7500d9 PB |
307 | /* The cpu state corresponding to 'searched_pc' is restored. |
308 | * Called with tb_lock held. | |
afd46fca PD |
309 | * When reset_icount is true, current TB will be interrupted and |
310 | * icount should be recalculated. | |
7d7500d9 | 311 | */ |
74f10515 | 312 | static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, |
afd46fca | 313 | uintptr_t searched_pc, bool reset_icount) |
d19893da | 314 | { |
fca8a500 | 315 | target_ulong data[TARGET_INSN_START_WORDS] = { tb->pc }; |
e7e168f4 | 316 | uintptr_t host_pc = (uintptr_t)tb->tc.ptr; |
74f10515 | 317 | CPUArchState *env = cpu->env_ptr; |
2ac01d6d | 318 | uint8_t *p = tb->tc.ptr + tb->tc.size; |
fca8a500 | 319 | int i, j, num_insns = tb->icount; |
57fec1fe | 320 | #ifdef CONFIG_PROFILER |
c3fac113 | 321 | TCGProfile *prof = &tcg_ctx->prof; |
fca8a500 | 322 | int64_t ti = profile_getclock(); |
57fec1fe FB |
323 | #endif |
324 | ||
01ecaf43 RH |
325 | searched_pc -= GETPC_ADJ; |
326 | ||
fca8a500 RH |
327 | if (searched_pc < host_pc) { |
328 | return -1; | |
329 | } | |
d19893da | 330 | |
fca8a500 RH |
331 | /* Reconstruct the stored insn data while looking for the point at |
332 | which the end of the insn exceeds the searched_pc. */ | |
333 | for (i = 0; i < num_insns; ++i) { | |
334 | for (j = 0; j < TARGET_INSN_START_WORDS; ++j) { | |
335 | data[j] += decode_sleb128(&p); | |
336 | } | |
337 | host_pc += decode_sleb128(&p); | |
338 | if (host_pc > searched_pc) { | |
339 | goto found; | |
340 | } | |
341 | } | |
342 | return -1; | |
3b46e624 | 343 | |
fca8a500 | 344 | found: |
afd46fca | 345 | if (reset_icount && (tb->cflags & CF_USE_ICOUNT)) { |
414b15c9 | 346 | assert(use_icount); |
afd46fca PD |
347 | /* Reset the cycle counter to the start of the block |
348 | and shift if to the number of actually executed instructions */ | |
349 | cpu->icount_decr.u16.low += num_insns - i; | |
2e70f6ef | 350 | } |
fca8a500 | 351 | restore_state_to_opc(env, tb, data); |
57fec1fe FB |
352 | |
353 | #ifdef CONFIG_PROFILER | |
c3fac113 EC |
354 | atomic_set(&prof->restore_time, |
355 | prof->restore_time + profile_getclock() - ti); | |
356 | atomic_set(&prof->restore_count, prof->restore_count + 1); | |
57fec1fe | 357 | #endif |
d19893da FB |
358 | return 0; |
359 | } | |
5b6dd868 | 360 | |
afd46fca | 361 | bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc, bool will_exit) |
a8a826a3 BS |
362 | { |
363 | TranslationBlock *tb; | |
a5e99826 | 364 | bool r = false; |
d25f2a72 AB |
365 | uintptr_t check_offset; |
366 | ||
367 | /* The host_pc has to be in the region of current code buffer. If | |
368 | * it is not we will not be able to resolve it here. The two cases | |
369 | * where host_pc will not be correct are: | |
370 | * | |
371 | * - fault during translation (instruction fetch) | |
372 | * - fault from helper (not using GETPC() macro) | |
373 | * | |
374 | * Either way we need return early to avoid blowing up on a | |
375 | * recursive tb_lock() as we can't resolve it here. | |
376 | * | |
377 | * We are using unsigned arithmetic so if host_pc < | |
378 | * tcg_init_ctx.code_gen_buffer check_offset will wrap to way | |
379 | * above the code_gen_buffer_size | |
d8b2239b | 380 | */ |
d25f2a72 AB |
381 | check_offset = host_pc - (uintptr_t) tcg_init_ctx.code_gen_buffer; |
382 | ||
383 | if (check_offset < tcg_init_ctx.code_gen_buffer_size) { | |
384 | tb_lock(); | |
be2cdc5e | 385 | tb = tcg_tb_lookup(host_pc); |
d25f2a72 | 386 | if (tb) { |
afd46fca | 387 | cpu_restore_state_from_tb(cpu, tb, host_pc, will_exit); |
d25f2a72 AB |
388 | if (tb->cflags & CF_NOCACHE) { |
389 | /* one-shot translation, invalidate it immediately */ | |
390 | tb_phys_invalidate(tb, -1); | |
be2cdc5e | 391 | tcg_tb_remove(tb); |
d25f2a72 AB |
392 | } |
393 | r = true; | |
d8a499f1 | 394 | } |
d25f2a72 | 395 | tb_unlock(); |
a8a826a3 | 396 | } |
a5e99826 FK |
397 | |
398 | return r; | |
a8a826a3 BS |
399 | } |
400 | ||
47c16ed5 AK |
401 | static void page_init(void) |
402 | { | |
403 | page_size_init(); | |
66ec9f49 VK |
404 | page_table_config_init(); |
405 | ||
5b6dd868 BS |
406 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
407 | { | |
408 | #ifdef HAVE_KINFO_GETVMMAP | |
409 | struct kinfo_vmentry *freep; | |
410 | int i, cnt; | |
411 | ||
412 | freep = kinfo_getvmmap(getpid(), &cnt); | |
413 | if (freep) { | |
414 | mmap_lock(); | |
415 | for (i = 0; i < cnt; i++) { | |
416 | unsigned long startaddr, endaddr; | |
417 | ||
418 | startaddr = freep[i].kve_start; | |
419 | endaddr = freep[i].kve_end; | |
420 | if (h2g_valid(startaddr)) { | |
421 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
422 | ||
423 | if (h2g_valid(endaddr)) { | |
424 | endaddr = h2g(endaddr); | |
425 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
426 | } else { | |
427 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS | |
428 | endaddr = ~0ul; | |
429 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
430 | #endif | |
431 | } | |
432 | } | |
433 | } | |
434 | free(freep); | |
435 | mmap_unlock(); | |
436 | } | |
437 | #else | |
438 | FILE *f; | |
439 | ||
440 | last_brk = (unsigned long)sbrk(0); | |
441 | ||
442 | f = fopen("/compat/linux/proc/self/maps", "r"); | |
443 | if (f) { | |
444 | mmap_lock(); | |
445 | ||
446 | do { | |
447 | unsigned long startaddr, endaddr; | |
448 | int n; | |
449 | ||
450 | n = fscanf(f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); | |
451 | ||
452 | if (n == 2 && h2g_valid(startaddr)) { | |
453 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
454 | ||
455 | if (h2g_valid(endaddr)) { | |
456 | endaddr = h2g(endaddr); | |
457 | } else { | |
458 | endaddr = ~0ul; | |
459 | } | |
460 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
461 | } | |
462 | } while (!feof(f)); | |
463 | ||
464 | fclose(f); | |
465 | mmap_unlock(); | |
466 | } | |
467 | #endif | |
468 | } | |
469 | #endif | |
470 | } | |
471 | ||
75692087 | 472 | /* If alloc=1: |
7d7500d9 | 473 | * Called with tb_lock held for system emulation. |
75692087 PB |
474 | * Called with mmap_lock held for user-mode emulation. |
475 | */ | |
5b6dd868 BS |
476 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
477 | { | |
478 | PageDesc *pd; | |
479 | void **lp; | |
480 | int i; | |
481 | ||
e505a063 AB |
482 | if (alloc) { |
483 | assert_memory_lock(); | |
484 | } | |
485 | ||
5b6dd868 | 486 | /* Level 1. Always allocated. */ |
66ec9f49 | 487 | lp = l1_map + ((index >> v_l1_shift) & (v_l1_size - 1)); |
5b6dd868 BS |
488 | |
489 | /* Level 2..N-1. */ | |
66ec9f49 | 490 | for (i = v_l2_levels; i > 0; i--) { |
6940fab8 | 491 | void **p = atomic_rcu_read(lp); |
5b6dd868 BS |
492 | |
493 | if (p == NULL) { | |
494 | if (!alloc) { | |
495 | return NULL; | |
496 | } | |
e3a0abfd | 497 | p = g_new0(void *, V_L2_SIZE); |
6940fab8 | 498 | atomic_rcu_set(lp, p); |
5b6dd868 BS |
499 | } |
500 | ||
03f49957 | 501 | lp = p + ((index >> (i * V_L2_BITS)) & (V_L2_SIZE - 1)); |
5b6dd868 BS |
502 | } |
503 | ||
6940fab8 | 504 | pd = atomic_rcu_read(lp); |
5b6dd868 BS |
505 | if (pd == NULL) { |
506 | if (!alloc) { | |
507 | return NULL; | |
508 | } | |
e3a0abfd | 509 | pd = g_new0(PageDesc, V_L2_SIZE); |
6940fab8 | 510 | atomic_rcu_set(lp, pd); |
5b6dd868 BS |
511 | } |
512 | ||
03f49957 | 513 | return pd + (index & (V_L2_SIZE - 1)); |
5b6dd868 BS |
514 | } |
515 | ||
516 | static inline PageDesc *page_find(tb_page_addr_t index) | |
517 | { | |
518 | return page_find_alloc(index, 0); | |
519 | } | |
520 | ||
5b6dd868 BS |
521 | #if defined(CONFIG_USER_ONLY) |
522 | /* Currently it is not recommended to allocate big chunks of data in | |
523 | user mode. It will change when a dedicated libc will be used. */ | |
524 | /* ??? 64-bit hosts ought to have no problem mmaping data outside the | |
525 | region in which the guest needs to run. Revisit this. */ | |
526 | #define USE_STATIC_CODE_GEN_BUFFER | |
527 | #endif | |
528 | ||
5b6dd868 BS |
529 | /* Minimum size of the code gen buffer. This number is randomly chosen, |
530 | but not so small that we can't have a fair number of TB's live. */ | |
531 | #define MIN_CODE_GEN_BUFFER_SIZE (1024u * 1024) | |
532 | ||
533 | /* Maximum size of the code gen buffer we'd like to use. Unless otherwise | |
534 | indicated, this is constrained by the range of direct branches on the | |
535 | host cpu, as used by the TCG implementation of goto_tb. */ | |
536 | #if defined(__x86_64__) | |
537 | # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024) | |
538 | #elif defined(__sparc__) | |
539 | # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024) | |
5bfd75a3 RH |
540 | #elif defined(__powerpc64__) |
541 | # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024) | |
399f1648 SF |
542 | #elif defined(__powerpc__) |
543 | # define MAX_CODE_GEN_BUFFER_SIZE (32u * 1024 * 1024) | |
4a136e0a | 544 | #elif defined(__aarch64__) |
b68686bd | 545 | # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024) |
5b6dd868 BS |
546 | #elif defined(__s390x__) |
547 | /* We have a +- 4GB range on the branches; leave some slop. */ | |
548 | # define MAX_CODE_GEN_BUFFER_SIZE (3ul * 1024 * 1024 * 1024) | |
479eb121 RH |
549 | #elif defined(__mips__) |
550 | /* We have a 256MB branch region, but leave room to make sure the | |
551 | main executable is also within that region. */ | |
552 | # define MAX_CODE_GEN_BUFFER_SIZE (128ul * 1024 * 1024) | |
5b6dd868 BS |
553 | #else |
554 | # define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) | |
555 | #endif | |
556 | ||
557 | #define DEFAULT_CODE_GEN_BUFFER_SIZE_1 (32u * 1024 * 1024) | |
558 | ||
559 | #define DEFAULT_CODE_GEN_BUFFER_SIZE \ | |
560 | (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \ | |
561 | ? DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE) | |
562 | ||
563 | static inline size_t size_code_gen_buffer(size_t tb_size) | |
564 | { | |
565 | /* Size the buffer. */ | |
566 | if (tb_size == 0) { | |
567 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
568 | tb_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
569 | #else | |
570 | /* ??? Needs adjustments. */ | |
571 | /* ??? If we relax the requirement that CONFIG_USER_ONLY use the | |
572 | static buffer, we could size this on RESERVED_VA, on the text | |
573 | segment size of the executable, or continue to use the default. */ | |
574 | tb_size = (unsigned long)(ram_size / 4); | |
575 | #endif | |
576 | } | |
577 | if (tb_size < MIN_CODE_GEN_BUFFER_SIZE) { | |
578 | tb_size = MIN_CODE_GEN_BUFFER_SIZE; | |
579 | } | |
580 | if (tb_size > MAX_CODE_GEN_BUFFER_SIZE) { | |
581 | tb_size = MAX_CODE_GEN_BUFFER_SIZE; | |
582 | } | |
5b6dd868 BS |
583 | return tb_size; |
584 | } | |
585 | ||
483c76e1 RH |
586 | #ifdef __mips__ |
587 | /* In order to use J and JAL within the code_gen_buffer, we require | |
588 | that the buffer not cross a 256MB boundary. */ | |
589 | static inline bool cross_256mb(void *addr, size_t size) | |
590 | { | |
7ba6a512 | 591 | return ((uintptr_t)addr ^ ((uintptr_t)addr + size)) & ~0x0ffffffful; |
483c76e1 RH |
592 | } |
593 | ||
594 | /* We weren't able to allocate a buffer without crossing that boundary, | |
595 | so make do with the larger portion of the buffer that doesn't cross. | |
596 | Returns the new base of the buffer, and adjusts code_gen_buffer_size. */ | |
597 | static inline void *split_cross_256mb(void *buf1, size_t size1) | |
598 | { | |
7ba6a512 | 599 | void *buf2 = (void *)(((uintptr_t)buf1 + size1) & ~0x0ffffffful); |
483c76e1 RH |
600 | size_t size2 = buf1 + size1 - buf2; |
601 | ||
602 | size1 = buf2 - buf1; | |
603 | if (size1 < size2) { | |
604 | size1 = size2; | |
605 | buf1 = buf2; | |
606 | } | |
607 | ||
b1311c4a | 608 | tcg_ctx->code_gen_buffer_size = size1; |
483c76e1 RH |
609 | return buf1; |
610 | } | |
611 | #endif | |
612 | ||
5b6dd868 BS |
613 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
614 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] | |
615 | __attribute__((aligned(CODE_GEN_ALIGN))); | |
616 | ||
617 | static inline void *alloc_code_gen_buffer(void) | |
618 | { | |
483c76e1 | 619 | void *buf = static_code_gen_buffer; |
f51f315a | 620 | void *end = static_code_gen_buffer + sizeof(static_code_gen_buffer); |
e8feb96f | 621 | size_t size; |
f293709c | 622 | |
f51f315a EC |
623 | /* page-align the beginning and end of the buffer */ |
624 | buf = QEMU_ALIGN_PTR_UP(buf, qemu_real_host_page_size); | |
625 | end = QEMU_ALIGN_PTR_DOWN(end, qemu_real_host_page_size); | |
f293709c | 626 | |
e8feb96f | 627 | size = end - buf; |
f293709c RH |
628 | |
629 | /* Honor a command-line option limiting the size of the buffer. */ | |
b1311c4a | 630 | if (size > tcg_ctx->code_gen_buffer_size) { |
f51f315a EC |
631 | size = QEMU_ALIGN_DOWN(tcg_ctx->code_gen_buffer_size, |
632 | qemu_real_host_page_size); | |
f293709c | 633 | } |
b1311c4a | 634 | tcg_ctx->code_gen_buffer_size = size; |
f293709c | 635 | |
483c76e1 | 636 | #ifdef __mips__ |
f293709c RH |
637 | if (cross_256mb(buf, size)) { |
638 | buf = split_cross_256mb(buf, size); | |
b1311c4a | 639 | size = tcg_ctx->code_gen_buffer_size; |
483c76e1 RH |
640 | } |
641 | #endif | |
f293709c | 642 | |
f51f315a EC |
643 | if (qemu_mprotect_rwx(buf, size)) { |
644 | abort(); | |
645 | } | |
f293709c RH |
646 | qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); |
647 | ||
483c76e1 | 648 | return buf; |
5b6dd868 | 649 | } |
f293709c RH |
650 | #elif defined(_WIN32) |
651 | static inline void *alloc_code_gen_buffer(void) | |
652 | { | |
b1311c4a | 653 | size_t size = tcg_ctx->code_gen_buffer_size; |
4a4ff4c5 | 654 | return VirtualAlloc(NULL, size, MEM_RESERVE | MEM_COMMIT, |
e8feb96f | 655 | PAGE_EXECUTE_READWRITE); |
f293709c RH |
656 | } |
657 | #else | |
5b6dd868 BS |
658 | static inline void *alloc_code_gen_buffer(void) |
659 | { | |
e8feb96f | 660 | int prot = PROT_WRITE | PROT_READ | PROT_EXEC; |
5b6dd868 BS |
661 | int flags = MAP_PRIVATE | MAP_ANONYMOUS; |
662 | uintptr_t start = 0; | |
b1311c4a | 663 | size_t size = tcg_ctx->code_gen_buffer_size; |
5b6dd868 BS |
664 | void *buf; |
665 | ||
666 | /* Constrain the position of the buffer based on the host cpu. | |
667 | Note that these addresses are chosen in concert with the | |
668 | addresses assigned in the relevant linker script file. */ | |
669 | # if defined(__PIE__) || defined(__PIC__) | |
670 | /* Don't bother setting a preferred location if we're building | |
671 | a position-independent executable. We're more likely to get | |
672 | an address near the main executable if we let the kernel | |
673 | choose the address. */ | |
674 | # elif defined(__x86_64__) && defined(MAP_32BIT) | |
675 | /* Force the memory down into low memory with the executable. | |
676 | Leave the choice of exact location with the kernel. */ | |
677 | flags |= MAP_32BIT; | |
678 | /* Cannot expect to map more than 800MB in low memory. */ | |
f293709c | 679 | if (size > 800u * 1024 * 1024) { |
b1311c4a | 680 | tcg_ctx->code_gen_buffer_size = size = 800u * 1024 * 1024; |
5b6dd868 BS |
681 | } |
682 | # elif defined(__sparc__) | |
683 | start = 0x40000000ul; | |
684 | # elif defined(__s390x__) | |
685 | start = 0x90000000ul; | |
479eb121 | 686 | # elif defined(__mips__) |
f293709c | 687 | # if _MIPS_SIM == _ABI64 |
479eb121 RH |
688 | start = 0x128000000ul; |
689 | # else | |
690 | start = 0x08000000ul; | |
691 | # endif | |
5b6dd868 BS |
692 | # endif |
693 | ||
e8feb96f | 694 | buf = mmap((void *)start, size, prot, flags, -1, 0); |
483c76e1 RH |
695 | if (buf == MAP_FAILED) { |
696 | return NULL; | |
697 | } | |
698 | ||
699 | #ifdef __mips__ | |
f293709c | 700 | if (cross_256mb(buf, size)) { |
5d831be2 | 701 | /* Try again, with the original still mapped, to avoid re-acquiring |
483c76e1 | 702 | that 256mb crossing. This time don't specify an address. */ |
f293709c | 703 | size_t size2; |
e8feb96f | 704 | void *buf2 = mmap(NULL, size, prot, flags, -1, 0); |
f68808c7 | 705 | switch ((int)(buf2 != MAP_FAILED)) { |
f293709c RH |
706 | case 1: |
707 | if (!cross_256mb(buf2, size)) { | |
483c76e1 | 708 | /* Success! Use the new buffer. */ |
e8feb96f | 709 | munmap(buf, size); |
f293709c | 710 | break; |
483c76e1 RH |
711 | } |
712 | /* Failure. Work with what we had. */ | |
e8feb96f | 713 | munmap(buf2, size); |
f293709c RH |
714 | /* fallthru */ |
715 | default: | |
716 | /* Split the original buffer. Free the smaller half. */ | |
717 | buf2 = split_cross_256mb(buf, size); | |
b1311c4a | 718 | size2 = tcg_ctx->code_gen_buffer_size; |
f293709c | 719 | if (buf == buf2) { |
e8feb96f | 720 | munmap(buf + size2, size - size2); |
f293709c RH |
721 | } else { |
722 | munmap(buf, size - size2); | |
723 | } | |
724 | size = size2; | |
725 | break; | |
483c76e1 | 726 | } |
f293709c | 727 | buf = buf2; |
483c76e1 RH |
728 | } |
729 | #endif | |
730 | ||
f293709c RH |
731 | /* Request large pages for the buffer. */ |
732 | qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); | |
483c76e1 | 733 | |
5b6dd868 BS |
734 | return buf; |
735 | } | |
f293709c | 736 | #endif /* USE_STATIC_CODE_GEN_BUFFER, WIN32, POSIX */ |
5b6dd868 BS |
737 | |
738 | static inline void code_gen_alloc(size_t tb_size) | |
739 | { | |
b1311c4a EC |
740 | tcg_ctx->code_gen_buffer_size = size_code_gen_buffer(tb_size); |
741 | tcg_ctx->code_gen_buffer = alloc_code_gen_buffer(); | |
742 | if (tcg_ctx->code_gen_buffer == NULL) { | |
5b6dd868 BS |
743 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
744 | exit(1); | |
745 | } | |
44ded3d0 | 746 | qemu_mutex_init(&tb_ctx.tb_lock); |
5b6dd868 BS |
747 | } |
748 | ||
61b8cef1 EC |
749 | static bool tb_cmp(const void *ap, const void *bp) |
750 | { | |
751 | const TranslationBlock *a = ap; | |
752 | const TranslationBlock *b = bp; | |
753 | ||
754 | return a->pc == b->pc && | |
755 | a->cs_base == b->cs_base && | |
756 | a->flags == b->flags && | |
757 | (tb_cflags(a) & CF_HASH_MASK) == (tb_cflags(b) & CF_HASH_MASK) && | |
758 | a->trace_vcpu_dstate == b->trace_vcpu_dstate && | |
759 | a->page_addr[0] == b->page_addr[0] && | |
760 | a->page_addr[1] == b->page_addr[1]; | |
761 | } | |
762 | ||
909eaac9 EC |
763 | static void tb_htable_init(void) |
764 | { | |
765 | unsigned int mode = QHT_MODE_AUTO_RESIZE; | |
766 | ||
61b8cef1 | 767 | qht_init(&tb_ctx.htable, tb_cmp, CODE_GEN_HTABLE_SIZE, mode); |
909eaac9 EC |
768 | } |
769 | ||
5b6dd868 BS |
770 | /* Must be called before using the QEMU cpus. 'tb_size' is the size |
771 | (in bytes) allocated to the translation buffer. Zero means default | |
772 | size. */ | |
773 | void tcg_exec_init(unsigned long tb_size) | |
774 | { | |
8e2b7299 | 775 | tcg_allowed = true; |
5b6dd868 | 776 | cpu_gen_init(); |
5b6dd868 | 777 | page_init(); |
909eaac9 | 778 | tb_htable_init(); |
f293709c | 779 | code_gen_alloc(tb_size); |
4cbea598 | 780 | #if defined(CONFIG_SOFTMMU) |
5b6dd868 BS |
781 | /* There's no guest base to take into account, so go ahead and |
782 | initialize the prologue now. */ | |
b1311c4a | 783 | tcg_prologue_init(tcg_ctx); |
5b6dd868 BS |
784 | #endif |
785 | } | |
786 | ||
7d7500d9 PB |
787 | /* |
788 | * Allocate a new translation block. Flush the translation buffer if | |
789 | * too many translation blocks or too much generated code. | |
790 | * | |
791 | * Called with tb_lock held. | |
792 | */ | |
5b6dd868 BS |
793 | static TranslationBlock *tb_alloc(target_ulong pc) |
794 | { | |
795 | TranslationBlock *tb; | |
796 | ||
6ac3d7e8 | 797 | assert_tb_locked(); |
e505a063 | 798 | |
b1311c4a | 799 | tb = tcg_tb_alloc(tcg_ctx); |
6e3b2bfd | 800 | if (unlikely(tb == NULL)) { |
5b6dd868 BS |
801 | return NULL; |
802 | } | |
5b6dd868 BS |
803 | return tb; |
804 | } | |
805 | ||
5b6dd868 BS |
806 | static inline void invalidate_page_bitmap(PageDesc *p) |
807 | { | |
6fad459c | 808 | #ifdef CONFIG_SOFTMMU |
012aef07 MA |
809 | g_free(p->code_bitmap); |
810 | p->code_bitmap = NULL; | |
5b6dd868 | 811 | p->code_write_count = 0; |
6fad459c | 812 | #endif |
5b6dd868 BS |
813 | } |
814 | ||
815 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ | |
816 | static void page_flush_tb_1(int level, void **lp) | |
817 | { | |
818 | int i; | |
819 | ||
820 | if (*lp == NULL) { | |
821 | return; | |
822 | } | |
823 | if (level == 0) { | |
824 | PageDesc *pd = *lp; | |
825 | ||
03f49957 | 826 | for (i = 0; i < V_L2_SIZE; ++i) { |
1e05197f | 827 | pd[i].first_tb = (uintptr_t)NULL; |
5b6dd868 BS |
828 | invalidate_page_bitmap(pd + i); |
829 | } | |
830 | } else { | |
831 | void **pp = *lp; | |
832 | ||
03f49957 | 833 | for (i = 0; i < V_L2_SIZE; ++i) { |
5b6dd868 BS |
834 | page_flush_tb_1(level - 1, pp + i); |
835 | } | |
836 | } | |
837 | } | |
838 | ||
839 | static void page_flush_tb(void) | |
840 | { | |
66ec9f49 | 841 | int i, l1_sz = v_l1_size; |
5b6dd868 | 842 | |
66ec9f49 VK |
843 | for (i = 0; i < l1_sz; i++) { |
844 | page_flush_tb_1(v_l2_levels, l1_map + i); | |
5b6dd868 BS |
845 | } |
846 | } | |
847 | ||
f19c6cc6 EC |
848 | static gboolean tb_host_size_iter(gpointer key, gpointer value, gpointer data) |
849 | { | |
850 | const TranslationBlock *tb = value; | |
851 | size_t *size = data; | |
852 | ||
853 | *size += tb->tc.size; | |
854 | return false; | |
855 | } | |
856 | ||
5b6dd868 | 857 | /* flush all the translation blocks */ |
14e6fe12 | 858 | static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count) |
5b6dd868 | 859 | { |
3359baad SF |
860 | tb_lock(); |
861 | ||
14e6fe12 | 862 | /* If it is already been done on request of another CPU, |
3359baad SF |
863 | * just retry. |
864 | */ | |
44ded3d0 | 865 | if (tb_ctx.tb_flush_count != tb_flush_count.host_int) { |
3359baad | 866 | goto done; |
135a972b | 867 | } |
3359baad | 868 | |
424079c1 | 869 | if (DEBUG_TB_FLUSH_GATE) { |
be2cdc5e | 870 | size_t nb_tbs = tcg_nb_tbs(); |
f19c6cc6 | 871 | size_t host_size = 0; |
2ac01d6d | 872 | |
be2cdc5e | 873 | tcg_tb_foreach(tb_host_size_iter, &host_size); |
e8feb96f EC |
874 | printf("qemu: flush code_size=%zu nb_tbs=%zu avg_tb_size=%zu\n", |
875 | tcg_code_size(), nb_tbs, nb_tbs > 0 ? host_size / nb_tbs : 0); | |
5b6dd868 | 876 | } |
5b6dd868 | 877 | |
bdc44640 | 878 | CPU_FOREACH(cpu) { |
f3ced3c5 | 879 | cpu_tb_jmp_cache_clear(cpu); |
5b6dd868 BS |
880 | } |
881 | ||
44ded3d0 | 882 | qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE); |
5b6dd868 BS |
883 | page_flush_tb(); |
884 | ||
e8feb96f | 885 | tcg_region_reset_all(); |
5b6dd868 BS |
886 | /* XXX: flush processor icache at this point if cache flush is |
887 | expensive */ | |
44ded3d0 | 888 | atomic_mb_set(&tb_ctx.tb_flush_count, tb_ctx.tb_flush_count + 1); |
3359baad SF |
889 | |
890 | done: | |
891 | tb_unlock(); | |
892 | } | |
893 | ||
894 | void tb_flush(CPUState *cpu) | |
895 | { | |
896 | if (tcg_enabled()) { | |
44ded3d0 | 897 | unsigned tb_flush_count = atomic_mb_read(&tb_ctx.tb_flush_count); |
14e6fe12 PB |
898 | async_safe_run_on_cpu(cpu, do_tb_flush, |
899 | RUN_ON_CPU_HOST_INT(tb_flush_count)); | |
3359baad | 900 | } |
5b6dd868 BS |
901 | } |
902 | ||
6eb062ab EC |
903 | /* |
904 | * Formerly ifdef DEBUG_TB_CHECK. These debug functions are user-mode-only, | |
905 | * so in order to prevent bit rot we compile them unconditionally in user-mode, | |
906 | * and let the optimizer get rid of them by wrapping their user-only callers | |
907 | * with if (DEBUG_TB_CHECK_GATE). | |
908 | */ | |
909 | #ifdef CONFIG_USER_ONLY | |
5b6dd868 | 910 | |
909eaac9 EC |
911 | static void |
912 | do_tb_invalidate_check(struct qht *ht, void *p, uint32_t hash, void *userp) | |
5b6dd868 | 913 | { |
909eaac9 EC |
914 | TranslationBlock *tb = p; |
915 | target_ulong addr = *(target_ulong *)userp; | |
916 | ||
917 | if (!(addr + TARGET_PAGE_SIZE <= tb->pc || addr >= tb->pc + tb->size)) { | |
918 | printf("ERROR invalidate: address=" TARGET_FMT_lx | |
919 | " PC=%08lx size=%04x\n", addr, (long)tb->pc, tb->size); | |
920 | } | |
921 | } | |
5b6dd868 | 922 | |
7d7500d9 PB |
923 | /* verify that all the pages have correct rights for code |
924 | * | |
925 | * Called with tb_lock held. | |
926 | */ | |
909eaac9 EC |
927 | static void tb_invalidate_check(target_ulong address) |
928 | { | |
5b6dd868 | 929 | address &= TARGET_PAGE_MASK; |
44ded3d0 | 930 | qht_iter(&tb_ctx.htable, do_tb_invalidate_check, &address); |
909eaac9 EC |
931 | } |
932 | ||
933 | static void | |
934 | do_tb_page_check(struct qht *ht, void *p, uint32_t hash, void *userp) | |
935 | { | |
936 | TranslationBlock *tb = p; | |
937 | int flags1, flags2; | |
938 | ||
939 | flags1 = page_get_flags(tb->pc); | |
940 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
941 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
942 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
943 | (long)tb->pc, tb->size, flags1, flags2); | |
5b6dd868 BS |
944 | } |
945 | } | |
946 | ||
947 | /* verify that all the pages have correct rights for code */ | |
948 | static void tb_page_check(void) | |
949 | { | |
44ded3d0 | 950 | qht_iter(&tb_ctx.htable, do_tb_page_check, NULL); |
5b6dd868 BS |
951 | } |
952 | ||
6eb062ab | 953 | #endif /* CONFIG_USER_ONLY */ |
5b6dd868 | 954 | |
1e05197f | 955 | static inline void tb_page_remove(PageDesc *pd, TranslationBlock *tb) |
5b6dd868 BS |
956 | { |
957 | TranslationBlock *tb1; | |
1e05197f | 958 | uintptr_t *pprev; |
5b6dd868 BS |
959 | unsigned int n1; |
960 | ||
1e05197f EC |
961 | pprev = &pd->first_tb; |
962 | PAGE_FOR_EACH_TB(pd, tb1, n1) { | |
5b6dd868 | 963 | if (tb1 == tb) { |
1e05197f EC |
964 | *pprev = tb1->page_next[n1]; |
965 | return; | |
5b6dd868 | 966 | } |
1e05197f | 967 | pprev = &tb1->page_next[n1]; |
5b6dd868 | 968 | } |
1e05197f | 969 | g_assert_not_reached(); |
5b6dd868 BS |
970 | } |
971 | ||
13362678 SF |
972 | /* remove the TB from a list of TBs jumping to the n-th jump target of the TB */ |
973 | static inline void tb_remove_from_jmp_list(TranslationBlock *tb, int n) | |
5b6dd868 | 974 | { |
c37e6d7e SF |
975 | TranslationBlock *tb1; |
976 | uintptr_t *ptb, ntb; | |
5b6dd868 BS |
977 | unsigned int n1; |
978 | ||
f309101c | 979 | ptb = &tb->jmp_list_next[n]; |
c37e6d7e | 980 | if (*ptb) { |
5b6dd868 BS |
981 | /* find tb(n) in circular list */ |
982 | for (;;) { | |
c37e6d7e SF |
983 | ntb = *ptb; |
984 | n1 = ntb & 3; | |
985 | tb1 = (TranslationBlock *)(ntb & ~3); | |
5b6dd868 BS |
986 | if (n1 == n && tb1 == tb) { |
987 | break; | |
988 | } | |
989 | if (n1 == 2) { | |
f309101c | 990 | ptb = &tb1->jmp_list_first; |
5b6dd868 | 991 | } else { |
f309101c | 992 | ptb = &tb1->jmp_list_next[n1]; |
5b6dd868 BS |
993 | } |
994 | } | |
995 | /* now we can suppress tb(n) from the list */ | |
f309101c | 996 | *ptb = tb->jmp_list_next[n]; |
5b6dd868 | 997 | |
c37e6d7e | 998 | tb->jmp_list_next[n] = (uintptr_t)NULL; |
5b6dd868 BS |
999 | } |
1000 | } | |
1001 | ||
1002 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
1003 | another TB */ | |
1004 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
1005 | { | |
e7e168f4 | 1006 | uintptr_t addr = (uintptr_t)(tb->tc.ptr + tb->jmp_reset_offset[n]); |
f309101c | 1007 | tb_set_jmp_target(tb, n, addr); |
5b6dd868 BS |
1008 | } |
1009 | ||
89bba496 SF |
1010 | /* remove any jumps to the TB */ |
1011 | static inline void tb_jmp_unlink(TranslationBlock *tb) | |
1012 | { | |
f9c5b66f SF |
1013 | TranslationBlock *tb1; |
1014 | uintptr_t *ptb, ntb; | |
89bba496 SF |
1015 | unsigned int n1; |
1016 | ||
f9c5b66f | 1017 | ptb = &tb->jmp_list_first; |
89bba496 | 1018 | for (;;) { |
f9c5b66f SF |
1019 | ntb = *ptb; |
1020 | n1 = ntb & 3; | |
1021 | tb1 = (TranslationBlock *)(ntb & ~3); | |
89bba496 SF |
1022 | if (n1 == 2) { |
1023 | break; | |
1024 | } | |
f9c5b66f SF |
1025 | tb_reset_jump(tb1, n1); |
1026 | *ptb = tb1->jmp_list_next[n1]; | |
1027 | tb1->jmp_list_next[n1] = (uintptr_t)NULL; | |
89bba496 | 1028 | } |
89bba496 SF |
1029 | } |
1030 | ||
7d7500d9 PB |
1031 | /* invalidate one TB |
1032 | * | |
1033 | * Called with tb_lock held. | |
1034 | */ | |
5b6dd868 BS |
1035 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
1036 | { | |
182735ef | 1037 | CPUState *cpu; |
5b6dd868 | 1038 | PageDesc *p; |
42bd3228 | 1039 | uint32_t h; |
5b6dd868 | 1040 | tb_page_addr_t phys_pc; |
5b6dd868 | 1041 | |
6ac3d7e8 | 1042 | assert_tb_locked(); |
e505a063 | 1043 | |
84f1c148 | 1044 | atomic_set(&tb->cflags, tb->cflags | CF_INVALID); |
6d21e420 | 1045 | |
5b6dd868 BS |
1046 | /* remove the TB from the hash list */ |
1047 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
4e2ca83e EC |
1048 | h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK, |
1049 | tb->trace_vcpu_dstate); | |
cc689485 EC |
1050 | if (!qht_remove(&tb_ctx.htable, tb, h)) { |
1051 | return; | |
1052 | } | |
5b6dd868 BS |
1053 | |
1054 | /* remove the TB from the page list */ | |
1055 | if (tb->page_addr[0] != page_addr) { | |
1056 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
1e05197f | 1057 | tb_page_remove(p, tb); |
5b6dd868 BS |
1058 | invalidate_page_bitmap(p); |
1059 | } | |
1060 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
1061 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
1e05197f | 1062 | tb_page_remove(p, tb); |
5b6dd868 BS |
1063 | invalidate_page_bitmap(p); |
1064 | } | |
1065 | ||
5b6dd868 BS |
1066 | /* remove the TB from the hash list */ |
1067 | h = tb_jmp_cache_hash_func(tb->pc); | |
bdc44640 | 1068 | CPU_FOREACH(cpu) { |
89a16b1e SF |
1069 | if (atomic_read(&cpu->tb_jmp_cache[h]) == tb) { |
1070 | atomic_set(&cpu->tb_jmp_cache[h], NULL); | |
5b6dd868 BS |
1071 | } |
1072 | } | |
1073 | ||
1074 | /* suppress this TB from the two jump lists */ | |
13362678 SF |
1075 | tb_remove_from_jmp_list(tb, 0); |
1076 | tb_remove_from_jmp_list(tb, 1); | |
5b6dd868 BS |
1077 | |
1078 | /* suppress any remaining jumps to this TB */ | |
89bba496 | 1079 | tb_jmp_unlink(tb); |
5b6dd868 | 1080 | |
128ed227 EC |
1081 | atomic_set(&tcg_ctx->tb_phys_invalidate_count, |
1082 | tcg_ctx->tb_phys_invalidate_count + 1); | |
5b6dd868 BS |
1083 | } |
1084 | ||
6fad459c | 1085 | #ifdef CONFIG_SOFTMMU |
5b6dd868 BS |
1086 | static void build_page_bitmap(PageDesc *p) |
1087 | { | |
1088 | int n, tb_start, tb_end; | |
1089 | TranslationBlock *tb; | |
1090 | ||
510a647f | 1091 | p->code_bitmap = bitmap_new(TARGET_PAGE_SIZE); |
5b6dd868 | 1092 | |
1e05197f | 1093 | PAGE_FOR_EACH_TB(p, tb, n) { |
5b6dd868 BS |
1094 | /* NOTE: this is subtle as a TB may span two physical pages */ |
1095 | if (n == 0) { | |
1096 | /* NOTE: tb_end may be after the end of the page, but | |
1097 | it is not a problem */ | |
1098 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
1099 | tb_end = tb_start + tb->size; | |
1100 | if (tb_end > TARGET_PAGE_SIZE) { | |
1101 | tb_end = TARGET_PAGE_SIZE; | |
e505a063 | 1102 | } |
5b6dd868 BS |
1103 | } else { |
1104 | tb_start = 0; | |
1105 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1106 | } | |
510a647f | 1107 | bitmap_set(p->code_bitmap, tb_start, tb_end - tb_start); |
5b6dd868 BS |
1108 | } |
1109 | } | |
6fad459c | 1110 | #endif |
5b6dd868 | 1111 | |
e90d96b1 SF |
1112 | /* add the tb in the target page and protect it if necessary |
1113 | * | |
1114 | * Called with mmap_lock held for user-mode emulation. | |
1115 | */ | |
1116 | static inline void tb_alloc_page(TranslationBlock *tb, | |
1117 | unsigned int n, tb_page_addr_t page_addr) | |
1118 | { | |
1119 | PageDesc *p; | |
1120 | #ifndef CONFIG_USER_ONLY | |
1121 | bool page_already_protected; | |
1122 | #endif | |
1123 | ||
e505a063 AB |
1124 | assert_memory_lock(); |
1125 | ||
e90d96b1 SF |
1126 | tb->page_addr[n] = page_addr; |
1127 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); | |
1128 | tb->page_next[n] = p->first_tb; | |
1129 | #ifndef CONFIG_USER_ONLY | |
1e05197f | 1130 | page_already_protected = p->first_tb != (uintptr_t)NULL; |
e90d96b1 | 1131 | #endif |
1e05197f | 1132 | p->first_tb = (uintptr_t)tb | n; |
e90d96b1 SF |
1133 | invalidate_page_bitmap(p); |
1134 | ||
1135 | #if defined(CONFIG_USER_ONLY) | |
1136 | if (p->flags & PAGE_WRITE) { | |
1137 | target_ulong addr; | |
1138 | PageDesc *p2; | |
1139 | int prot; | |
1140 | ||
1141 | /* force the host page as non writable (writes will have a | |
1142 | page fault + mprotect overhead) */ | |
1143 | page_addr &= qemu_host_page_mask; | |
1144 | prot = 0; | |
1145 | for (addr = page_addr; addr < page_addr + qemu_host_page_size; | |
1146 | addr += TARGET_PAGE_SIZE) { | |
1147 | ||
1148 | p2 = page_find(addr >> TARGET_PAGE_BITS); | |
1149 | if (!p2) { | |
1150 | continue; | |
1151 | } | |
1152 | prot |= p2->flags; | |
1153 | p2->flags &= ~PAGE_WRITE; | |
1154 | } | |
1155 | mprotect(g2h(page_addr), qemu_host_page_size, | |
1156 | (prot & PAGE_BITS) & ~PAGE_WRITE); | |
dae9e03a EC |
1157 | if (DEBUG_TB_INVALIDATE_GATE) { |
1158 | printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr); | |
1159 | } | |
e90d96b1 SF |
1160 | } |
1161 | #else | |
1162 | /* if some code is already present, then the pages are already | |
1163 | protected. So we handle the case where only the first TB is | |
1164 | allocated in a physical page */ | |
1165 | if (!page_already_protected) { | |
1166 | tlb_protect_code(page_addr); | |
1167 | } | |
1168 | #endif | |
1169 | } | |
1170 | ||
1171 | /* add a new TB and link it to the physical page tables. phys_page2 is | |
1172 | * (-1) to indicate that only one page contains the TB. | |
1173 | * | |
1174 | * Called with mmap_lock held for user-mode emulation. | |
1175 | */ | |
1176 | static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, | |
1177 | tb_page_addr_t phys_page2) | |
1178 | { | |
42bd3228 | 1179 | uint32_t h; |
e90d96b1 | 1180 | |
e505a063 AB |
1181 | assert_memory_lock(); |
1182 | ||
e90d96b1 SF |
1183 | /* add in the page list */ |
1184 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); | |
1185 | if (phys_page2 != -1) { | |
1186 | tb_alloc_page(tb, 1, phys_page2); | |
1187 | } else { | |
1188 | tb->page_addr[1] = -1; | |
1189 | } | |
1190 | ||
2e1ae44a | 1191 | /* add in the hash table */ |
4e2ca83e EC |
1192 | h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK, |
1193 | tb->trace_vcpu_dstate); | |
32359d52 | 1194 | qht_insert(&tb_ctx.htable, tb, h, NULL); |
2e1ae44a | 1195 | |
6eb062ab EC |
1196 | #ifdef CONFIG_USER_ONLY |
1197 | if (DEBUG_TB_CHECK_GATE) { | |
1198 | tb_page_check(); | |
1199 | } | |
e90d96b1 SF |
1200 | #endif |
1201 | } | |
1202 | ||
75692087 | 1203 | /* Called with mmap_lock held for user mode emulation. */ |
648f034c | 1204 | TranslationBlock *tb_gen_code(CPUState *cpu, |
5b6dd868 | 1205 | target_ulong pc, target_ulong cs_base, |
89fee74a | 1206 | uint32_t flags, int cflags) |
5b6dd868 | 1207 | { |
648f034c | 1208 | CPUArchState *env = cpu->env_ptr; |
5b6dd868 | 1209 | TranslationBlock *tb; |
5b6dd868 BS |
1210 | tb_page_addr_t phys_pc, phys_page2; |
1211 | target_ulong virt_page2; | |
fec88f64 | 1212 | tcg_insn_unit *gen_code_buf; |
fca8a500 | 1213 | int gen_code_size, search_size; |
fec88f64 | 1214 | #ifdef CONFIG_PROFILER |
c3fac113 | 1215 | TCGProfile *prof = &tcg_ctx->prof; |
fec88f64 RH |
1216 | int64_t ti; |
1217 | #endif | |
e505a063 | 1218 | assert_memory_lock(); |
5b6dd868 BS |
1219 | |
1220 | phys_pc = get_page_addr_code(env, pc); | |
b125f9dc | 1221 | |
e8feb96f | 1222 | buffer_overflow: |
5b6dd868 | 1223 | tb = tb_alloc(pc); |
b125f9dc | 1224 | if (unlikely(!tb)) { |
5b6dd868 | 1225 | /* flush must be done */ |
bbd77c18 | 1226 | tb_flush(cpu); |
3359baad | 1227 | mmap_unlock(); |
8499c8fc PD |
1228 | /* Make the execution loop process the flush as soon as possible. */ |
1229 | cpu->exception_index = EXCP_INTERRUPT; | |
3359baad | 1230 | cpu_loop_exit(cpu); |
5b6dd868 | 1231 | } |
fec88f64 | 1232 | |
b1311c4a | 1233 | gen_code_buf = tcg_ctx->code_gen_ptr; |
e7e168f4 | 1234 | tb->tc.ptr = gen_code_buf; |
2b48e10f | 1235 | tb->pc = pc; |
5b6dd868 BS |
1236 | tb->cs_base = cs_base; |
1237 | tb->flags = flags; | |
1238 | tb->cflags = cflags; | |
61a67f71 | 1239 | tb->trace_vcpu_dstate = *cpu->trace_dstate; |
b1311c4a | 1240 | tcg_ctx->tb_cflags = cflags; |
fec88f64 RH |
1241 | |
1242 | #ifdef CONFIG_PROFILER | |
c3fac113 EC |
1243 | /* includes aborted translations because of exceptions */ |
1244 | atomic_set(&prof->tb_count1, prof->tb_count1 + 1); | |
fec88f64 RH |
1245 | ti = profile_getclock(); |
1246 | #endif | |
1247 | ||
b1311c4a | 1248 | tcg_func_start(tcg_ctx); |
fec88f64 | 1249 | |
b1311c4a | 1250 | tcg_ctx->cpu = ENV_GET_CPU(env); |
9c489ea6 | 1251 | gen_intermediate_code(cpu, tb); |
b1311c4a | 1252 | tcg_ctx->cpu = NULL; |
fec88f64 | 1253 | |
e7e168f4 | 1254 | trace_translate_block(tb, tb->pc, tb->tc.ptr); |
fec88f64 RH |
1255 | |
1256 | /* generate machine code */ | |
f309101c SF |
1257 | tb->jmp_reset_offset[0] = TB_JMP_RESET_OFFSET_INVALID; |
1258 | tb->jmp_reset_offset[1] = TB_JMP_RESET_OFFSET_INVALID; | |
b1311c4a | 1259 | tcg_ctx->tb_jmp_reset_offset = tb->jmp_reset_offset; |
a8583393 | 1260 | if (TCG_TARGET_HAS_direct_jump) { |
b1311c4a EC |
1261 | tcg_ctx->tb_jmp_insn_offset = tb->jmp_target_arg; |
1262 | tcg_ctx->tb_jmp_target_addr = NULL; | |
a8583393 | 1263 | } else { |
b1311c4a EC |
1264 | tcg_ctx->tb_jmp_insn_offset = NULL; |
1265 | tcg_ctx->tb_jmp_target_addr = tb->jmp_target_arg; | |
a8583393 | 1266 | } |
fec88f64 RH |
1267 | |
1268 | #ifdef CONFIG_PROFILER | |
c3fac113 EC |
1269 | atomic_set(&prof->tb_count, prof->tb_count + 1); |
1270 | atomic_set(&prof->interm_time, prof->interm_time + profile_getclock() - ti); | |
0aecede6 | 1271 | ti = profile_getclock(); |
fec88f64 RH |
1272 | #endif |
1273 | ||
b125f9dc RH |
1274 | /* ??? Overflow could be handled better here. In particular, we |
1275 | don't need to re-do gen_intermediate_code, nor should we re-do | |
1276 | the tcg optimization currently hidden inside tcg_gen_code. All | |
1277 | that should be required is to flush the TBs, allocate a new TB, | |
1278 | re-initialize it per above, and re-do the actual code generation. */ | |
b1311c4a | 1279 | gen_code_size = tcg_gen_code(tcg_ctx, tb); |
b125f9dc RH |
1280 | if (unlikely(gen_code_size < 0)) { |
1281 | goto buffer_overflow; | |
1282 | } | |
fca8a500 | 1283 | search_size = encode_search(tb, (void *)gen_code_buf + gen_code_size); |
b125f9dc RH |
1284 | if (unlikely(search_size < 0)) { |
1285 | goto buffer_overflow; | |
1286 | } | |
2ac01d6d | 1287 | tb->tc.size = gen_code_size; |
fec88f64 RH |
1288 | |
1289 | #ifdef CONFIG_PROFILER | |
c3fac113 EC |
1290 | atomic_set(&prof->code_time, prof->code_time + profile_getclock() - ti); |
1291 | atomic_set(&prof->code_in_len, prof->code_in_len + tb->size); | |
1292 | atomic_set(&prof->code_out_len, prof->code_out_len + gen_code_size); | |
1293 | atomic_set(&prof->search_out_len, prof->search_out_len + search_size); | |
fec88f64 RH |
1294 | #endif |
1295 | ||
1296 | #ifdef DEBUG_DISAS | |
d977e1c2 AB |
1297 | if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && |
1298 | qemu_log_in_addr_range(tb->pc)) { | |
1ee73216 | 1299 | qemu_log_lock(); |
fec88f64 | 1300 | qemu_log("OUT: [size=%d]\n", gen_code_size); |
b1311c4a EC |
1301 | if (tcg_ctx->data_gen_ptr) { |
1302 | size_t code_size = tcg_ctx->data_gen_ptr - tb->tc.ptr; | |
57a26946 RH |
1303 | size_t data_size = gen_code_size - code_size; |
1304 | size_t i; | |
1305 | ||
e7e168f4 | 1306 | log_disas(tb->tc.ptr, code_size); |
57a26946 RH |
1307 | |
1308 | for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { | |
1309 | if (sizeof(tcg_target_ulong) == 8) { | |
1310 | qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", | |
b1311c4a EC |
1311 | (uintptr_t)tcg_ctx->data_gen_ptr + i, |
1312 | *(uint64_t *)(tcg_ctx->data_gen_ptr + i)); | |
57a26946 RH |
1313 | } else { |
1314 | qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n", | |
b1311c4a EC |
1315 | (uintptr_t)tcg_ctx->data_gen_ptr + i, |
1316 | *(uint32_t *)(tcg_ctx->data_gen_ptr + i)); | |
57a26946 RH |
1317 | } |
1318 | } | |
1319 | } else { | |
e7e168f4 | 1320 | log_disas(tb->tc.ptr, gen_code_size); |
57a26946 | 1321 | } |
fec88f64 RH |
1322 | qemu_log("\n"); |
1323 | qemu_log_flush(); | |
1ee73216 | 1324 | qemu_log_unlock(); |
fec88f64 RH |
1325 | } |
1326 | #endif | |
1327 | ||
e8feb96f | 1328 | atomic_set(&tcg_ctx->code_gen_ptr, (void *) |
fca8a500 | 1329 | ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size, |
e8feb96f | 1330 | CODE_GEN_ALIGN)); |
5b6dd868 | 1331 | |
901bc3de SF |
1332 | /* init jump list */ |
1333 | assert(((uintptr_t)tb & 3) == 0); | |
1334 | tb->jmp_list_first = (uintptr_t)tb | 2; | |
1335 | tb->jmp_list_next[0] = (uintptr_t)NULL; | |
1336 | tb->jmp_list_next[1] = (uintptr_t)NULL; | |
1337 | ||
1338 | /* init original jump addresses wich has been set during tcg_gen_code() */ | |
1339 | if (tb->jmp_reset_offset[0] != TB_JMP_RESET_OFFSET_INVALID) { | |
1340 | tb_reset_jump(tb, 0); | |
1341 | } | |
1342 | if (tb->jmp_reset_offset[1] != TB_JMP_RESET_OFFSET_INVALID) { | |
1343 | tb_reset_jump(tb, 1); | |
1344 | } | |
1345 | ||
5b6dd868 BS |
1346 | /* check next page if needed */ |
1347 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; | |
1348 | phys_page2 = -1; | |
1349 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { | |
1350 | phys_page2 = get_page_addr_code(env, virt_page2); | |
1351 | } | |
901bc3de SF |
1352 | /* As long as consistency of the TB stuff is provided by tb_lock in user |
1353 | * mode and is implicit in single-threaded softmmu emulation, no explicit | |
1354 | * memory barrier is required before tb_link_page() makes the TB visible | |
1355 | * through the physical hash table and physical page list. | |
1356 | */ | |
5b6dd868 | 1357 | tb_link_page(tb, phys_pc, phys_page2); |
be2cdc5e | 1358 | tcg_tb_insert(tb); |
5b6dd868 BS |
1359 | return tb; |
1360 | } | |
1361 | ||
1362 | /* | |
1363 | * Invalidate all TBs which intersect with the target physical address range | |
1364 | * [start;end[. NOTE: start and end may refer to *different* physical pages. | |
1365 | * 'is_cpu_write_access' should be true if called from a real cpu write | |
1366 | * access: the virtual CPU will exit the current TB if code is modified inside | |
1367 | * this TB. | |
75692087 | 1368 | * |
ba051fb5 AB |
1369 | * Called with mmap_lock held for user-mode emulation, grabs tb_lock |
1370 | * Called with tb_lock held for system-mode emulation | |
5b6dd868 | 1371 | */ |
ba051fb5 | 1372 | static void tb_invalidate_phys_range_1(tb_page_addr_t start, tb_page_addr_t end) |
5b6dd868 BS |
1373 | { |
1374 | while (start < end) { | |
35865339 | 1375 | tb_invalidate_phys_page_range(start, end, 0); |
5b6dd868 BS |
1376 | start &= TARGET_PAGE_MASK; |
1377 | start += TARGET_PAGE_SIZE; | |
1378 | } | |
1379 | } | |
1380 | ||
ba051fb5 AB |
1381 | #ifdef CONFIG_SOFTMMU |
1382 | void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end) | |
1383 | { | |
6ac3d7e8 | 1384 | assert_tb_locked(); |
ba051fb5 AB |
1385 | tb_invalidate_phys_range_1(start, end); |
1386 | } | |
1387 | #else | |
1388 | void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end) | |
1389 | { | |
1390 | assert_memory_lock(); | |
1391 | tb_lock(); | |
1392 | tb_invalidate_phys_range_1(start, end); | |
1393 | tb_unlock(); | |
1394 | } | |
1395 | #endif | |
5b6dd868 BS |
1396 | /* |
1397 | * Invalidate all TBs which intersect with the target physical address range | |
1398 | * [start;end[. NOTE: start and end must refer to the *same* physical page. | |
1399 | * 'is_cpu_write_access' should be true if called from a real cpu write | |
1400 | * access: the virtual CPU will exit the current TB if code is modified inside | |
1401 | * this TB. | |
75692087 | 1402 | * |
ba051fb5 AB |
1403 | * Called with tb_lock/mmap_lock held for user-mode emulation |
1404 | * Called with tb_lock held for system-mode emulation | |
5b6dd868 BS |
1405 | */ |
1406 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, | |
1407 | int is_cpu_write_access) | |
1408 | { | |
1e05197f | 1409 | TranslationBlock *tb; |
5b6dd868 BS |
1410 | tb_page_addr_t tb_start, tb_end; |
1411 | PageDesc *p; | |
1412 | int n; | |
1413 | #ifdef TARGET_HAS_PRECISE_SMC | |
9b990ee5 RH |
1414 | CPUState *cpu = current_cpu; |
1415 | CPUArchState *env = NULL; | |
5b6dd868 BS |
1416 | int current_tb_not_found = is_cpu_write_access; |
1417 | TranslationBlock *current_tb = NULL; | |
1418 | int current_tb_modified = 0; | |
1419 | target_ulong current_pc = 0; | |
1420 | target_ulong current_cs_base = 0; | |
89fee74a | 1421 | uint32_t current_flags = 0; |
5b6dd868 BS |
1422 | #endif /* TARGET_HAS_PRECISE_SMC */ |
1423 | ||
e505a063 | 1424 | assert_memory_lock(); |
6ac3d7e8 | 1425 | assert_tb_locked(); |
e505a063 | 1426 | |
5b6dd868 BS |
1427 | p = page_find(start >> TARGET_PAGE_BITS); |
1428 | if (!p) { | |
1429 | return; | |
1430 | } | |
baea4fae | 1431 | #if defined(TARGET_HAS_PRECISE_SMC) |
4917cf44 AF |
1432 | if (cpu != NULL) { |
1433 | env = cpu->env_ptr; | |
d77953b9 | 1434 | } |
4917cf44 | 1435 | #endif |
5b6dd868 BS |
1436 | |
1437 | /* we remove all the TBs in the range [start, end[ */ | |
1438 | /* XXX: see if in some cases it could be faster to invalidate all | |
1439 | the code */ | |
1e05197f | 1440 | PAGE_FOR_EACH_TB(p, tb, n) { |
5b6dd868 BS |
1441 | /* NOTE: this is subtle as a TB may span two physical pages */ |
1442 | if (n == 0) { | |
1443 | /* NOTE: tb_end may be after the end of the page, but | |
1444 | it is not a problem */ | |
1445 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
1446 | tb_end = tb_start + tb->size; | |
1447 | } else { | |
1448 | tb_start = tb->page_addr[1]; | |
1449 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1450 | } | |
1451 | if (!(tb_end <= start || tb_start >= end)) { | |
1452 | #ifdef TARGET_HAS_PRECISE_SMC | |
1453 | if (current_tb_not_found) { | |
1454 | current_tb_not_found = 0; | |
1455 | current_tb = NULL; | |
93afeade | 1456 | if (cpu->mem_io_pc) { |
5b6dd868 | 1457 | /* now we have a real cpu fault */ |
be2cdc5e | 1458 | current_tb = tcg_tb_lookup(cpu->mem_io_pc); |
5b6dd868 BS |
1459 | } |
1460 | } | |
1461 | if (current_tb == tb && | |
1462 | (current_tb->cflags & CF_COUNT_MASK) != 1) { | |
1463 | /* If we are modifying the current TB, we must stop | |
1464 | its execution. We could be more precise by checking | |
1465 | that the modification is after the current PC, but it | |
1466 | would require a specialized function to partially | |
1467 | restore the CPU state */ | |
1468 | ||
1469 | current_tb_modified = 1; | |
afd46fca PD |
1470 | cpu_restore_state_from_tb(cpu, current_tb, |
1471 | cpu->mem_io_pc, true); | |
5b6dd868 BS |
1472 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1473 | ¤t_flags); | |
1474 | } | |
1475 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
5b6dd868 | 1476 | tb_phys_invalidate(tb, -1); |
5b6dd868 | 1477 | } |
5b6dd868 BS |
1478 | } |
1479 | #if !defined(CONFIG_USER_ONLY) | |
1480 | /* if no code remaining, no need to continue to use slow writes */ | |
1481 | if (!p->first_tb) { | |
1482 | invalidate_page_bitmap(p); | |
fc377bcf | 1483 | tlb_unprotect_code(start); |
5b6dd868 BS |
1484 | } |
1485 | #endif | |
1486 | #ifdef TARGET_HAS_PRECISE_SMC | |
1487 | if (current_tb_modified) { | |
9b990ee5 RH |
1488 | /* Force execution of one insn next time. */ |
1489 | cpu->cflags_next_tb = 1 | curr_cflags(); | |
6886b980 | 1490 | cpu_loop_exit_noexc(cpu); |
5b6dd868 BS |
1491 | } |
1492 | #endif | |
1493 | } | |
1494 | ||
6fad459c | 1495 | #ifdef CONFIG_SOFTMMU |
ba051fb5 AB |
1496 | /* len must be <= 8 and start must be a multiple of len. |
1497 | * Called via softmmu_template.h when code areas are written to with | |
8d04fb55 | 1498 | * iothread mutex not held. |
ba051fb5 | 1499 | */ |
5b6dd868 BS |
1500 | void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) |
1501 | { | |
1502 | PageDesc *p; | |
5b6dd868 BS |
1503 | |
1504 | #if 0 | |
1505 | if (1) { | |
1506 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", | |
1507 | cpu_single_env->mem_io_vaddr, len, | |
1508 | cpu_single_env->eip, | |
1509 | cpu_single_env->eip + | |
1510 | (intptr_t)cpu_single_env->segs[R_CS].base); | |
1511 | } | |
1512 | #endif | |
ba051fb5 AB |
1513 | assert_memory_lock(); |
1514 | ||
5b6dd868 BS |
1515 | p = page_find(start >> TARGET_PAGE_BITS); |
1516 | if (!p) { | |
1517 | return; | |
1518 | } | |
fc377bcf PB |
1519 | if (!p->code_bitmap && |
1520 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD) { | |
7d7500d9 PB |
1521 | /* build code bitmap. FIXME: writes should be protected by |
1522 | * tb_lock, reads by tb_lock or RCU. | |
1523 | */ | |
fc377bcf PB |
1524 | build_page_bitmap(p); |
1525 | } | |
5b6dd868 | 1526 | if (p->code_bitmap) { |
510a647f EC |
1527 | unsigned int nr; |
1528 | unsigned long b; | |
1529 | ||
1530 | nr = start & ~TARGET_PAGE_MASK; | |
1531 | b = p->code_bitmap[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG - 1)); | |
5b6dd868 BS |
1532 | if (b & ((1 << len) - 1)) { |
1533 | goto do_invalidate; | |
1534 | } | |
1535 | } else { | |
1536 | do_invalidate: | |
1537 | tb_invalidate_phys_page_range(start, start + len, 1); | |
1538 | } | |
1539 | } | |
6fad459c | 1540 | #else |
75809229 PM |
1541 | /* Called with mmap_lock held. If pc is not 0 then it indicates the |
1542 | * host PC of the faulting store instruction that caused this invalidate. | |
1543 | * Returns true if the caller needs to abort execution of the current | |
1544 | * TB (because it was modified by this store and the guest CPU has | |
1545 | * precise-SMC semantics). | |
1546 | */ | |
1547 | static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc) | |
5b6dd868 BS |
1548 | { |
1549 | TranslationBlock *tb; | |
1550 | PageDesc *p; | |
1551 | int n; | |
1552 | #ifdef TARGET_HAS_PRECISE_SMC | |
1553 | TranslationBlock *current_tb = NULL; | |
4917cf44 AF |
1554 | CPUState *cpu = current_cpu; |
1555 | CPUArchState *env = NULL; | |
5b6dd868 BS |
1556 | int current_tb_modified = 0; |
1557 | target_ulong current_pc = 0; | |
1558 | target_ulong current_cs_base = 0; | |
89fee74a | 1559 | uint32_t current_flags = 0; |
5b6dd868 BS |
1560 | #endif |
1561 | ||
ba051fb5 AB |
1562 | assert_memory_lock(); |
1563 | ||
5b6dd868 BS |
1564 | addr &= TARGET_PAGE_MASK; |
1565 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1566 | if (!p) { | |
75809229 | 1567 | return false; |
5b6dd868 | 1568 | } |
a5e99826 FK |
1569 | |
1570 | tb_lock(); | |
5b6dd868 | 1571 | #ifdef TARGET_HAS_PRECISE_SMC |
1e05197f | 1572 | if (p->first_tb && pc != 0) { |
be2cdc5e | 1573 | current_tb = tcg_tb_lookup(pc); |
5b6dd868 | 1574 | } |
4917cf44 AF |
1575 | if (cpu != NULL) { |
1576 | env = cpu->env_ptr; | |
d77953b9 | 1577 | } |
5b6dd868 | 1578 | #endif |
1e05197f | 1579 | PAGE_FOR_EACH_TB(p, tb, n) { |
5b6dd868 BS |
1580 | #ifdef TARGET_HAS_PRECISE_SMC |
1581 | if (current_tb == tb && | |
1582 | (current_tb->cflags & CF_COUNT_MASK) != 1) { | |
1583 | /* If we are modifying the current TB, we must stop | |
1584 | its execution. We could be more precise by checking | |
1585 | that the modification is after the current PC, but it | |
1586 | would require a specialized function to partially | |
1587 | restore the CPU state */ | |
1588 | ||
1589 | current_tb_modified = 1; | |
afd46fca | 1590 | cpu_restore_state_from_tb(cpu, current_tb, pc, true); |
5b6dd868 BS |
1591 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1592 | ¤t_flags); | |
1593 | } | |
1594 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1595 | tb_phys_invalidate(tb, addr); | |
5b6dd868 | 1596 | } |
1e05197f | 1597 | p->first_tb = (uintptr_t)NULL; |
5b6dd868 BS |
1598 | #ifdef TARGET_HAS_PRECISE_SMC |
1599 | if (current_tb_modified) { | |
9b990ee5 RH |
1600 | /* Force execution of one insn next time. */ |
1601 | cpu->cflags_next_tb = 1 | curr_cflags(); | |
a5e99826 FK |
1602 | /* tb_lock will be reset after cpu_loop_exit_noexc longjmps |
1603 | * back into the cpu_exec loop. */ | |
75809229 | 1604 | return true; |
5b6dd868 BS |
1605 | } |
1606 | #endif | |
a5e99826 FK |
1607 | tb_unlock(); |
1608 | ||
75809229 | 1609 | return false; |
5b6dd868 BS |
1610 | } |
1611 | #endif | |
1612 | ||
ec53b45b | 1613 | #if !defined(CONFIG_USER_ONLY) |
c874dc4f | 1614 | void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) |
5b6dd868 BS |
1615 | { |
1616 | ram_addr_t ram_addr; | |
5c8a00ce | 1617 | MemoryRegion *mr; |
149f54b5 | 1618 | hwaddr l = 1; |
5b6dd868 | 1619 | |
41063e1e | 1620 | rcu_read_lock(); |
bc6b1cec | 1621 | mr = address_space_translate(as, addr, &addr, &l, false, attrs); |
5c8a00ce PB |
1622 | if (!(memory_region_is_ram(mr) |
1623 | || memory_region_is_romd(mr))) { | |
41063e1e | 1624 | rcu_read_unlock(); |
5b6dd868 BS |
1625 | return; |
1626 | } | |
e4e69794 | 1627 | ram_addr = memory_region_get_ram_addr(mr) + addr; |
ba051fb5 | 1628 | tb_lock(); |
5b6dd868 | 1629 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
ba051fb5 | 1630 | tb_unlock(); |
41063e1e | 1631 | rcu_read_unlock(); |
5b6dd868 | 1632 | } |
ec53b45b | 1633 | #endif /* !defined(CONFIG_USER_ONLY) */ |
5b6dd868 | 1634 | |
7d7500d9 | 1635 | /* Called with tb_lock held. */ |
239c51a5 | 1636 | void tb_check_watchpoint(CPUState *cpu) |
5b6dd868 BS |
1637 | { |
1638 | TranslationBlock *tb; | |
1639 | ||
be2cdc5e | 1640 | tb = tcg_tb_lookup(cpu->mem_io_pc); |
8d302e76 AJ |
1641 | if (tb) { |
1642 | /* We can use retranslation to find the PC. */ | |
afd46fca | 1643 | cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc, true); |
8d302e76 AJ |
1644 | tb_phys_invalidate(tb, -1); |
1645 | } else { | |
1646 | /* The exception probably happened in a helper. The CPU state should | |
1647 | have been saved before calling it. Fetch the PC from there. */ | |
1648 | CPUArchState *env = cpu->env_ptr; | |
1649 | target_ulong pc, cs_base; | |
1650 | tb_page_addr_t addr; | |
89fee74a | 1651 | uint32_t flags; |
8d302e76 AJ |
1652 | |
1653 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); | |
1654 | addr = get_page_addr_code(env, pc); | |
1655 | tb_invalidate_phys_range(addr, addr + 1); | |
5b6dd868 | 1656 | } |
5b6dd868 BS |
1657 | } |
1658 | ||
1659 | #ifndef CONFIG_USER_ONLY | |
5b6dd868 | 1660 | /* in deterministic execution mode, instructions doing device I/Os |
8d04fb55 JK |
1661 | * must be at the end of the TB. |
1662 | * | |
1663 | * Called by softmmu_template.h, with iothread mutex not held. | |
1664 | */ | |
90b40a69 | 1665 | void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) |
5b6dd868 | 1666 | { |
a47dddd7 | 1667 | #if defined(TARGET_MIPS) || defined(TARGET_SH4) |
90b40a69 | 1668 | CPUArchState *env = cpu->env_ptr; |
a47dddd7 | 1669 | #endif |
5b6dd868 | 1670 | TranslationBlock *tb; |
87f963be | 1671 | uint32_t n; |
5b6dd868 | 1672 | |
a5e99826 | 1673 | tb_lock(); |
be2cdc5e | 1674 | tb = tcg_tb_lookup(retaddr); |
5b6dd868 | 1675 | if (!tb) { |
a47dddd7 | 1676 | cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p", |
5b6dd868 BS |
1677 | (void *)retaddr); |
1678 | } | |
afd46fca | 1679 | cpu_restore_state_from_tb(cpu, tb, retaddr, true); |
87f963be | 1680 | |
5b6dd868 BS |
1681 | /* On MIPS and SH, delay slot instructions can only be restarted if |
1682 | they were already the first instruction in the TB. If this is not | |
1683 | the first instruction in a TB then re-execute the preceding | |
1684 | branch. */ | |
87f963be | 1685 | n = 1; |
5b6dd868 | 1686 | #if defined(TARGET_MIPS) |
87f963be RH |
1687 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 |
1688 | && env->active_tc.PC != tb->pc) { | |
c3577479 | 1689 | env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); |
28ecfd7a | 1690 | cpu->icount_decr.u16.low++; |
5b6dd868 | 1691 | env->hflags &= ~MIPS_HFLAG_BMASK; |
87f963be | 1692 | n = 2; |
5b6dd868 BS |
1693 | } |
1694 | #elif defined(TARGET_SH4) | |
1695 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
87f963be | 1696 | && env->pc != tb->pc) { |
5b6dd868 | 1697 | env->pc -= 2; |
28ecfd7a | 1698 | cpu->icount_decr.u16.low++; |
5b6dd868 | 1699 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
87f963be | 1700 | n = 2; |
5b6dd868 BS |
1701 | } |
1702 | #endif | |
5b6dd868 | 1703 | |
87f963be RH |
1704 | /* Generate a new TB executing the I/O insn. */ |
1705 | cpu->cflags_next_tb = curr_cflags() | CF_LAST_IO | n; | |
9b990ee5 | 1706 | |
02d57ea1 SF |
1707 | if (tb->cflags & CF_NOCACHE) { |
1708 | if (tb->orig_tb) { | |
1709 | /* Invalidate original TB if this TB was generated in | |
1710 | * cpu_exec_nocache() */ | |
1711 | tb_phys_invalidate(tb->orig_tb, -1); | |
1712 | } | |
be2cdc5e | 1713 | tcg_tb_remove(tb); |
02d57ea1 | 1714 | } |
a5e99826 | 1715 | |
5b6dd868 | 1716 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
a5e99826 FK |
1717 | * the first in the TB) then we end up generating a whole new TB and |
1718 | * repeating the fault, which is horribly inefficient. | |
1719 | * Better would be to execute just this insn uncached, or generate a | |
1720 | * second new TB. | |
1721 | * | |
1722 | * cpu_loop_exit_noexc will longjmp back to cpu_exec where the | |
1723 | * tb_lock gets reset. | |
1724 | */ | |
6886b980 | 1725 | cpu_loop_exit_noexc(cpu); |
5b6dd868 BS |
1726 | } |
1727 | ||
f3ced3c5 | 1728 | static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr) |
5b6dd868 | 1729 | { |
f3ced3c5 | 1730 | unsigned int i, i0 = tb_jmp_cache_hash_page(page_addr); |
5b6dd868 | 1731 | |
f3ced3c5 EC |
1732 | for (i = 0; i < TB_JMP_PAGE_SIZE; i++) { |
1733 | atomic_set(&cpu->tb_jmp_cache[i0 + i], NULL); | |
1734 | } | |
1735 | } | |
1736 | ||
1737 | void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr) | |
1738 | { | |
5b6dd868 BS |
1739 | /* Discard jump cache entries for any tb which might potentially |
1740 | overlap the flushed page. */ | |
f3ced3c5 EC |
1741 | tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE); |
1742 | tb_jmp_cache_clear_page(cpu, addr); | |
5b6dd868 BS |
1743 | } |
1744 | ||
7266ae91 EC |
1745 | static void print_qht_statistics(FILE *f, fprintf_function cpu_fprintf, |
1746 | struct qht_stats hst) | |
1747 | { | |
1748 | uint32_t hgram_opts; | |
1749 | size_t hgram_bins; | |
1750 | char *hgram; | |
1751 | ||
1752 | if (!hst.head_buckets) { | |
1753 | return; | |
1754 | } | |
1755 | cpu_fprintf(f, "TB hash buckets %zu/%zu (%0.2f%% head buckets used)\n", | |
1756 | hst.used_head_buckets, hst.head_buckets, | |
1757 | (double)hst.used_head_buckets / hst.head_buckets * 100); | |
1758 | ||
1759 | hgram_opts = QDIST_PR_BORDER | QDIST_PR_LABELS; | |
1760 | hgram_opts |= QDIST_PR_100X | QDIST_PR_PERCENT; | |
1761 | if (qdist_xmax(&hst.occupancy) - qdist_xmin(&hst.occupancy) == 1) { | |
1762 | hgram_opts |= QDIST_PR_NODECIMAL; | |
1763 | } | |
1764 | hgram = qdist_pr(&hst.occupancy, 10, hgram_opts); | |
1765 | cpu_fprintf(f, "TB hash occupancy %0.2f%% avg chain occ. Histogram: %s\n", | |
1766 | qdist_avg(&hst.occupancy) * 100, hgram); | |
1767 | g_free(hgram); | |
1768 | ||
1769 | hgram_opts = QDIST_PR_BORDER | QDIST_PR_LABELS; | |
1770 | hgram_bins = qdist_xmax(&hst.chain) - qdist_xmin(&hst.chain); | |
1771 | if (hgram_bins > 10) { | |
1772 | hgram_bins = 10; | |
1773 | } else { | |
1774 | hgram_bins = 0; | |
1775 | hgram_opts |= QDIST_PR_NODECIMAL | QDIST_PR_NOBINRANGE; | |
1776 | } | |
1777 | hgram = qdist_pr(&hst.chain, hgram_bins, hgram_opts); | |
1778 | cpu_fprintf(f, "TB hash avg chain %0.3f buckets. Histogram: %s\n", | |
1779 | qdist_avg(&hst.chain), hgram); | |
1780 | g_free(hgram); | |
1781 | } | |
1782 | ||
2ac01d6d | 1783 | struct tb_tree_stats { |
be2cdc5e | 1784 | size_t nb_tbs; |
f19c6cc6 | 1785 | size_t host_size; |
2ac01d6d EC |
1786 | size_t target_size; |
1787 | size_t max_target_size; | |
1788 | size_t direct_jmp_count; | |
1789 | size_t direct_jmp2_count; | |
1790 | size_t cross_page; | |
1791 | }; | |
1792 | ||
1793 | static gboolean tb_tree_stats_iter(gpointer key, gpointer value, gpointer data) | |
1794 | { | |
1795 | const TranslationBlock *tb = value; | |
1796 | struct tb_tree_stats *tst = data; | |
1797 | ||
be2cdc5e | 1798 | tst->nb_tbs++; |
f19c6cc6 | 1799 | tst->host_size += tb->tc.size; |
2ac01d6d EC |
1800 | tst->target_size += tb->size; |
1801 | if (tb->size > tst->max_target_size) { | |
1802 | tst->max_target_size = tb->size; | |
1803 | } | |
1804 | if (tb->page_addr[1] != -1) { | |
1805 | tst->cross_page++; | |
1806 | } | |
1807 | if (tb->jmp_reset_offset[0] != TB_JMP_RESET_OFFSET_INVALID) { | |
1808 | tst->direct_jmp_count++; | |
1809 | if (tb->jmp_reset_offset[1] != TB_JMP_RESET_OFFSET_INVALID) { | |
1810 | tst->direct_jmp2_count++; | |
1811 | } | |
1812 | } | |
1813 | return false; | |
1814 | } | |
1815 | ||
5b6dd868 BS |
1816 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) |
1817 | { | |
2ac01d6d | 1818 | struct tb_tree_stats tst = {}; |
329844d4 | 1819 | struct qht_stats hst; |
2ac01d6d | 1820 | size_t nb_tbs; |
5b6dd868 | 1821 | |
be2cdc5e EC |
1822 | tcg_tb_foreach(tb_tree_stats_iter, &tst); |
1823 | nb_tbs = tst.nb_tbs; | |
5b6dd868 BS |
1824 | /* XXX: avoid using doubles ? */ |
1825 | cpu_fprintf(f, "Translation buffer state:\n"); | |
f19c6cc6 EC |
1826 | /* |
1827 | * Report total code size including the padding and TB structs; | |
1828 | * otherwise users might think "-tb-size" is not honoured. | |
1829 | * For avg host size we use the precise numbers from tb_tree_stats though. | |
1830 | */ | |
e8feb96f EC |
1831 | cpu_fprintf(f, "gen code size %zu/%zu\n", |
1832 | tcg_code_size(), tcg_code_capacity()); | |
2ac01d6d EC |
1833 | cpu_fprintf(f, "TB count %zu\n", nb_tbs); |
1834 | cpu_fprintf(f, "TB avg target size %zu max=%zu bytes\n", | |
1835 | nb_tbs ? tst.target_size / nb_tbs : 0, | |
1836 | tst.max_target_size); | |
f19c6cc6 EC |
1837 | cpu_fprintf(f, "TB avg host size %zu bytes (expansion ratio: %0.1f)\n", |
1838 | nb_tbs ? tst.host_size / nb_tbs : 0, | |
1839 | tst.target_size ? (double)tst.host_size / tst.target_size : 0); | |
2ac01d6d EC |
1840 | cpu_fprintf(f, "cross page TB count %zu (%zu%%)\n", tst.cross_page, |
1841 | nb_tbs ? (tst.cross_page * 100) / nb_tbs : 0); | |
1842 | cpu_fprintf(f, "direct jump count %zu (%zu%%) (2 jumps=%zu %zu%%)\n", | |
1843 | tst.direct_jmp_count, | |
1844 | nb_tbs ? (tst.direct_jmp_count * 100) / nb_tbs : 0, | |
1845 | tst.direct_jmp2_count, | |
1846 | nb_tbs ? (tst.direct_jmp2_count * 100) / nb_tbs : 0); | |
329844d4 | 1847 | |
44ded3d0 | 1848 | qht_statistics_init(&tb_ctx.htable, &hst); |
7266ae91 | 1849 | print_qht_statistics(f, cpu_fprintf, hst); |
329844d4 EC |
1850 | qht_statistics_destroy(&hst); |
1851 | ||
5b6dd868 | 1852 | cpu_fprintf(f, "\nStatistics:\n"); |
3359baad | 1853 | cpu_fprintf(f, "TB flush count %u\n", |
44ded3d0 | 1854 | atomic_read(&tb_ctx.tb_flush_count)); |
128ed227 | 1855 | cpu_fprintf(f, "TB invalidate count %zu\n", tcg_tb_phys_invalidate_count()); |
83974cf4 | 1856 | cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count()); |
5b6dd868 BS |
1857 | tcg_dump_info(f, cpu_fprintf); |
1858 | } | |
1859 | ||
246ae24d MF |
1860 | void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf) |
1861 | { | |
1862 | tcg_dump_op_count(f, cpu_fprintf); | |
1863 | } | |
1864 | ||
5b6dd868 BS |
1865 | #else /* CONFIG_USER_ONLY */ |
1866 | ||
c3affe56 | 1867 | void cpu_interrupt(CPUState *cpu, int mask) |
5b6dd868 | 1868 | { |
8d04fb55 | 1869 | g_assert(qemu_mutex_iothread_locked()); |
259186a7 | 1870 | cpu->interrupt_request |= mask; |
1aab16c2 | 1871 | cpu->icount_decr.u16.high = -1; |
5b6dd868 BS |
1872 | } |
1873 | ||
1874 | /* | |
1875 | * Walks guest process memory "regions" one by one | |
1876 | * and calls callback function 'fn' for each region. | |
1877 | */ | |
1878 | struct walk_memory_regions_data { | |
1879 | walk_memory_regions_fn fn; | |
1880 | void *priv; | |
1a1c4db9 | 1881 | target_ulong start; |
5b6dd868 BS |
1882 | int prot; |
1883 | }; | |
1884 | ||
1885 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, | |
1a1c4db9 | 1886 | target_ulong end, int new_prot) |
5b6dd868 | 1887 | { |
1a1c4db9 | 1888 | if (data->start != -1u) { |
5b6dd868 BS |
1889 | int rc = data->fn(data->priv, data->start, end, data->prot); |
1890 | if (rc != 0) { | |
1891 | return rc; | |
1892 | } | |
1893 | } | |
1894 | ||
1a1c4db9 | 1895 | data->start = (new_prot ? end : -1u); |
5b6dd868 BS |
1896 | data->prot = new_prot; |
1897 | ||
1898 | return 0; | |
1899 | } | |
1900 | ||
1901 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, | |
1a1c4db9 | 1902 | target_ulong base, int level, void **lp) |
5b6dd868 | 1903 | { |
1a1c4db9 | 1904 | target_ulong pa; |
5b6dd868 BS |
1905 | int i, rc; |
1906 | ||
1907 | if (*lp == NULL) { | |
1908 | return walk_memory_regions_end(data, base, 0); | |
1909 | } | |
1910 | ||
1911 | if (level == 0) { | |
1912 | PageDesc *pd = *lp; | |
1913 | ||
03f49957 | 1914 | for (i = 0; i < V_L2_SIZE; ++i) { |
5b6dd868 BS |
1915 | int prot = pd[i].flags; |
1916 | ||
1917 | pa = base | (i << TARGET_PAGE_BITS); | |
1918 | if (prot != data->prot) { | |
1919 | rc = walk_memory_regions_end(data, pa, prot); | |
1920 | if (rc != 0) { | |
1921 | return rc; | |
1922 | } | |
1923 | } | |
1924 | } | |
1925 | } else { | |
1926 | void **pp = *lp; | |
1927 | ||
03f49957 | 1928 | for (i = 0; i < V_L2_SIZE; ++i) { |
1a1c4db9 | 1929 | pa = base | ((target_ulong)i << |
03f49957 | 1930 | (TARGET_PAGE_BITS + V_L2_BITS * level)); |
5b6dd868 BS |
1931 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); |
1932 | if (rc != 0) { | |
1933 | return rc; | |
1934 | } | |
1935 | } | |
1936 | } | |
1937 | ||
1938 | return 0; | |
1939 | } | |
1940 | ||
1941 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) | |
1942 | { | |
1943 | struct walk_memory_regions_data data; | |
66ec9f49 | 1944 | uintptr_t i, l1_sz = v_l1_size; |
5b6dd868 BS |
1945 | |
1946 | data.fn = fn; | |
1947 | data.priv = priv; | |
1a1c4db9 | 1948 | data.start = -1u; |
5b6dd868 BS |
1949 | data.prot = 0; |
1950 | ||
66ec9f49 VK |
1951 | for (i = 0; i < l1_sz; i++) { |
1952 | target_ulong base = i << (v_l1_shift + TARGET_PAGE_BITS); | |
1953 | int rc = walk_memory_regions_1(&data, base, v_l2_levels, l1_map + i); | |
5b6dd868 BS |
1954 | if (rc != 0) { |
1955 | return rc; | |
1956 | } | |
1957 | } | |
1958 | ||
1959 | return walk_memory_regions_end(&data, 0, 0); | |
1960 | } | |
1961 | ||
1a1c4db9 MI |
1962 | static int dump_region(void *priv, target_ulong start, |
1963 | target_ulong end, unsigned long prot) | |
5b6dd868 BS |
1964 | { |
1965 | FILE *f = (FILE *)priv; | |
1966 | ||
1a1c4db9 MI |
1967 | (void) fprintf(f, TARGET_FMT_lx"-"TARGET_FMT_lx |
1968 | " "TARGET_FMT_lx" %c%c%c\n", | |
5b6dd868 BS |
1969 | start, end, end - start, |
1970 | ((prot & PAGE_READ) ? 'r' : '-'), | |
1971 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
1972 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
1973 | ||
1974 | return 0; | |
1975 | } | |
1976 | ||
1977 | /* dump memory mappings */ | |
1978 | void page_dump(FILE *f) | |
1979 | { | |
1a1c4db9 | 1980 | const int length = sizeof(target_ulong) * 2; |
227b8175 SW |
1981 | (void) fprintf(f, "%-*s %-*s %-*s %s\n", |
1982 | length, "start", length, "end", length, "size", "prot"); | |
5b6dd868 BS |
1983 | walk_memory_regions(f, dump_region); |
1984 | } | |
1985 | ||
1986 | int page_get_flags(target_ulong address) | |
1987 | { | |
1988 | PageDesc *p; | |
1989 | ||
1990 | p = page_find(address >> TARGET_PAGE_BITS); | |
1991 | if (!p) { | |
1992 | return 0; | |
1993 | } | |
1994 | return p->flags; | |
1995 | } | |
1996 | ||
1997 | /* Modify the flags of a page and invalidate the code if necessary. | |
1998 | The flag PAGE_WRITE_ORG is positioned automatically depending | |
1999 | on PAGE_WRITE. The mmap_lock should already be held. */ | |
2000 | void page_set_flags(target_ulong start, target_ulong end, int flags) | |
2001 | { | |
2002 | target_ulong addr, len; | |
2003 | ||
2004 | /* This function should never be called with addresses outside the | |
2005 | guest address space. If this assert fires, it probably indicates | |
2006 | a missing call to h2g_valid. */ | |
2007 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS | |
de258eb0 | 2008 | assert(end <= ((target_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
5b6dd868 BS |
2009 | #endif |
2010 | assert(start < end); | |
e505a063 | 2011 | assert_memory_lock(); |
5b6dd868 BS |
2012 | |
2013 | start = start & TARGET_PAGE_MASK; | |
2014 | end = TARGET_PAGE_ALIGN(end); | |
2015 | ||
2016 | if (flags & PAGE_WRITE) { | |
2017 | flags |= PAGE_WRITE_ORG; | |
2018 | } | |
2019 | ||
2020 | for (addr = start, len = end - start; | |
2021 | len != 0; | |
2022 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
2023 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
2024 | ||
2025 | /* If the write protection bit is set, then we invalidate | |
2026 | the code inside. */ | |
2027 | if (!(p->flags & PAGE_WRITE) && | |
2028 | (flags & PAGE_WRITE) && | |
2029 | p->first_tb) { | |
75809229 | 2030 | tb_invalidate_phys_page(addr, 0); |
5b6dd868 BS |
2031 | } |
2032 | p->flags = flags; | |
2033 | } | |
2034 | } | |
2035 | ||
2036 | int page_check_range(target_ulong start, target_ulong len, int flags) | |
2037 | { | |
2038 | PageDesc *p; | |
2039 | target_ulong end; | |
2040 | target_ulong addr; | |
2041 | ||
2042 | /* This function should never be called with addresses outside the | |
2043 | guest address space. If this assert fires, it probably indicates | |
2044 | a missing call to h2g_valid. */ | |
2045 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS | |
1a1c4db9 | 2046 | assert(start < ((target_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
5b6dd868 BS |
2047 | #endif |
2048 | ||
2049 | if (len == 0) { | |
2050 | return 0; | |
2051 | } | |
2052 | if (start + len - 1 < start) { | |
2053 | /* We've wrapped around. */ | |
2054 | return -1; | |
2055 | } | |
2056 | ||
2057 | /* must do before we loose bits in the next step */ | |
2058 | end = TARGET_PAGE_ALIGN(start + len); | |
2059 | start = start & TARGET_PAGE_MASK; | |
2060 | ||
2061 | for (addr = start, len = end - start; | |
2062 | len != 0; | |
2063 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
2064 | p = page_find(addr >> TARGET_PAGE_BITS); | |
2065 | if (!p) { | |
2066 | return -1; | |
2067 | } | |
2068 | if (!(p->flags & PAGE_VALID)) { | |
2069 | return -1; | |
2070 | } | |
2071 | ||
2072 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) { | |
2073 | return -1; | |
2074 | } | |
2075 | if (flags & PAGE_WRITE) { | |
2076 | if (!(p->flags & PAGE_WRITE_ORG)) { | |
2077 | return -1; | |
2078 | } | |
2079 | /* unprotect the page if it was put read-only because it | |
2080 | contains translated code */ | |
2081 | if (!(p->flags & PAGE_WRITE)) { | |
f213e72f | 2082 | if (!page_unprotect(addr, 0)) { |
5b6dd868 BS |
2083 | return -1; |
2084 | } | |
2085 | } | |
5b6dd868 BS |
2086 | } |
2087 | } | |
2088 | return 0; | |
2089 | } | |
2090 | ||
2091 | /* called from signal handler: invalidate the code and unprotect the | |
f213e72f PM |
2092 | * page. Return 0 if the fault was not handled, 1 if it was handled, |
2093 | * and 2 if it was handled but the caller must cause the TB to be | |
2094 | * immediately exited. (We can only return 2 if the 'pc' argument is | |
2095 | * non-zero.) | |
2096 | */ | |
2097 | int page_unprotect(target_ulong address, uintptr_t pc) | |
5b6dd868 BS |
2098 | { |
2099 | unsigned int prot; | |
7399a337 | 2100 | bool current_tb_invalidated; |
5b6dd868 BS |
2101 | PageDesc *p; |
2102 | target_ulong host_start, host_end, addr; | |
2103 | ||
2104 | /* Technically this isn't safe inside a signal handler. However we | |
2105 | know this only ever happens in a synchronous SEGV handler, so in | |
2106 | practice it seems to be ok. */ | |
2107 | mmap_lock(); | |
2108 | ||
2109 | p = page_find(address >> TARGET_PAGE_BITS); | |
2110 | if (!p) { | |
2111 | mmap_unlock(); | |
2112 | return 0; | |
2113 | } | |
2114 | ||
2115 | /* if the page was really writable, then we change its | |
2116 | protection back to writable */ | |
9c4bbee9 | 2117 | if (p->flags & PAGE_WRITE_ORG) { |
7399a337 | 2118 | current_tb_invalidated = false; |
9c4bbee9 PM |
2119 | if (p->flags & PAGE_WRITE) { |
2120 | /* If the page is actually marked WRITE then assume this is because | |
2121 | * this thread raced with another one which got here first and | |
2122 | * set the page to PAGE_WRITE and did the TB invalidate for us. | |
2123 | */ | |
2124 | #ifdef TARGET_HAS_PRECISE_SMC | |
be2cdc5e | 2125 | TranslationBlock *current_tb = tcg_tb_lookup(pc); |
9c4bbee9 PM |
2126 | if (current_tb) { |
2127 | current_tb_invalidated = tb_cflags(current_tb) & CF_INVALID; | |
6eb062ab | 2128 | } |
5b6dd868 | 2129 | #endif |
9c4bbee9 PM |
2130 | } else { |
2131 | host_start = address & qemu_host_page_mask; | |
2132 | host_end = host_start + qemu_host_page_size; | |
2133 | ||
2134 | prot = 0; | |
2135 | for (addr = host_start; addr < host_end; addr += TARGET_PAGE_SIZE) { | |
2136 | p = page_find(addr >> TARGET_PAGE_BITS); | |
2137 | p->flags |= PAGE_WRITE; | |
2138 | prot |= p->flags; | |
2139 | ||
2140 | /* and since the content will be modified, we must invalidate | |
2141 | the corresponding translated code. */ | |
2142 | current_tb_invalidated |= tb_invalidate_phys_page(addr, pc); | |
2143 | #ifdef CONFIG_USER_ONLY | |
2144 | if (DEBUG_TB_CHECK_GATE) { | |
2145 | tb_invalidate_check(addr); | |
2146 | } | |
2147 | #endif | |
2148 | } | |
2149 | mprotect((void *)g2h(host_start), qemu_host_page_size, | |
2150 | prot & PAGE_BITS); | |
5b6dd868 | 2151 | } |
5b6dd868 | 2152 | mmap_unlock(); |
7399a337 SS |
2153 | /* If current TB was invalidated return to main loop */ |
2154 | return current_tb_invalidated ? 2 : 1; | |
5b6dd868 BS |
2155 | } |
2156 | mmap_unlock(); | |
2157 | return 0; | |
2158 | } | |
2159 | #endif /* CONFIG_USER_ONLY */ | |
2cd53943 TH |
2160 | |
2161 | /* This is a wrapper for common code that can not use CONFIG_SOFTMMU */ | |
2162 | void tcg_flush_softmmu_tlb(CPUState *cs) | |
2163 | { | |
2164 | #ifdef CONFIG_SOFTMMU | |
2165 | tlb_flush(cs); | |
2166 | #endif | |
2167 | } |