[mirror_ubuntu-artful-kernel.git] / arch / arc / include / asm / arcregs.h

/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _ASM_ARC_ARCREGS_H
#define _ASM_ARC_ARCREGS_H

/* Build Configuration Registers */
#define ARC_REG_DCCMBASE_BCR	0x61	/* DCCM Base Addr */
#define ARC_REG_CRC_BCR		0x62
#define ARC_REG_DVFB_BCR	0x64
#define ARC_REG_EXTARITH_BCR	0x65
#define ARC_REG_VECBASE_BCR	0x68
#define ARC_REG_PERIBASE_BCR	0x69
#define ARC_REG_FP_BCR		0x6B	/* Single-Precision FPU */
#define ARC_REG_DPFP_BCR	0x6C	/* Dbl Precision FPU */
#define ARC_REG_DCCM_BCR	0x74	/* DCCM Present + SZ */
#define ARC_REG_TIMERS_BCR	0x75
#define ARC_REG_ICCM_BCR	0x78
#define ARC_REG_XY_MEM_BCR	0x79
#define ARC_REG_MAC_BCR		0x7a
#define ARC_REG_MUL_BCR		0x7b
#define ARC_REG_SWAP_BCR	0x7c
#define ARC_REG_NORM_BCR	0x7d
#define ARC_REG_MIXMAX_BCR	0x7e
#define ARC_REG_BARREL_BCR	0x7f
#define ARC_REG_D_UNCACH_BCR	0x6A

/* status32 Bits Positions */
#define STATUS_AE_BIT		5	/* Exception active */
#define STATUS_DE_BIT		6	/* PC is in delay slot */
#define STATUS_U_BIT		7	/* User/Kernel mode */
#define STATUS_L_BIT		12	/* Loop inhibit */

/* These masks correspond to the status word(STATUS_32) bits */
#define STATUS_AE_MASK		(1<<STATUS_AE_BIT)
#define STATUS_DE_MASK		(1<<STATUS_DE_BIT)
#define STATUS_U_MASK		(1<<STATUS_U_BIT)
#define STATUS_L_MASK		(1<<STATUS_L_BIT)

/*
 * ECR: Exception Cause Reg bits-n-pieces
 * [23:16] = Exception Vector
 * [15: 8] = Exception Cause Code
 * [ 7: 0] = Exception Parameters (for certain types only)
 */
#define ECR_VEC_MASK			0xff0000
#define ECR_CODE_MASK			0x00ff00
#define ECR_PARAM_MASK			0x0000ff

/* Exception Cause Vector Values */
#define ECR_V_INSN_ERR			0x02
#define ECR_V_MACH_CHK			0x20
#define ECR_V_ITLB_MISS			0x21
#define ECR_V_DTLB_MISS			0x22
#define ECR_V_PROTV			0x23
#define ECR_V_TRAP			0x25

/* Protection Violation Exception Cause Code Values */
#define ECR_C_PROTV_INST_FETCH		0x00
#define ECR_C_PROTV_LOAD		0x01
#define ECR_C_PROTV_STORE		0x02
#define ECR_C_PROTV_XCHG		0x03
#define ECR_C_PROTV_MISALIG_DATA	0x04

#define ECR_C_BIT_PROTV_MISALIG_DATA	10

/* Machine Check Cause Code Values */
#define ECR_C_MCHK_DUP_TLB		0x01

/* DTLB Miss Exception Cause Code Values */
#define ECR_C_BIT_DTLB_LD_MISS		8
#define ECR_C_BIT_DTLB_ST_MISS		9

/* Dummy ECR values for Interrupts */
#define event_IRQ1		0x0031abcd
#define event_IRQ2		0x0032abcd

/* Auxiliary registers */
#define AUX_IDENTITY		4
#define AUX_INTR_VEC_BASE	0x25


/*
 * Floating Pt Registers
 * Status regs are read-only (build-time) so need not be saved/restored
 */
#define ARC_AUX_FP_STAT         0x300
#define ARC_AUX_DPFP_1L         0x301
#define ARC_AUX_DPFP_1H         0x302
#define ARC_AUX_DPFP_2L         0x303
#define ARC_AUX_DPFP_2H         0x304
#define ARC_AUX_DPFP_STAT       0x305

#ifndef __ASSEMBLY__

/*
 ******************************************************************
 *      Inline ASM macros to read/write AUX Regs
 *      Essentially invocation of lr/sr insns from "C"
 */

#if 1

#define read_aux_reg(reg)	__builtin_arc_lr(reg)

/* gcc builtin sr needs reg param to be long immediate */
#define write_aux_reg(reg_immed, val)		\
		__builtin_arc_sr((unsigned int)val, reg_immed)

#else

#define read_aux_reg(reg)		\
({					\
	unsigned int __ret;		\
	__asm__ __volatile__(		\
	"	lr    %0, [%1]"		\
	: "=r"(__ret)			\
	: "i"(reg));			\
	__ret;				\
})

/*
 * Aux Reg address is specified as long immediate by caller
 * e.g.
 *    write_aux_reg(0x69, some_val);
 * This generates tightest code.
 */
#define write_aux_reg(reg_imm, val)	\
({					\
	__asm__ __volatile__(		\
	"	sr   %0, [%1]	\n"	\
	:				\
	: "ir"(val), "i"(reg_imm));	\
})

/*
 * Aux Reg address is specified in a variable
 *  * e.g.
 *      reg_num = 0x69
 *      write_aux_reg2(reg_num, some_val);
 * This has to generate glue code to load the reg num from
 *  memory to a reg hence not recommended.
 */
#define write_aux_reg2(reg_in_var, val)		\
({						\
	unsigned int tmp;			\
						\
	__asm__ __volatile__(			\
	"	ld   %0, [%2]	\n\t"		\
	"	sr   %1, [%0]	\n\t"		\
	: "=&r"(tmp)				\
	: "r"(val), "memory"(&reg_in_var));	\
})

#endif

#define READ_BCR(reg, into)				\
{							\
	unsigned int tmp;				\
	tmp = read_aux_reg(reg);			\
	if (sizeof(tmp) == sizeof(into)) {		\
		into = *((typeof(into) *)&tmp);		\
	} else {					\
		extern void bogus_undefined(void);	\
		bogus_undefined();			\
	}						\
}

#define WRITE_BCR(reg, into)				\
{							\
	unsigned int tmp;				\
	if (sizeof(tmp) == sizeof(into)) {		\
		tmp = (*(unsigned int *)(into));	\
		write_aux_reg(reg, tmp);		\
	} else  {					\
		extern void bogus_undefined(void);	\
		bogus_undefined();			\
	}						\
}

/* Helpers */
#define TO_KB(bytes)		((bytes) >> 10)
#define TO_MB(bytes)		(TO_KB(bytes) >> 10)
#define PAGES_TO_KB(n_pages)	((n_pages) << (PAGE_SHIFT - 10))
#define PAGES_TO_MB(n_pages)	(PAGES_TO_KB(n_pages) >> 10)


/*
 ***************************************************************
 * Build Configuration Registers, with encoded hardware config
 */
struct bcr_identity {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int chip_id:16, cpu_id:8, family:8;
#else
	unsigned int family:8, cpu_id:8, chip_id:16;
#endif
};

#define EXTN_SWAP_VALID     0x1
#define EXTN_NORM_VALID     0x2
#define EXTN_MINMAX_VALID   0x2
#define EXTN_BARREL_VALID   0x2

struct bcr_extn {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:20, crc:1, ext_arith:2, mul:2, barrel:2, minmax:2,
		     norm:2, swap:1;
#else
	unsigned int swap:1, norm:2, minmax:2, barrel:2, mul:2, ext_arith:2,
		     crc:1, pad:20;
#endif
};

/* DSP Options Ref Manual */
struct bcr_extn_mac_mul {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:16, type:8, ver:8;
#else
	unsigned int ver:8, type:8, pad:16;
#endif
};

struct bcr_extn_xymem {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
#else
	unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
#endif
};

struct bcr_perip {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int start:8, pad2:8, sz:8, pad:8;
#else
	unsigned int pad:8, sz:8, pad2:8, start:8;
#endif
};
struct bcr_iccm {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int base:16, pad:5, sz:3, ver:8;
#else
	unsigned int ver:8, sz:3, pad:5, base:16;
#endif
};

/* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
struct bcr_dccm_base {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int addr:24, ver:8;
#else
	unsigned int ver:8, addr:24;
#endif
};

/* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
struct bcr_dccm {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int res:21, sz:3, ver:8;
#else
	unsigned int ver:8, sz:3, res:21;
#endif
};

/* Both SP and DP FPU BCRs have same format */
struct bcr_fp {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int fast:1, ver:8;
#else
	unsigned int ver:8, fast:1;
#endif
};

/*
 *******************************************************************
 * Generic structures to hold build configuration used at runtime
 */

struct cpuinfo_arc_mmu {
	unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb;
};

struct cpuinfo_arc_cache {
	unsigned int sz_k:8, line_len:8, assoc:4, ver:4, alias:1, vipt:1, pad:6;
};

struct cpuinfo_arc_ccm {
	unsigned int base_addr, sz;
};

struct cpuinfo_arc {
	struct cpuinfo_arc_cache icache, dcache;
	struct cpuinfo_arc_mmu mmu;
	struct bcr_identity core;
	unsigned int timers;
	unsigned int vec_base;
	unsigned int uncached_base;
	struct cpuinfo_arc_ccm iccm, dccm;
	struct bcr_extn extn;
	struct bcr_extn_xymem extn_xymem;
	struct bcr_extn_mac_mul extn_mac_mul;
	struct bcr_fp fp, dpfp;
};

extern struct cpuinfo_arc cpuinfo_arc700[];

#endif /* __ASEMBLY__ */

#endif /* _ASM_ARC_ARCREGS_H */
Commit	Line	Data
ac4c244d VG	1	/*
	2	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#ifndef _ASM_ARC_ARCREGS_H
	10	#define _ASM_ARC_ARCREGS_H
	11
bacdf480	12	/* Build Configuration Registers */
af617428 VG	13	#define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */
	14	#define ARC_REG_CRC_BCR 0x62
	15	#define ARC_REG_DVFB_BCR 0x64
	16	#define ARC_REG_EXTARITH_BCR 0x65
bacdf480	17	#define ARC_REG_VECBASE_BCR 0x68
af617428 VG	18	#define ARC_REG_PERIBASE_BCR 0x69
	19	#define ARC_REG_FP_BCR 0x6B /* Single-Precision FPU */
	20	#define ARC_REG_DPFP_BCR 0x6C /* Dbl Precision FPU */
af617428 VG	21	#define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */
	22	#define ARC_REG_TIMERS_BCR 0x75
	23	#define ARC_REG_ICCM_BCR 0x78
	24	#define ARC_REG_XY_MEM_BCR 0x79
	25	#define ARC_REG_MAC_BCR 0x7a
	26	#define ARC_REG_MUL_BCR 0x7b
	27	#define ARC_REG_SWAP_BCR 0x7c
	28	#define ARC_REG_NORM_BCR 0x7d
	29	#define ARC_REG_MIXMAX_BCR 0x7e
	30	#define ARC_REG_BARREL_BCR 0x7f
	31	#define ARC_REG_D_UNCACH_BCR 0x6A
bacdf480	32
ac4c244d	33	/* status32 Bits Positions */
ac4c244d VG	34	#define STATUS_AE_BIT 5 /* Exception active */
	35	#define STATUS_DE_BIT 6 /* PC is in delay slot */
	36	#define STATUS_U_BIT 7 /* User/Kernel mode */
	37	#define STATUS_L_BIT 12 /* Loop inhibit */
	38
	39	/* These masks correspond to the status word(STATUS_32) bits */
ac4c244d VG	40	#define STATUS_AE_MASK (1<<STATUS_AE_BIT)
	41	#define STATUS_DE_MASK (1<<STATUS_DE_BIT)
	42	#define STATUS_U_MASK (1<<STATUS_U_BIT)
	43	#define STATUS_L_MASK (1<<STATUS_L_BIT)
	44
cc562d2e VG	45	/*
	46	* ECR: Exception Cause Reg bits-n-pieces
	47	* [23:16] = Exception Vector
	48	* [15: 8] = Exception Cause Code
	49	* [ 7: 0] = Exception Parameters (for certain types only)
	50	*/
	51	#define ECR_VEC_MASK 0xff0000
	52	#define ECR_CODE_MASK 0x00ff00
	53	#define ECR_PARAM_MASK 0x0000ff
	54
	55	/* Exception Cause Vector Values */
	56	#define ECR_V_INSN_ERR 0x02
	57	#define ECR_V_MACH_CHK 0x20
	58	#define ECR_V_ITLB_MISS 0x21
	59	#define ECR_V_DTLB_MISS 0x22
	60	#define ECR_V_PROTV 0x23
502a0c77	61	#define ECR_V_TRAP 0x25
cc562d2e VG	62
	63	/* Protection Violation Exception Cause Code Values */
	64	#define ECR_C_PROTV_INST_FETCH 0x00
	65	#define ECR_C_PROTV_LOAD 0x01
	66	#define ECR_C_PROTV_STORE 0x02
	67	#define ECR_C_PROTV_XCHG 0x03
	68	#define ECR_C_PROTV_MISALIG_DATA 0x04
	69
1898a959 VG	70	#define ECR_C_BIT_PROTV_MISALIG_DATA 10
	71
	72	/* Machine Check Cause Code Values */
	73	#define ECR_C_MCHK_DUP_TLB 0x01
	74
cc562d2e VG	75	/* DTLB Miss Exception Cause Code Values */
	76	#define ECR_C_BIT_DTLB_LD_MISS 8
	77	#define ECR_C_BIT_DTLB_ST_MISS 9
	78
502a0c77 VG	79	/* Dummy ECR values for Interrupts */
	80	#define event_IRQ1 0x0031abcd
	81	#define event_IRQ2 0x0032abcd
cc562d2e	82
ac4c244d VG	83	/* Auxiliary registers */
	84	#define AUX_IDENTITY 4
	85	#define AUX_INTR_VEC_BASE 0x25
95d6976d	86
f1f3347d	87
bf90e1ea VG	88	/*
	89	* Floating Pt Registers
	90	* Status regs are read-only (build-time) so need not be saved/restored
	91	*/
	92	#define ARC_AUX_FP_STAT 0x300
	93	#define ARC_AUX_DPFP_1L 0x301
	94	#define ARC_AUX_DPFP_1H 0x302
	95	#define ARC_AUX_DPFP_2L 0x303
	96	#define ARC_AUX_DPFP_2H 0x304
	97	#define ARC_AUX_DPFP_STAT 0x305
	98
ac4c244d VG	99	#ifndef __ASSEMBLY__
	100
	101	/*
	102	******************************************************************
	103	* Inline ASM macros to read/write AUX Regs
	104	* Essentially invocation of lr/sr insns from "C"
	105	*/
	106
	107	#if 1
	108
	109	#define read_aux_reg(reg) __builtin_arc_lr(reg)
	110
	111	/* gcc builtin sr needs reg param to be long immediate */
	112	#define write_aux_reg(reg_immed, val) \
	113	__builtin_arc_sr((unsigned int)val, reg_immed)
	114
	115	#else
	116
	117	#define read_aux_reg(reg) \
	118	({ \
	119	unsigned int __ret; \
	120	__asm__ __volatile__( \
	121	" lr %0, [%1]" \
	122	: "=r"(__ret) \
	123	: "i"(reg)); \
	124	__ret; \
	125	})
	126
	127	/*
	128	* Aux Reg address is specified as long immediate by caller
	129	* e.g.
	130	* write_aux_reg(0x69, some_val);
	131	* This generates tightest code.
	132	*/
	133	#define write_aux_reg(reg_imm, val) \
	134	({ \
	135	__asm__ __volatile__( \
	136	" sr %0, [%1] \n" \
	137	: \
	138	: "ir"(val), "i"(reg_imm)); \
	139	})
	140
	141	/*
	142	* Aux Reg address is specified in a variable
	143	* * e.g.
	144	* reg_num = 0x69
	145	* write_aux_reg2(reg_num, some_val);
	146	* This has to generate glue code to load the reg num from
	147	* memory to a reg hence not recommended.
	148	*/
	149	#define write_aux_reg2(reg_in_var, val) \
	150	({ \
	151	unsigned int tmp; \
	152	\
	153	__asm__ __volatile__( \
	154	" ld %0, [%2] \n\t" \
	155	" sr %1, [%0] \n\t" \
	156	: "=&r"(tmp) \
	157	: "r"(val), "memory"(&reg_in_var)); \
	158	})
	159
	160	#endif
	161
95d6976d VG	162	#define READ_BCR(reg, into) \
	163	{ \
	164	unsigned int tmp; \
	165	tmp = read_aux_reg(reg); \
	166	if (sizeof(tmp) == sizeof(into)) { \
	167	into = ((typeof(into) )&tmp); \
	168	} else { \
	169	extern void bogus_undefined(void); \
	170	bogus_undefined(); \
	171	} \
	172	}
	173
	174	#define WRITE_BCR(reg, into) \
	175	{ \
	176	unsigned int tmp; \
	177	if (sizeof(tmp) == sizeof(into)) { \
	178	tmp = ((unsigned int )(into)); \
	179	write_aux_reg(reg, tmp); \
	180	} else { \
	181	extern void bogus_undefined(void); \
	182	bogus_undefined(); \
	183	} \
	184	}
	185
c121c506 VG	186	/* Helpers */
	187	#define TO_KB(bytes) ((bytes) >> 10)
	188	#define TO_MB(bytes) (TO_KB(bytes) >> 10)
	189	#define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
	190	#define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
95d6976d	191
bf90e1ea	192
95d6976d VG	193	/*
	194	***************************************************************
	195	* Build Configuration Registers, with encoded hardware config
	196	*/
af617428 VG	197	struct bcr_identity {
	198	#ifdef CONFIG_CPU_BIG_ENDIAN
	199	unsigned int chip_id:16, cpu_id:8, family:8;
	200	#else
	201	unsigned int family:8, cpu_id:8, chip_id:16;
	202	#endif
	203	};
95d6976d	204
af617428 VG	205	#define EXTN_SWAP_VALID 0x1
	206	#define EXTN_NORM_VALID 0x2
	207	#define EXTN_MINMAX_VALID 0x2
	208	#define EXTN_BARREL_VALID 0x2
	209
	210	struct bcr_extn {
	211	#ifdef CONFIG_CPU_BIG_ENDIAN
	212	unsigned int pad:20, crc:1, ext_arith:2, mul:2, barrel:2, minmax:2,
	213	norm:2, swap:1;
	214	#else
	215	unsigned int swap:1, norm:2, minmax:2, barrel:2, mul:2, ext_arith:2,
	216	crc:1, pad:20;
	217	#endif
	218	};
	219
	220	/* DSP Options Ref Manual */
	221	struct bcr_extn_mac_mul {
	222	#ifdef CONFIG_CPU_BIG_ENDIAN
	223	unsigned int pad:16, type:8, ver:8;
	224	#else
	225	unsigned int ver:8, type:8, pad:16;
	226	#endif
	227	};
	228
	229	struct bcr_extn_xymem {
	230	#ifdef CONFIG_CPU_BIG_ENDIAN
	231	unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
	232	#else
	233	unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
	234	#endif
	235	};
	236
af617428 VG	237	struct bcr_perip {
	238	#ifdef CONFIG_CPU_BIG_ENDIAN
	239	unsigned int start:8, pad2:8, sz:8, pad:8;
	240	#else
	241	unsigned int pad:8, sz:8, pad2:8, start:8;
	242	#endif
	243	};
	244	struct bcr_iccm {
	245	#ifdef CONFIG_CPU_BIG_ENDIAN
	246	unsigned int base:16, pad:5, sz:3, ver:8;
	247	#else
	248	unsigned int ver:8, sz:3, pad:5, base:16;
	249	#endif
	250	};
	251
	252	/* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
	253	struct bcr_dccm_base {
	254	#ifdef CONFIG_CPU_BIG_ENDIAN
	255	unsigned int addr:24, ver:8;
	256	#else
	257	unsigned int ver:8, addr:24;
	258	#endif
	259	};
	260
	261	/* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
	262	struct bcr_dccm {
	263	#ifdef CONFIG_CPU_BIG_ENDIAN
	264	unsigned int res:21, sz:3, ver:8;
	265	#else
	266	unsigned int ver:8, sz:3, res:21;
	267	#endif
	268	};
	269
	270	/* Both SP and DP FPU BCRs have same format */
	271	struct bcr_fp {
	272	#ifdef CONFIG_CPU_BIG_ENDIAN
	273	unsigned int fast:1, ver:8;
	274	#else
	275	unsigned int ver:8, fast:1;
	276	#endif
	277	};
	278
95d6976d VG	279	/*
	280	*******************************************************************
	281	* Generic structures to hold build configuration used at runtime
	282	*/
	283
cc562d2e VG	284	struct cpuinfo_arc_mmu {
	285	unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb;
	286	};
	287
95d6976d	288	struct cpuinfo_arc_cache {
da40ff48	289	unsigned int sz_k:8, line_len:8, assoc:4, ver:4, alias:1, vipt:1, pad:6;
95d6976d VG	290	};
95d6976d VG	291
af617428 VG	292	struct cpuinfo_arc_ccm {
	293	unsigned int base_addr, sz;
	294	};
	295
95d6976d VG	296	struct cpuinfo_arc {
95d6976d VG	297	struct cpuinfo_arc_cache icache, dcache;
cc562d2e	298	struct cpuinfo_arc_mmu mmu;
af617428 VG	299	struct bcr_identity core;
	300	unsigned int timers;
	301	unsigned int vec_base;
	302	unsigned int uncached_base;
	303	struct cpuinfo_arc_ccm iccm, dccm;
	304	struct bcr_extn extn;
	305	struct bcr_extn_xymem extn_xymem;
	306	struct bcr_extn_mac_mul extn_mac_mul;
	307	struct bcr_fp fp, dpfp;
95d6976d VG	308	};
	309
	310	extern struct cpuinfo_arc cpuinfo_arc700[];
	311
ac4c244d VG	312	#endif /* __ASEMBLY__ */
ac4c244d VG	313
ac4c244d	314	#endif /* _ASM_ARC_ARCREGS_H */