[mirror_ubuntu-zesty-kernel.git] / arch / arc / include / asm / perf_event.h

/*
 * Linux performance counter support for ARC
 *
 * Copyright (C) 2014-2015 Synopsys, Inc. (www.synopsys.com)
 * Copyright (C) 2011-2013 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef __ASM_PERF_EVENT_H
#define __ASM_PERF_EVENT_H

/* Max number of counters that PCT block may ever have */
#define ARC_PERF_MAX_COUNTERS	32

#define ARC_REG_CC_BUILD	0xF6
#define ARC_REG_CC_INDEX	0x240
#define ARC_REG_CC_NAME0	0x241
#define ARC_REG_CC_NAME1	0x242

#define ARC_REG_PCT_BUILD	0xF5
#define ARC_REG_PCT_COUNTL	0x250
#define ARC_REG_PCT_COUNTH	0x251
#define ARC_REG_PCT_SNAPL	0x252
#define ARC_REG_PCT_SNAPH	0x253
#define ARC_REG_PCT_CONFIG	0x254
#define ARC_REG_PCT_CONTROL	0x255
#define ARC_REG_PCT_INDEX	0x256
#define ARC_REG_PCT_INT_CNTL	0x25C
#define ARC_REG_PCT_INT_CNTH	0x25D
#define ARC_REG_PCT_INT_CTRL	0x25E
#define ARC_REG_PCT_INT_ACT	0x25F

#define ARC_REG_PCT_CONTROL_CC	(1 << 16)	/* clear counts */
#define ARC_REG_PCT_CONTROL_SN	(1 << 17)	/* snapshot */

struct arc_reg_pct_build {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int m:8, c:8, r:5, i:1, s:2, v:8;
#else
	unsigned int v:8, s:2, i:1, r:5, c:8, m:8;
#endif
};

struct arc_reg_cc_build {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int c:16, r:8, v:8;
#else
	unsigned int v:8, r:8, c:16;
#endif
};

#define PERF_COUNT_ARC_DCLM	(PERF_COUNT_HW_MAX + 0)
#define PERF_COUNT_ARC_DCSM	(PERF_COUNT_HW_MAX + 1)
#define PERF_COUNT_ARC_ICM	(PERF_COUNT_HW_MAX + 2)
#define PERF_COUNT_ARC_BPOK	(PERF_COUNT_HW_MAX + 3)
#define PERF_COUNT_ARC_EDTLB	(PERF_COUNT_HW_MAX + 4)
#define PERF_COUNT_ARC_EITLB	(PERF_COUNT_HW_MAX + 5)
#define PERF_COUNT_ARC_LDC	(PERF_COUNT_HW_MAX + 6)
#define PERF_COUNT_ARC_STC	(PERF_COUNT_HW_MAX + 7)

#define PERF_COUNT_ARC_HW_MAX	(PERF_COUNT_HW_MAX + 8)

/*
 * Some ARC pct quirks:
 *
 * PERF_COUNT_HW_STALLED_CYCLES_BACKEND
 * PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
 *	The ARC 700 can either measure stalls per pipeline stage, or all stalls
 *	combined; for now we assign all stalls to STALLED_CYCLES_BACKEND
 *	and all pipeline flushes (e.g. caused by mispredicts, etc.) to
 *	STALLED_CYCLES_FRONTEND.
 *
 *	We could start multiple performance counters and combine everything
 *	afterwards, but that makes it complicated.
 *
 *	Note that I$ cache misses aren't counted by either of the two!
 */

/*
 * ARC PCT has hardware conditions with fixed "names" but variable "indexes"
 * (based on a specific RTL build)
 * Below is the static map between perf generic/arc specific event_id and
 * h/w condition names.
 * At the time of probe, we loop thru each index and find it's name to
 * complete the mapping of perf event_id to h/w index as latter is needed
 * to program the counter really
 */
static const char * const arc_pmu_ev_hw_map[] = {
	/* count cycles */
	[PERF_COUNT_HW_CPU_CYCLES] = "crun",
	[PERF_COUNT_HW_REF_CPU_CYCLES] = "crun",
	[PERF_COUNT_HW_BUS_CYCLES] = "crun",

	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush",
	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",

	/* counts condition */
	[PERF_COUNT_HW_INSTRUCTIONS] = "iall",
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp", /* Excludes ZOL jumps */
	[PERF_COUNT_ARC_BPOK]         = "bpok",	  /* NP-NT, PT-T, PNT-NT */
	[PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */

	[PERF_COUNT_ARC_LDC] = "imemrdc",	/* Instr: mem read cached */
	[PERF_COUNT_ARC_STC] = "imemwrc",	/* Instr: mem write cached */

	[PERF_COUNT_ARC_DCLM] = "dclm",		/* D-cache Load Miss */
	[PERF_COUNT_ARC_DCSM] = "dcsm",		/* D-cache Store Miss */
	[PERF_COUNT_ARC_ICM] = "icm",		/* I-cache Miss */
	[PERF_COUNT_ARC_EDTLB] = "edtlb",	/* D-TLB Miss */
	[PERF_COUNT_ARC_EITLB] = "eitlb",	/* I-TLB Miss */
};

#define C(_x)			PERF_COUNT_HW_CACHE_##_x
#define CACHE_OP_UNSUPPORTED	0xffff

static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
	[C(L1D)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= PERF_COUNT_ARC_LDC,
			[C(RESULT_MISS)]	= PERF_COUNT_ARC_DCLM,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= PERF_COUNT_ARC_STC,
			[C(RESULT_MISS)]	= PERF_COUNT_ARC_DCSM,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(L1I)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= PERF_COUNT_HW_INSTRUCTIONS,
			[C(RESULT_MISS)]	= PERF_COUNT_ARC_ICM,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(LL)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(DTLB)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= PERF_COUNT_ARC_LDC,
			[C(RESULT_MISS)]	= PERF_COUNT_ARC_EDTLB,
		},
			/* DTLB LD/ST Miss not segregated by h/w*/
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(ITLB)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= PERF_COUNT_ARC_EITLB,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(BPU)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
			[C(RESULT_MISS)]	= PERF_COUNT_HW_BRANCH_MISSES,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(NODE)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
};

#endif /* __ASM_PERF_EVENT_H */
Commit	Line	Data
9c57564e	1	/*
0dd450fe MJ	2	* Linux performance counter support for ARC
0dd450fe MJ	3	*
fb7c5725	4	* Copyright (C) 2014-2015 Synopsys, Inc. (www.synopsys.com)
0dd450fe	5	* Copyright (C) 2011-2013 Synopsys, Inc. (www.synopsys.com)
9c57564e VG	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	*/
	12
	13	#ifndef __ASM_PERF_EVENT_H
	14	#define __ASM_PERF_EVENT_H
	15
fb7c5725 VG	16	/* Max number of counters that PCT block may ever have */
fb7c5725 VG	17	#define ARC_PERF_MAX_COUNTERS 32
0dd450fe MJ	18
	19	#define ARC_REG_CC_BUILD 0xF6
	20	#define ARC_REG_CC_INDEX 0x240
	21	#define ARC_REG_CC_NAME0 0x241
	22	#define ARC_REG_CC_NAME1 0x242
	23
	24	#define ARC_REG_PCT_BUILD 0xF5
	25	#define ARC_REG_PCT_COUNTL 0x250
	26	#define ARC_REG_PCT_COUNTH 0x251
	27	#define ARC_REG_PCT_SNAPL 0x252
	28	#define ARC_REG_PCT_SNAPH 0x253
	29	#define ARC_REG_PCT_CONFIG 0x254
	30	#define ARC_REG_PCT_CONTROL 0x255
	31	#define ARC_REG_PCT_INDEX 0x256
36481cf7 AB	32	#define ARC_REG_PCT_INT_CNTL 0x25C
	33	#define ARC_REG_PCT_INT_CNTH 0x25D
	34	#define ARC_REG_PCT_INT_CTRL 0x25E
	35	#define ARC_REG_PCT_INT_ACT 0x25F
0dd450fe MJ	36
	37	#define ARC_REG_PCT_CONTROL_CC (1 << 16) /* clear counts */
	38	#define ARC_REG_PCT_CONTROL_SN (1 << 17) /* snapshot */
	39
	40	struct arc_reg_pct_build {
	41	#ifdef CONFIG_CPU_BIG_ENDIAN
36481cf7	42	unsigned int m:8, c:8, r:5, i:1, s:2, v:8;
0dd450fe	43	#else
36481cf7	44	unsigned int v:8, s:2, i:1, r:5, c:8, m:8;
0dd450fe MJ	45	#endif
	46	};
	47
	48	struct arc_reg_cc_build {
	49	#ifdef CONFIG_CPU_BIG_ENDIAN
	50	unsigned int c:16, r:8, v:8;
	51	#else
	52	unsigned int v:8, r:8, c:16;
	53	#endif
	54	};
	55
	56	#define PERF_COUNT_ARC_DCLM (PERF_COUNT_HW_MAX + 0)
	57	#define PERF_COUNT_ARC_DCSM (PERF_COUNT_HW_MAX + 1)
	58	#define PERF_COUNT_ARC_ICM (PERF_COUNT_HW_MAX + 2)
	59	#define PERF_COUNT_ARC_BPOK (PERF_COUNT_HW_MAX + 3)
	60	#define PERF_COUNT_ARC_EDTLB (PERF_COUNT_HW_MAX + 4)
	61	#define PERF_COUNT_ARC_EITLB (PERF_COUNT_HW_MAX + 5)
0a8a4767 VG	62	#define PERF_COUNT_ARC_LDC (PERF_COUNT_HW_MAX + 6)
	63	#define PERF_COUNT_ARC_STC (PERF_COUNT_HW_MAX + 7)
	64
	65	#define PERF_COUNT_ARC_HW_MAX (PERF_COUNT_HW_MAX + 8)
0dd450fe MJ	66
0dd450fe MJ	67	/*
bde80c23	68	* Some ARC pct quirks:
0dd450fe MJ	69	*
	70	* PERF_COUNT_HW_STALLED_CYCLES_BACKEND
	71	* PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
	72	* The ARC 700 can either measure stalls per pipeline stage, or all stalls
	73	* combined; for now we assign all stalls to STALLED_CYCLES_BACKEND
	74	* and all pipeline flushes (e.g. caused by mispredicts, etc.) to
	75	* STALLED_CYCLES_FRONTEND.
	76	*
	77	* We could start multiple performance counters and combine everything
	78	* afterwards, but that makes it complicated.
	79	*
	80	* Note that I$ cache misses aren't counted by either of the two!
	81	*/
	82
bde80c23 VG	83	/*
	84	* ARC PCT has hardware conditions with fixed "names" but variable "indexes"
	85	* (based on a specific RTL build)
	86	* Below is the static map between perf generic/arc specific event_id and
	87	* h/w condition names.
	88	* At the time of probe, we loop thru each index and find it's name to
	89	* complete the mapping of perf event_id to h/w index as latter is needed
	90	* to program the counter really
	91	*/
0dd450fe	92	static const char * const arc_pmu_ev_hw_map[] = {
bde80c23	93	/* count cycles */
0dd450fe MJ	94	[PERF_COUNT_HW_CPU_CYCLES] = "crun",
	95	[PERF_COUNT_HW_REF_CPU_CYCLES] = "crun",
	96	[PERF_COUNT_HW_BUS_CYCLES] = "crun",
bde80c23	97
0dd450fe MJ	98	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush",
0dd450fe MJ	99	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",
bde80c23 VG	100
	101	/* counts condition */
	102	[PERF_COUNT_HW_INSTRUCTIONS] = "iall",
09074950	103	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmp", /* Excludes ZOL jumps */
bde80c23 VG	104	[PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */
	105	[PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */
	106
0a8a4767 VG	107	[PERF_COUNT_ARC_LDC] = "imemrdc", /* Instr: mem read cached */
	108	[PERF_COUNT_ARC_STC] = "imemwrc", /* Instr: mem write cached */
	109
bde80c23 VG	110	[PERF_COUNT_ARC_DCLM] = "dclm", /* D-cache Load Miss */
	111	[PERF_COUNT_ARC_DCSM] = "dcsm", /* D-cache Store Miss */
	112	[PERF_COUNT_ARC_ICM] = "icm", /* I-cache Miss */
	113	[PERF_COUNT_ARC_EDTLB] = "edtlb", /* D-TLB Miss */
	114	[PERF_COUNT_ARC_EITLB] = "eitlb", /* I-TLB Miss */
0dd450fe MJ	115	};
	116
	117	#define C(_x) PERF_COUNT_HW_CACHE_##_x
	118	#define CACHE_OP_UNSUPPORTED 0xffff
	119
	120	static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
	121	[C(L1D)] = {
	122	[C(OP_READ)] = {
0a8a4767	123	[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
0dd450fe MJ	124	[C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
	125	},
	126	[C(OP_WRITE)] = {
0a8a4767	127	[C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
0dd450fe MJ	128	[C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
	129	},
	130	[C(OP_PREFETCH)] = {
	131	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	132	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	133	},
	134	},
	135	[C(L1I)] = {
	136	[C(OP_READ)] = {
0a8a4767	137	[C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS,
0dd450fe MJ	138	[C(RESULT_MISS)] = PERF_COUNT_ARC_ICM,
	139	},
	140	[C(OP_WRITE)] = {
	141	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	142	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	143	},
	144	[C(OP_PREFETCH)] = {
	145	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	146	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	147	},
	148	},
	149	[C(LL)] = {
	150	[C(OP_READ)] = {
	151	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	152	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	153	},
	154	[C(OP_WRITE)] = {
	155	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	156	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	157	},
	158	[C(OP_PREFETCH)] = {
	159	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	160	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	161	},
	162	},
	163	[C(DTLB)] = {
	164	[C(OP_READ)] = {
0a8a4767	165	[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
0dd450fe MJ	166	[C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB,
0dd450fe MJ	167	},
0a8a4767	168	/* DTLB LD/ST Miss not segregated by h/w*/
0dd450fe MJ	169	[C(OP_WRITE)] = {
	170	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	171	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	172	},
	173	[C(OP_PREFETCH)] = {
	174	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	175	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	176	},
	177	},
	178	[C(ITLB)] = {
	179	[C(OP_READ)] = {
	180	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	181	[C(RESULT_MISS)] = PERF_COUNT_ARC_EITLB,
	182	},
	183	[C(OP_WRITE)] = {
	184	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	185	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	186	},
	187	[C(OP_PREFETCH)] = {
	188	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	189	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	190	},
	191	},
	192	[C(BPU)] = {
	193	[C(OP_READ)] = {
	194	[C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
	195	[C(RESULT_MISS)] = PERF_COUNT_HW_BRANCH_MISSES,
	196	},
	197	[C(OP_WRITE)] = {
	198	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	199	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	200	},
	201	[C(OP_PREFETCH)] = {
	202	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	203	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	204	},
	205	},
	206	[C(NODE)] = {
	207	[C(OP_READ)] = {
	208	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	209	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	210	},
	211	[C(OP_WRITE)] = {
	212	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	213	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	214	},
	215	[C(OP_PREFETCH)] = {
	216	[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
	217	[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
	218	},
	219	},
	220	};
	221
9c57564e	222	#endif /* __ASM_PERF_EVENT_H */