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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/boot/compressed/head.S | |
3 | * | |
4 | * Copyright (C) 1996-2002 Russell King | |
10c2df65 | 5 | * Copyright (C) 2004 Hyok S. Choi (MPU support) |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/linkage.h> |
12 | ||
13 | /* | |
14 | * Debugging stuff | |
15 | * | |
16 | * Note that these macros must not contain any code which is not | |
17 | * 100% relocatable. Any attempt to do so will result in a crash. | |
18 | * Please select one of the following when turning on debugging. | |
19 | */ | |
20 | #ifdef DEBUG | |
5cd0c344 | 21 | |
5cd0c344 | 22 | #if defined(CONFIG_DEBUG_ICEDCC) |
7d95ded9 | 23 | |
dfad549d | 24 | #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) |
4e6d488a | 25 | .macro loadsp, rb, tmp |
7d95ded9 TL |
26 | .endm |
27 | .macro writeb, ch, rb | |
28 | mcr p14, 0, \ch, c0, c5, 0 | |
29 | .endm | |
c633c3cf | 30 | #elif defined(CONFIG_CPU_XSCALE) |
4e6d488a | 31 | .macro loadsp, rb, tmp |
c633c3cf JCPV |
32 | .endm |
33 | .macro writeb, ch, rb | |
34 | mcr p14, 0, \ch, c8, c0, 0 | |
35 | .endm | |
7d95ded9 | 36 | #else |
4e6d488a | 37 | .macro loadsp, rb, tmp |
1da177e4 | 38 | .endm |
224b5be6 | 39 | .macro writeb, ch, rb |
41a9e680 | 40 | mcr p14, 0, \ch, c1, c0, 0 |
1da177e4 | 41 | .endm |
7d95ded9 TL |
42 | #endif |
43 | ||
5cd0c344 | 44 | #else |
224b5be6 | 45 | |
a09e64fb | 46 | #include <mach/debug-macro.S> |
224b5be6 | 47 | |
5cd0c344 RK |
48 | .macro writeb, ch, rb |
49 | senduart \ch, \rb | |
1da177e4 | 50 | .endm |
5cd0c344 | 51 | |
224b5be6 | 52 | #if defined(CONFIG_ARCH_SA1100) |
4e6d488a | 53 | .macro loadsp, rb, tmp |
1da177e4 | 54 | mov \rb, #0x80000000 @ physical base address |
224b5be6 | 55 | #ifdef CONFIG_DEBUG_LL_SER3 |
1da177e4 | 56 | add \rb, \rb, #0x00050000 @ Ser3 |
224b5be6 | 57 | #else |
1da177e4 | 58 | add \rb, \rb, #0x00010000 @ Ser1 |
224b5be6 | 59 | #endif |
1da177e4 | 60 | .endm |
1da177e4 | 61 | #elif defined(CONFIG_ARCH_S3C2410) |
4e6d488a | 62 | .macro loadsp, rb, tmp |
1da177e4 | 63 | mov \rb, #0x50000000 |
c7657846 | 64 | add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT |
1da177e4 | 65 | .endm |
1da177e4 | 66 | #else |
4e6d488a TL |
67 | .macro loadsp, rb, tmp |
68 | addruart \rb, \tmp | |
224b5be6 | 69 | .endm |
1da177e4 | 70 | #endif |
5cd0c344 | 71 | #endif |
1da177e4 LT |
72 | #endif |
73 | ||
74 | .macro kputc,val | |
75 | mov r0, \val | |
76 | bl putc | |
77 | .endm | |
78 | ||
79 | .macro kphex,val,len | |
80 | mov r0, \val | |
81 | mov r1, #\len | |
82 | bl phex | |
83 | .endm | |
84 | ||
85 | .macro debug_reloc_start | |
86 | #ifdef DEBUG | |
87 | kputc #'\n' | |
88 | kphex r6, 8 /* processor id */ | |
89 | kputc #':' | |
90 | kphex r7, 8 /* architecture id */ | |
f12d0d7c | 91 | #ifdef CONFIG_CPU_CP15 |
1da177e4 LT |
92 | kputc #':' |
93 | mrc p15, 0, r0, c1, c0 | |
94 | kphex r0, 8 /* control reg */ | |
f12d0d7c | 95 | #endif |
1da177e4 LT |
96 | kputc #'\n' |
97 | kphex r5, 8 /* decompressed kernel start */ | |
98 | kputc #'-' | |
f4619025 | 99 | kphex r9, 8 /* decompressed kernel end */ |
1da177e4 LT |
100 | kputc #'>' |
101 | kphex r4, 8 /* kernel execution address */ | |
102 | kputc #'\n' | |
103 | #endif | |
104 | .endm | |
105 | ||
106 | .macro debug_reloc_end | |
107 | #ifdef DEBUG | |
108 | kphex r5, 8 /* end of kernel */ | |
109 | kputc #'\n' | |
110 | mov r0, r4 | |
111 | bl memdump /* dump 256 bytes at start of kernel */ | |
112 | #endif | |
113 | .endm | |
114 | ||
115 | .section ".start", #alloc, #execinstr | |
116 | /* | |
117 | * sort out different calling conventions | |
118 | */ | |
119 | .align | |
26e5ca93 | 120 | .arm @ Always enter in ARM state |
1da177e4 LT |
121 | start: |
122 | .type start,#function | |
b11fe388 | 123 | .rept 7 |
1da177e4 LT |
124 | mov r0, r0 |
125 | .endr | |
b11fe388 NP |
126 | ARM( mov r0, r0 ) |
127 | ARM( b 1f ) | |
128 | THUMB( adr r12, BSYM(1f) ) | |
129 | THUMB( bx r12 ) | |
1da177e4 | 130 | |
1da177e4 LT |
131 | .word 0x016f2818 @ Magic numbers to help the loader |
132 | .word start @ absolute load/run zImage address | |
133 | .word _edata @ zImage end address | |
26e5ca93 | 134 | THUMB( .thumb ) |
1da177e4 | 135 | 1: mov r7, r1 @ save architecture ID |
f4619025 | 136 | mov r8, r2 @ save atags pointer |
1da177e4 LT |
137 | |
138 | #ifndef __ARM_ARCH_2__ | |
139 | /* | |
140 | * Booting from Angel - need to enter SVC mode and disable | |
141 | * FIQs/IRQs (numeric definitions from angel arm.h source). | |
142 | * We only do this if we were in user mode on entry. | |
143 | */ | |
144 | mrs r2, cpsr @ get current mode | |
145 | tst r2, #3 @ not user? | |
146 | bne not_angel | |
147 | mov r0, #0x17 @ angel_SWIreason_EnterSVC | |
0e056f20 CM |
148 | ARM( swi 0x123456 ) @ angel_SWI_ARM |
149 | THUMB( svc 0xab ) @ angel_SWI_THUMB | |
1da177e4 LT |
150 | not_angel: |
151 | mrs r2, cpsr @ turn off interrupts to | |
152 | orr r2, r2, #0xc0 @ prevent angel from running | |
153 | msr cpsr_c, r2 | |
154 | #else | |
155 | teqp pc, #0x0c000003 @ turn off interrupts | |
156 | #endif | |
157 | ||
158 | /* | |
159 | * Note that some cache flushing and other stuff may | |
160 | * be needed here - is there an Angel SWI call for this? | |
161 | */ | |
162 | ||
163 | /* | |
164 | * some architecture specific code can be inserted | |
f4619025 | 165 | * by the linker here, but it should preserve r7, r8, and r9. |
1da177e4 LT |
166 | */ |
167 | ||
168 | .text | |
6d7d0ae5 | 169 | |
e69edc79 EM |
170 | #ifdef CONFIG_AUTO_ZRELADDR |
171 | @ determine final kernel image address | |
bfa64c4a DM |
172 | mov r4, pc |
173 | and r4, r4, #0xf8000000 | |
e69edc79 EM |
174 | add r4, r4, #TEXT_OFFSET |
175 | #else | |
9e84ed63 | 176 | ldr r4, =zreladdr |
e69edc79 | 177 | #endif |
1da177e4 | 178 | |
6d7d0ae5 NP |
179 | bl cache_on |
180 | ||
181 | restart: adr r0, LC0 | |
34cc1a8f | 182 | ldmia r0, {r1, r2, r3, r6, r10, r11, r12} |
adcc2591 | 183 | ldr sp, [r0, #28] |
6d7d0ae5 NP |
184 | |
185 | /* | |
186 | * We might be running at a different address. We need | |
187 | * to fix up various pointers. | |
188 | */ | |
189 | sub r0, r0, r1 @ calculate the delta offset | |
6d7d0ae5 | 190 | add r6, r6, r0 @ _edata |
34cc1a8f NP |
191 | add r10, r10, r0 @ inflated kernel size location |
192 | ||
193 | /* | |
194 | * The kernel build system appends the size of the | |
195 | * decompressed kernel at the end of the compressed data | |
196 | * in little-endian form. | |
197 | */ | |
198 | ldrb r9, [r10, #0] | |
199 | ldrb lr, [r10, #1] | |
200 | orr r9, r9, lr, lsl #8 | |
201 | ldrb lr, [r10, #2] | |
202 | ldrb r10, [r10, #3] | |
203 | orr r9, r9, lr, lsl #16 | |
204 | orr r9, r9, r10, lsl #24 | |
1da177e4 | 205 | |
6d7d0ae5 NP |
206 | #ifndef CONFIG_ZBOOT_ROM |
207 | /* malloc space is above the relocated stack (64k max) */ | |
208 | add sp, sp, r0 | |
209 | add r10, sp, #0x10000 | |
210 | #else | |
1da177e4 | 211 | /* |
6d7d0ae5 NP |
212 | * With ZBOOT_ROM the bss/stack is non relocatable, |
213 | * but someone could still run this code from RAM, | |
214 | * in which case our reference is _edata. | |
1da177e4 | 215 | */ |
6d7d0ae5 NP |
216 | mov r10, r6 |
217 | #endif | |
218 | ||
e2a6a3aa JB |
219 | mov r5, #0 @ init dtb size to 0 |
220 | #ifdef CONFIG_ARM_APPENDED_DTB | |
221 | /* | |
222 | * r0 = delta | |
223 | * r2 = BSS start | |
224 | * r3 = BSS end | |
225 | * r4 = final kernel address | |
226 | * r5 = appended dtb size (still unknown) | |
227 | * r6 = _edata | |
228 | * r7 = architecture ID | |
229 | * r8 = atags/device tree pointer | |
230 | * r9 = size of decompressed image | |
231 | * r10 = end of this image, including bss/stack/malloc space if non XIP | |
232 | * r11 = GOT start | |
233 | * r12 = GOT end | |
234 | * sp = stack pointer | |
235 | * | |
236 | * if there are device trees (dtb) appended to zImage, advance r10 so that the | |
237 | * dtb data will get relocated along with the kernel if necessary. | |
238 | */ | |
239 | ||
240 | ldr lr, [r6, #0] | |
241 | #ifndef __ARMEB__ | |
242 | ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian | |
243 | #else | |
244 | ldr r1, =0xd00dfeed | |
245 | #endif | |
246 | cmp lr, r1 | |
247 | bne dtb_check_done @ not found | |
248 | ||
249 | mov r8, r6 @ use the appended device tree | |
250 | ||
251 | /* Get the dtb's size */ | |
252 | ldr r5, [r6, #4] | |
253 | #ifndef __ARMEB__ | |
254 | /* convert r5 (dtb size) to little endian */ | |
255 | eor r1, r5, r5, ror #16 | |
256 | bic r1, r1, #0x00ff0000 | |
257 | mov r5, r5, ror #8 | |
258 | eor r5, r5, r1, lsr #8 | |
259 | #endif | |
260 | ||
261 | /* preserve 64-bit alignment */ | |
262 | add r5, r5, #7 | |
263 | bic r5, r5, #7 | |
264 | ||
265 | /* relocate some pointers past the appended dtb */ | |
266 | add r6, r6, r5 | |
267 | add r10, r10, r5 | |
268 | add sp, sp, r5 | |
269 | dtb_check_done: | |
270 | #endif | |
271 | ||
6d7d0ae5 NP |
272 | /* |
273 | * Check to see if we will overwrite ourselves. | |
274 | * r4 = final kernel address | |
6d7d0ae5 NP |
275 | * r9 = size of decompressed image |
276 | * r10 = end of this image, including bss/stack/malloc space if non XIP | |
277 | * We basically want: | |
ea9df3b1 | 278 | * r4 - 16k page directory >= r10 -> OK |
adcc2591 | 279 | * r4 + image length <= current position (pc) -> OK |
6d7d0ae5 | 280 | */ |
ea9df3b1 | 281 | add r10, r10, #16384 |
6d7d0ae5 NP |
282 | cmp r4, r10 |
283 | bhs wont_overwrite | |
284 | add r10, r4, r9 | |
adcc2591 NP |
285 | ARM( cmp r10, pc ) |
286 | THUMB( mov lr, pc ) | |
287 | THUMB( cmp r10, lr ) | |
6d7d0ae5 NP |
288 | bls wont_overwrite |
289 | ||
290 | /* | |
291 | * Relocate ourselves past the end of the decompressed kernel. | |
6d7d0ae5 NP |
292 | * r6 = _edata |
293 | * r10 = end of the decompressed kernel | |
294 | * Because we always copy ahead, we need to do it from the end and go | |
295 | * backward in case the source and destination overlap. | |
296 | */ | |
adcc2591 NP |
297 | /* |
298 | * Bump to the next 256-byte boundary with the size of | |
299 | * the relocation code added. This avoids overwriting | |
300 | * ourself when the offset is small. | |
301 | */ | |
302 | add r10, r10, #((reloc_code_end - restart + 256) & ~255) | |
6d7d0ae5 NP |
303 | bic r10, r10, #255 |
304 | ||
adcc2591 NP |
305 | /* Get start of code we want to copy and align it down. */ |
306 | adr r5, restart | |
307 | bic r5, r5, #31 | |
308 | ||
6d7d0ae5 NP |
309 | sub r9, r6, r5 @ size to copy |
310 | add r9, r9, #31 @ rounded up to a multiple | |
311 | bic r9, r9, #31 @ ... of 32 bytes | |
312 | add r6, r9, r5 | |
313 | add r9, r9, r10 | |
314 | ||
315 | 1: ldmdb r6!, {r0 - r3, r10 - r12, lr} | |
316 | cmp r6, r5 | |
317 | stmdb r9!, {r0 - r3, r10 - r12, lr} | |
318 | bhi 1b | |
319 | ||
320 | /* Preserve offset to relocated code. */ | |
321 | sub r6, r9, r6 | |
322 | ||
7c2527f0 TL |
323 | #ifndef CONFIG_ZBOOT_ROM |
324 | /* cache_clean_flush may use the stack, so relocate it */ | |
325 | add sp, sp, r6 | |
326 | #endif | |
327 | ||
6d7d0ae5 NP |
328 | bl cache_clean_flush |
329 | ||
330 | adr r0, BSYM(restart) | |
331 | add r0, r0, r6 | |
332 | mov pc, r0 | |
333 | ||
334 | wont_overwrite: | |
335 | /* | |
336 | * If delta is zero, we are running at the address we were linked at. | |
337 | * r0 = delta | |
338 | * r2 = BSS start | |
339 | * r3 = BSS end | |
340 | * r4 = kernel execution address | |
e2a6a3aa | 341 | * r5 = appended dtb size (0 if not present) |
6d7d0ae5 NP |
342 | * r7 = architecture ID |
343 | * r8 = atags pointer | |
344 | * r11 = GOT start | |
345 | * r12 = GOT end | |
346 | * sp = stack pointer | |
347 | */ | |
e2a6a3aa | 348 | orrs r1, r0, r5 |
6d7d0ae5 | 349 | beq not_relocated |
e2a6a3aa | 350 | |
98e12b5a | 351 | add r11, r11, r0 |
6d7d0ae5 | 352 | add r12, r12, r0 |
1da177e4 LT |
353 | |
354 | #ifndef CONFIG_ZBOOT_ROM | |
355 | /* | |
356 | * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, | |
357 | * we need to fix up pointers into the BSS region. | |
6d7d0ae5 | 358 | * Note that the stack pointer has already been fixed up. |
1da177e4 LT |
359 | */ |
360 | add r2, r2, r0 | |
361 | add r3, r3, r0 | |
1da177e4 LT |
362 | |
363 | /* | |
364 | * Relocate all entries in the GOT table. | |
e2a6a3aa | 365 | * Bump bss entries to _edata + dtb size |
1da177e4 | 366 | */ |
98e12b5a | 367 | 1: ldr r1, [r11, #0] @ relocate entries in the GOT |
e2a6a3aa JB |
368 | add r1, r1, r0 @ This fixes up C references |
369 | cmp r1, r2 @ if entry >= bss_start && | |
370 | cmphs r3, r1 @ bss_end > entry | |
371 | addhi r1, r1, r5 @ entry += dtb size | |
372 | str r1, [r11], #4 @ next entry | |
6d7d0ae5 | 373 | cmp r11, r12 |
1da177e4 | 374 | blo 1b |
e2a6a3aa JB |
375 | |
376 | /* bump our bss pointers too */ | |
377 | add r2, r2, r5 | |
378 | add r3, r3, r5 | |
379 | ||
1da177e4 LT |
380 | #else |
381 | ||
382 | /* | |
383 | * Relocate entries in the GOT table. We only relocate | |
384 | * the entries that are outside the (relocated) BSS region. | |
385 | */ | |
98e12b5a | 386 | 1: ldr r1, [r11, #0] @ relocate entries in the GOT |
1da177e4 LT |
387 | cmp r1, r2 @ entry < bss_start || |
388 | cmphs r3, r1 @ _end < entry | |
389 | addlo r1, r1, r0 @ table. This fixes up the | |
98e12b5a | 390 | str r1, [r11], #4 @ C references. |
6d7d0ae5 | 391 | cmp r11, r12 |
1da177e4 LT |
392 | blo 1b |
393 | #endif | |
394 | ||
395 | not_relocated: mov r0, #0 | |
396 | 1: str r0, [r2], #4 @ clear bss | |
397 | str r0, [r2], #4 | |
398 | str r0, [r2], #4 | |
399 | str r0, [r2], #4 | |
400 | cmp r2, r3 | |
401 | blo 1b | |
402 | ||
1da177e4 | 403 | /* |
6d7d0ae5 NP |
404 | * The C runtime environment should now be setup sufficiently. |
405 | * Set up some pointers, and start decompressing. | |
406 | * r4 = kernel execution address | |
407 | * r7 = architecture ID | |
408 | * r8 = atags pointer | |
1da177e4 | 409 | */ |
6d7d0ae5 NP |
410 | mov r0, r4 |
411 | mov r1, sp @ malloc space above stack | |
412 | add r2, sp, #0x10000 @ 64k max | |
1da177e4 LT |
413 | mov r3, r7 |
414 | bl decompress_kernel | |
1da177e4 | 415 | bl cache_clean_flush |
6d7d0ae5 NP |
416 | bl cache_off |
417 | mov r0, #0 @ must be zero | |
418 | mov r1, r7 @ restore architecture number | |
419 | mov r2, r8 @ restore atags pointer | |
540b5738 DM |
420 | ARM( mov pc, r4 ) @ call kernel |
421 | THUMB( bx r4 ) @ entry point is always ARM | |
1da177e4 | 422 | |
88987ef9 | 423 | .align 2 |
1da177e4 LT |
424 | .type LC0, #object |
425 | LC0: .word LC0 @ r1 | |
426 | .word __bss_start @ r2 | |
427 | .word _end @ r3 | |
6d7d0ae5 | 428 | .word _edata @ r6 |
34cc1a8f | 429 | .word input_data_end - 4 @ r10 (inflated size location) |
98e12b5a | 430 | .word _got_start @ r11 |
1da177e4 | 431 | .word _got_end @ ip |
8d7e4cc2 | 432 | .word .L_user_stack_end @ sp |
1da177e4 LT |
433 | .size LC0, . - LC0 |
434 | ||
435 | #ifdef CONFIG_ARCH_RPC | |
436 | .globl params | |
db7b2b4b | 437 | params: ldr r0, =0x10000100 @ params_phys for RPC |
1da177e4 LT |
438 | mov pc, lr |
439 | .ltorg | |
440 | .align | |
441 | #endif | |
442 | ||
443 | /* | |
444 | * Turn on the cache. We need to setup some page tables so that we | |
445 | * can have both the I and D caches on. | |
446 | * | |
447 | * We place the page tables 16k down from the kernel execution address, | |
448 | * and we hope that nothing else is using it. If we're using it, we | |
449 | * will go pop! | |
450 | * | |
451 | * On entry, | |
452 | * r4 = kernel execution address | |
1da177e4 | 453 | * r7 = architecture number |
f4619025 | 454 | * r8 = atags pointer |
1da177e4 | 455 | * On exit, |
21b2841d | 456 | * r0, r1, r2, r3, r9, r10, r12 corrupted |
1da177e4 | 457 | * This routine must preserve: |
6d7d0ae5 | 458 | * r4, r7, r8 |
1da177e4 LT |
459 | */ |
460 | .align 5 | |
461 | cache_on: mov r3, #8 @ cache_on function | |
462 | b call_cache_fn | |
463 | ||
10c2df65 HC |
464 | /* |
465 | * Initialize the highest priority protection region, PR7 | |
466 | * to cover all 32bit address and cacheable and bufferable. | |
467 | */ | |
468 | __armv4_mpu_cache_on: | |
469 | mov r0, #0x3f @ 4G, the whole | |
470 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
471 | mcr p15, 0, r0, c6, c7, 1 | |
472 | ||
473 | mov r0, #0x80 @ PR7 | |
474 | mcr p15, 0, r0, c2, c0, 0 @ D-cache on | |
475 | mcr p15, 0, r0, c2, c0, 1 @ I-cache on | |
476 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
477 | ||
478 | mov r0, #0xc000 | |
479 | mcr p15, 0, r0, c5, c0, 1 @ I-access permission | |
480 | mcr p15, 0, r0, c5, c0, 0 @ D-access permission | |
481 | ||
482 | mov r0, #0 | |
483 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
484 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
485 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
486 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
487 | @ ...I .... ..D. WC.M | |
488 | orr r0, r0, #0x002d @ .... .... ..1. 11.1 | |
489 | orr r0, r0, #0x1000 @ ...1 .... .... .... | |
490 | ||
491 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
492 | ||
493 | mov r0, #0 | |
494 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
495 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
496 | mov pc, lr | |
497 | ||
498 | __armv3_mpu_cache_on: | |
499 | mov r0, #0x3f @ 4G, the whole | |
500 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
501 | ||
502 | mov r0, #0x80 @ PR7 | |
503 | mcr p15, 0, r0, c2, c0, 0 @ cache on | |
504 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
505 | ||
506 | mov r0, #0xc000 | |
507 | mcr p15, 0, r0, c5, c0, 0 @ access permission | |
508 | ||
509 | mov r0, #0 | |
510 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
4a8d57a5 UKK |
511 | /* |
512 | * ?? ARMv3 MMU does not allow reading the control register, | |
513 | * does this really work on ARMv3 MPU? | |
514 | */ | |
10c2df65 HC |
515 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
516 | @ .... .... .... WC.M | |
517 | orr r0, r0, #0x000d @ .... .... .... 11.1 | |
4a8d57a5 | 518 | /* ?? this overwrites the value constructed above? */ |
10c2df65 HC |
519 | mov r0, #0 |
520 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
521 | ||
4a8d57a5 | 522 | /* ?? invalidate for the second time? */ |
10c2df65 HC |
523 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 |
524 | mov pc, lr | |
525 | ||
1da177e4 LT |
526 | __setup_mmu: sub r3, r4, #16384 @ Page directory size |
527 | bic r3, r3, #0xff @ Align the pointer | |
528 | bic r3, r3, #0x3f00 | |
529 | /* | |
530 | * Initialise the page tables, turning on the cacheable and bufferable | |
531 | * bits for the RAM area only. | |
532 | */ | |
533 | mov r0, r3 | |
f4619025 RK |
534 | mov r9, r0, lsr #18 |
535 | mov r9, r9, lsl #18 @ start of RAM | |
536 | add r10, r9, #0x10000000 @ a reasonable RAM size | |
1da177e4 LT |
537 | mov r1, #0x12 |
538 | orr r1, r1, #3 << 10 | |
539 | add r2, r3, #16384 | |
265d5e48 | 540 | 1: cmp r1, r9 @ if virt > start of RAM |
af3e4fd3 MG |
541 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH |
542 | orrhs r1, r1, #0x08 @ set cacheable | |
543 | #else | |
1da177e4 | 544 | orrhs r1, r1, #0x0c @ set cacheable, bufferable |
af3e4fd3 | 545 | #endif |
f4619025 | 546 | cmp r1, r10 @ if virt > end of RAM |
1da177e4 LT |
547 | bichs r1, r1, #0x0c @ clear cacheable, bufferable |
548 | str r1, [r0], #4 @ 1:1 mapping | |
549 | add r1, r1, #1048576 | |
550 | teq r0, r2 | |
551 | bne 1b | |
552 | /* | |
553 | * If ever we are running from Flash, then we surely want the cache | |
554 | * to be enabled also for our execution instance... We map 2MB of it | |
555 | * so there is no map overlap problem for up to 1 MB compressed kernel. | |
556 | * If the execution is in RAM then we would only be duplicating the above. | |
557 | */ | |
558 | mov r1, #0x1e | |
559 | orr r1, r1, #3 << 10 | |
bfa64c4a DM |
560 | mov r2, pc |
561 | mov r2, r2, lsr #20 | |
1da177e4 LT |
562 | orr r1, r1, r2, lsl #20 |
563 | add r0, r3, r2, lsl #2 | |
564 | str r1, [r0], #4 | |
565 | add r1, r1, #1048576 | |
566 | str r1, [r0] | |
567 | mov pc, lr | |
93ed3970 | 568 | ENDPROC(__setup_mmu) |
1da177e4 | 569 | |
af3e4fd3 MG |
570 | __arm926ejs_mmu_cache_on: |
571 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
572 | mov r0, #4 @ put dcache in WT mode | |
573 | mcr p15, 7, r0, c15, c0, 0 | |
574 | #endif | |
575 | ||
c76b6b41 | 576 | __armv4_mmu_cache_on: |
1da177e4 | 577 | mov r12, lr |
8bdca0ac | 578 | #ifdef CONFIG_MMU |
1da177e4 LT |
579 | bl __setup_mmu |
580 | mov r0, #0 | |
581 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
582 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
583 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
584 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
585 | orr r0, r0, #0x0030 | |
26584853 CM |
586 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
587 | orr r0, r0, #1 << 25 @ big-endian page tables | |
588 | #endif | |
c76b6b41 | 589 | bl __common_mmu_cache_on |
1da177e4 LT |
590 | mov r0, #0 |
591 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
8bdca0ac | 592 | #endif |
1da177e4 LT |
593 | mov pc, r12 |
594 | ||
7d09e854 CM |
595 | __armv7_mmu_cache_on: |
596 | mov r12, lr | |
8bdca0ac | 597 | #ifdef CONFIG_MMU |
7d09e854 CM |
598 | mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 |
599 | tst r11, #0xf @ VMSA | |
600 | blne __setup_mmu | |
601 | mov r0, #0 | |
602 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
603 | tst r11, #0xf @ VMSA | |
604 | mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
8bdca0ac | 605 | #endif |
7d09e854 CM |
606 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
607 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
608 | orr r0, r0, #0x003c @ write buffer | |
8bdca0ac | 609 | #ifdef CONFIG_MMU |
26584853 CM |
610 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
611 | orr r0, r0, #1 << 25 @ big-endian page tables | |
612 | #endif | |
7d09e854 CM |
613 | orrne r0, r0, #1 @ MMU enabled |
614 | movne r1, #-1 | |
615 | mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer | |
616 | mcrne p15, 0, r1, c3, c0, 0 @ load domain access control | |
8bdca0ac | 617 | #endif |
7d09e854 CM |
618 | mcr p15, 0, r0, c1, c0, 0 @ load control register |
619 | mrc p15, 0, r0, c1, c0, 0 @ and read it back | |
620 | mov r0, #0 | |
621 | mcr p15, 0, r0, c7, c5, 4 @ ISB | |
622 | mov pc, r12 | |
623 | ||
28853ac8 PZ |
624 | __fa526_cache_on: |
625 | mov r12, lr | |
626 | bl __setup_mmu | |
627 | mov r0, #0 | |
628 | mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache | |
629 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
630 | mcr p15, 0, r0, c8, c7, 0 @ flush UTLB | |
631 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
632 | orr r0, r0, #0x1000 @ I-cache enable | |
633 | bl __common_mmu_cache_on | |
634 | mov r0, #0 | |
635 | mcr p15, 0, r0, c8, c7, 0 @ flush UTLB | |
636 | mov pc, r12 | |
637 | ||
c76b6b41 | 638 | __arm6_mmu_cache_on: |
1da177e4 LT |
639 | mov r12, lr |
640 | bl __setup_mmu | |
641 | mov r0, #0 | |
642 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
643 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
644 | mov r0, #0x30 | |
c76b6b41 | 645 | bl __common_mmu_cache_on |
1da177e4 LT |
646 | mov r0, #0 |
647 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
648 | mov pc, r12 | |
649 | ||
c76b6b41 | 650 | __common_mmu_cache_on: |
0e056f20 | 651 | #ifndef CONFIG_THUMB2_KERNEL |
1da177e4 LT |
652 | #ifndef DEBUG |
653 | orr r0, r0, #0x000d @ Write buffer, mmu | |
654 | #endif | |
655 | mov r1, #-1 | |
656 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer | |
657 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control | |
2dc7667b NP |
658 | b 1f |
659 | .align 5 @ cache line aligned | |
660 | 1: mcr p15, 0, r0, c1, c0, 0 @ load control register | |
661 | mrc p15, 0, r0, c1, c0, 0 @ and read it back to | |
662 | sub pc, lr, r0, lsr #32 @ properly flush pipeline | |
0e056f20 | 663 | #endif |
1da177e4 | 664 | |
946a105e DM |
665 | #define PROC_ENTRY_SIZE (4*5) |
666 | ||
1da177e4 LT |
667 | /* |
668 | * Here follow the relocatable cache support functions for the | |
669 | * various processors. This is a generic hook for locating an | |
670 | * entry and jumping to an instruction at the specified offset | |
671 | * from the start of the block. Please note this is all position | |
672 | * independent code. | |
673 | * | |
674 | * r1 = corrupted | |
675 | * r2 = corrupted | |
676 | * r3 = block offset | |
98e12b5a | 677 | * r9 = corrupted |
1da177e4 LT |
678 | * r12 = corrupted |
679 | */ | |
680 | ||
681 | call_cache_fn: adr r12, proc_types | |
f12d0d7c | 682 | #ifdef CONFIG_CPU_CP15 |
98e12b5a | 683 | mrc p15, 0, r9, c0, c0 @ get processor ID |
f12d0d7c | 684 | #else |
98e12b5a | 685 | ldr r9, =CONFIG_PROCESSOR_ID |
f12d0d7c | 686 | #endif |
1da177e4 LT |
687 | 1: ldr r1, [r12, #0] @ get value |
688 | ldr r2, [r12, #4] @ get mask | |
98e12b5a | 689 | eor r1, r1, r9 @ (real ^ match) |
1da177e4 | 690 | tst r1, r2 @ & mask |
0e056f20 CM |
691 | ARM( addeq pc, r12, r3 ) @ call cache function |
692 | THUMB( addeq r12, r3 ) | |
693 | THUMB( moveq pc, r12 ) @ call cache function | |
946a105e | 694 | add r12, r12, #PROC_ENTRY_SIZE |
1da177e4 LT |
695 | b 1b |
696 | ||
697 | /* | |
698 | * Table for cache operations. This is basically: | |
699 | * - CPU ID match | |
700 | * - CPU ID mask | |
701 | * - 'cache on' method instruction | |
702 | * - 'cache off' method instruction | |
703 | * - 'cache flush' method instruction | |
704 | * | |
705 | * We match an entry using: ((real_id ^ match) & mask) == 0 | |
706 | * | |
707 | * Writethrough caches generally only need 'on' and 'off' | |
708 | * methods. Writeback caches _must_ have the flush method | |
709 | * defined. | |
710 | */ | |
88987ef9 | 711 | .align 2 |
1da177e4 LT |
712 | .type proc_types,#object |
713 | proc_types: | |
714 | .word 0x41560600 @ ARM6/610 | |
715 | .word 0xffffffe0 | |
0e056f20 CM |
716 | W(b) __arm6_mmu_cache_off @ works, but slow |
717 | W(b) __arm6_mmu_cache_off | |
1da177e4 | 718 | mov pc, lr |
0e056f20 | 719 | THUMB( nop ) |
c76b6b41 HC |
720 | @ b __arm6_mmu_cache_on @ untested |
721 | @ b __arm6_mmu_cache_off | |
722 | @ b __armv3_mmu_cache_flush | |
1da177e4 LT |
723 | |
724 | .word 0x00000000 @ old ARM ID | |
725 | .word 0x0000f000 | |
726 | mov pc, lr | |
0e056f20 | 727 | THUMB( nop ) |
1da177e4 | 728 | mov pc, lr |
0e056f20 | 729 | THUMB( nop ) |
1da177e4 | 730 | mov pc, lr |
0e056f20 | 731 | THUMB( nop ) |
1da177e4 LT |
732 | |
733 | .word 0x41007000 @ ARM7/710 | |
734 | .word 0xfff8fe00 | |
0e056f20 CM |
735 | W(b) __arm7_mmu_cache_off |
736 | W(b) __arm7_mmu_cache_off | |
1da177e4 | 737 | mov pc, lr |
0e056f20 | 738 | THUMB( nop ) |
1da177e4 LT |
739 | |
740 | .word 0x41807200 @ ARM720T (writethrough) | |
741 | .word 0xffffff00 | |
0e056f20 CM |
742 | W(b) __armv4_mmu_cache_on |
743 | W(b) __armv4_mmu_cache_off | |
1da177e4 | 744 | mov pc, lr |
0e056f20 | 745 | THUMB( nop ) |
1da177e4 | 746 | |
10c2df65 HC |
747 | .word 0x41007400 @ ARM74x |
748 | .word 0xff00ff00 | |
0e056f20 CM |
749 | W(b) __armv3_mpu_cache_on |
750 | W(b) __armv3_mpu_cache_off | |
751 | W(b) __armv3_mpu_cache_flush | |
10c2df65 HC |
752 | |
753 | .word 0x41009400 @ ARM94x | |
754 | .word 0xff00ff00 | |
0e056f20 CM |
755 | W(b) __armv4_mpu_cache_on |
756 | W(b) __armv4_mpu_cache_off | |
757 | W(b) __armv4_mpu_cache_flush | |
10c2df65 | 758 | |
af3e4fd3 MG |
759 | .word 0x41069260 @ ARM926EJ-S (v5TEJ) |
760 | .word 0xff0ffff0 | |
720c60e1 NP |
761 | W(b) __arm926ejs_mmu_cache_on |
762 | W(b) __armv4_mmu_cache_off | |
763 | W(b) __armv5tej_mmu_cache_flush | |
10c2df65 | 764 | |
1da177e4 LT |
765 | .word 0x00007000 @ ARM7 IDs |
766 | .word 0x0000f000 | |
767 | mov pc, lr | |
0e056f20 | 768 | THUMB( nop ) |
1da177e4 | 769 | mov pc, lr |
0e056f20 | 770 | THUMB( nop ) |
1da177e4 | 771 | mov pc, lr |
0e056f20 | 772 | THUMB( nop ) |
1da177e4 LT |
773 | |
774 | @ Everything from here on will be the new ID system. | |
775 | ||
776 | .word 0x4401a100 @ sa110 / sa1100 | |
777 | .word 0xffffffe0 | |
0e056f20 CM |
778 | W(b) __armv4_mmu_cache_on |
779 | W(b) __armv4_mmu_cache_off | |
780 | W(b) __armv4_mmu_cache_flush | |
1da177e4 LT |
781 | |
782 | .word 0x6901b110 @ sa1110 | |
783 | .word 0xfffffff0 | |
0e056f20 CM |
784 | W(b) __armv4_mmu_cache_on |
785 | W(b) __armv4_mmu_cache_off | |
786 | W(b) __armv4_mmu_cache_flush | |
1da177e4 | 787 | |
4157d317 HZ |
788 | .word 0x56056900 |
789 | .word 0xffffff00 @ PXA9xx | |
0e056f20 CM |
790 | W(b) __armv4_mmu_cache_on |
791 | W(b) __armv4_mmu_cache_off | |
792 | W(b) __armv4_mmu_cache_flush | |
49cbe786 EM |
793 | |
794 | .word 0x56158000 @ PXA168 | |
795 | .word 0xfffff000 | |
0e056f20 CM |
796 | W(b) __armv4_mmu_cache_on |
797 | W(b) __armv4_mmu_cache_off | |
798 | W(b) __armv5tej_mmu_cache_flush | |
49cbe786 | 799 | |
2e2023fe NP |
800 | .word 0x56050000 @ Feroceon |
801 | .word 0xff0f0000 | |
0e056f20 CM |
802 | W(b) __armv4_mmu_cache_on |
803 | W(b) __armv4_mmu_cache_off | |
804 | W(b) __armv5tej_mmu_cache_flush | |
3ebb5a2b | 805 | |
5587931c JS |
806 | #ifdef CONFIG_CPU_FEROCEON_OLD_ID |
807 | /* this conflicts with the standard ARMv5TE entry */ | |
808 | .long 0x41009260 @ Old Feroceon | |
809 | .long 0xff00fff0 | |
810 | b __armv4_mmu_cache_on | |
811 | b __armv4_mmu_cache_off | |
812 | b __armv5tej_mmu_cache_flush | |
813 | #endif | |
814 | ||
28853ac8 PZ |
815 | .word 0x66015261 @ FA526 |
816 | .word 0xff01fff1 | |
0e056f20 CM |
817 | W(b) __fa526_cache_on |
818 | W(b) __armv4_mmu_cache_off | |
819 | W(b) __fa526_cache_flush | |
28853ac8 | 820 | |
1da177e4 LT |
821 | @ These match on the architecture ID |
822 | ||
823 | .word 0x00020000 @ ARMv4T | |
824 | .word 0x000f0000 | |
0e056f20 CM |
825 | W(b) __armv4_mmu_cache_on |
826 | W(b) __armv4_mmu_cache_off | |
827 | W(b) __armv4_mmu_cache_flush | |
1da177e4 LT |
828 | |
829 | .word 0x00050000 @ ARMv5TE | |
830 | .word 0x000f0000 | |
0e056f20 CM |
831 | W(b) __armv4_mmu_cache_on |
832 | W(b) __armv4_mmu_cache_off | |
833 | W(b) __armv4_mmu_cache_flush | |
1da177e4 LT |
834 | |
835 | .word 0x00060000 @ ARMv5TEJ | |
836 | .word 0x000f0000 | |
0e056f20 CM |
837 | W(b) __armv4_mmu_cache_on |
838 | W(b) __armv4_mmu_cache_off | |
75216859 | 839 | W(b) __armv5tej_mmu_cache_flush |
1da177e4 | 840 | |
45a7b9cf | 841 | .word 0x0007b000 @ ARMv6 |
7d09e854 | 842 | .word 0x000ff000 |
0e056f20 CM |
843 | W(b) __armv4_mmu_cache_on |
844 | W(b) __armv4_mmu_cache_off | |
845 | W(b) __armv6_mmu_cache_flush | |
1da177e4 | 846 | |
7d09e854 CM |
847 | .word 0x000f0000 @ new CPU Id |
848 | .word 0x000f0000 | |
0e056f20 CM |
849 | W(b) __armv7_mmu_cache_on |
850 | W(b) __armv7_mmu_cache_off | |
851 | W(b) __armv7_mmu_cache_flush | |
7d09e854 | 852 | |
1da177e4 LT |
853 | .word 0 @ unrecognised type |
854 | .word 0 | |
855 | mov pc, lr | |
0e056f20 | 856 | THUMB( nop ) |
1da177e4 | 857 | mov pc, lr |
0e056f20 | 858 | THUMB( nop ) |
1da177e4 | 859 | mov pc, lr |
0e056f20 | 860 | THUMB( nop ) |
1da177e4 LT |
861 | |
862 | .size proc_types, . - proc_types | |
863 | ||
946a105e DM |
864 | /* |
865 | * If you get a "non-constant expression in ".if" statement" | |
866 | * error from the assembler on this line, check that you have | |
867 | * not accidentally written a "b" instruction where you should | |
868 | * have written W(b). | |
869 | */ | |
870 | .if (. - proc_types) % PROC_ENTRY_SIZE != 0 | |
871 | .error "The size of one or more proc_types entries is wrong." | |
872 | .endif | |
873 | ||
1da177e4 LT |
874 | /* |
875 | * Turn off the Cache and MMU. ARMv3 does not support | |
876 | * reading the control register, but ARMv4 does. | |
877 | * | |
21b2841d UKK |
878 | * On exit, |
879 | * r0, r1, r2, r3, r9, r12 corrupted | |
880 | * This routine must preserve: | |
6d7d0ae5 | 881 | * r4, r7, r8 |
1da177e4 LT |
882 | */ |
883 | .align 5 | |
884 | cache_off: mov r3, #12 @ cache_off function | |
885 | b call_cache_fn | |
886 | ||
10c2df65 HC |
887 | __armv4_mpu_cache_off: |
888 | mrc p15, 0, r0, c1, c0 | |
889 | bic r0, r0, #0x000d | |
890 | mcr p15, 0, r0, c1, c0 @ turn MPU and cache off | |
891 | mov r0, #0 | |
892 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
893 | mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache | |
894 | mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache | |
895 | mov pc, lr | |
896 | ||
897 | __armv3_mpu_cache_off: | |
898 | mrc p15, 0, r0, c1, c0 | |
899 | bic r0, r0, #0x000d | |
900 | mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off | |
901 | mov r0, #0 | |
902 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
903 | mov pc, lr | |
904 | ||
c76b6b41 | 905 | __armv4_mmu_cache_off: |
8bdca0ac | 906 | #ifdef CONFIG_MMU |
1da177e4 LT |
907 | mrc p15, 0, r0, c1, c0 |
908 | bic r0, r0, #0x000d | |
909 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off | |
910 | mov r0, #0 | |
911 | mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 | |
912 | mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 | |
8bdca0ac | 913 | #endif |
1da177e4 LT |
914 | mov pc, lr |
915 | ||
7d09e854 CM |
916 | __armv7_mmu_cache_off: |
917 | mrc p15, 0, r0, c1, c0 | |
8bdca0ac | 918 | #ifdef CONFIG_MMU |
7d09e854 | 919 | bic r0, r0, #0x000d |
8bdca0ac CM |
920 | #else |
921 | bic r0, r0, #0x000c | |
922 | #endif | |
7d09e854 CM |
923 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off |
924 | mov r12, lr | |
925 | bl __armv7_mmu_cache_flush | |
926 | mov r0, #0 | |
8bdca0ac | 927 | #ifdef CONFIG_MMU |
7d09e854 | 928 | mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB |
8bdca0ac | 929 | #endif |
c30c2f99 CM |
930 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC |
931 | mcr p15, 0, r0, c7, c10, 4 @ DSB | |
932 | mcr p15, 0, r0, c7, c5, 4 @ ISB | |
7d09e854 CM |
933 | mov pc, r12 |
934 | ||
c76b6b41 | 935 | __arm6_mmu_cache_off: |
1da177e4 | 936 | mov r0, #0x00000030 @ ARM6 control reg. |
c76b6b41 | 937 | b __armv3_mmu_cache_off |
1da177e4 | 938 | |
c76b6b41 | 939 | __arm7_mmu_cache_off: |
1da177e4 | 940 | mov r0, #0x00000070 @ ARM7 control reg. |
c76b6b41 | 941 | b __armv3_mmu_cache_off |
1da177e4 | 942 | |
c76b6b41 | 943 | __armv3_mmu_cache_off: |
1da177e4 LT |
944 | mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off |
945 | mov r0, #0 | |
946 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
947 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
948 | mov pc, lr | |
949 | ||
950 | /* | |
951 | * Clean and flush the cache to maintain consistency. | |
952 | * | |
1da177e4 | 953 | * On exit, |
21b2841d | 954 | * r1, r2, r3, r9, r10, r11, r12 corrupted |
1da177e4 | 955 | * This routine must preserve: |
6d7d0ae5 | 956 | * r4, r6, r7, r8 |
1da177e4 LT |
957 | */ |
958 | .align 5 | |
959 | cache_clean_flush: | |
960 | mov r3, #16 | |
961 | b call_cache_fn | |
962 | ||
10c2df65 HC |
963 | __armv4_mpu_cache_flush: |
964 | mov r2, #1 | |
965 | mov r3, #0 | |
966 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
967 | mov r1, #7 << 5 @ 8 segments | |
968 | 1: orr r3, r1, #63 << 26 @ 64 entries | |
969 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index | |
970 | subs r3, r3, #1 << 26 | |
971 | bcs 2b @ entries 63 to 0 | |
972 | subs r1, r1, #1 << 5 | |
973 | bcs 1b @ segments 7 to 0 | |
974 | ||
975 | teq r2, #0 | |
976 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
977 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
978 | mov pc, lr | |
979 | ||
28853ac8 PZ |
980 | __fa526_cache_flush: |
981 | mov r1, #0 | |
982 | mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache | |
983 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | |
984 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
985 | mov pc, lr | |
10c2df65 | 986 | |
c76b6b41 | 987 | __armv6_mmu_cache_flush: |
1da177e4 LT |
988 | mov r1, #0 |
989 | mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D | |
990 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB | |
991 | mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified | |
992 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
993 | mov pc, lr | |
994 | ||
7d09e854 CM |
995 | __armv7_mmu_cache_flush: |
996 | mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 | |
997 | tst r10, #0xf << 16 @ hierarchical cache (ARMv7) | |
7d09e854 | 998 | mov r10, #0 |
c30c2f99 | 999 | beq hierarchical |
7d09e854 CM |
1000 | mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D |
1001 | b iflush | |
1002 | hierarchical: | |
c30c2f99 | 1003 | mcr p15, 0, r10, c7, c10, 5 @ DMB |
0e056f20 | 1004 | stmfd sp!, {r0-r7, r9-r11} |
7d09e854 CM |
1005 | mrc p15, 1, r0, c0, c0, 1 @ read clidr |
1006 | ands r3, r0, #0x7000000 @ extract loc from clidr | |
1007 | mov r3, r3, lsr #23 @ left align loc bit field | |
1008 | beq finished @ if loc is 0, then no need to clean | |
1009 | mov r10, #0 @ start clean at cache level 0 | |
1010 | loop1: | |
1011 | add r2, r10, r10, lsr #1 @ work out 3x current cache level | |
1012 | mov r1, r0, lsr r2 @ extract cache type bits from clidr | |
1013 | and r1, r1, #7 @ mask of the bits for current cache only | |
1014 | cmp r1, #2 @ see what cache we have at this level | |
1015 | blt skip @ skip if no cache, or just i-cache | |
1016 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
1017 | mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr | |
1018 | mrc p15, 1, r1, c0, c0, 0 @ read the new csidr | |
1019 | and r2, r1, #7 @ extract the length of the cache lines | |
1020 | add r2, r2, #4 @ add 4 (line length offset) | |
1021 | ldr r4, =0x3ff | |
1022 | ands r4, r4, r1, lsr #3 @ find maximum number on the way size | |
000b5025 | 1023 | clz r5, r4 @ find bit position of way size increment |
7d09e854 CM |
1024 | ldr r7, =0x7fff |
1025 | ands r7, r7, r1, lsr #13 @ extract max number of the index size | |
1026 | loop2: | |
1027 | mov r9, r4 @ create working copy of max way size | |
1028 | loop3: | |
0e056f20 CM |
1029 | ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 |
1030 | ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 | |
1031 | THUMB( lsl r6, r9, r5 ) | |
1032 | THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 | |
1033 | THUMB( lsl r6, r7, r2 ) | |
1034 | THUMB( orr r11, r11, r6 ) @ factor index number into r11 | |
7d09e854 CM |
1035 | mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way |
1036 | subs r9, r9, #1 @ decrement the way | |
1037 | bge loop3 | |
1038 | subs r7, r7, #1 @ decrement the index | |
1039 | bge loop2 | |
1040 | skip: | |
1041 | add r10, r10, #2 @ increment cache number | |
1042 | cmp r3, r10 | |
1043 | bgt loop1 | |
1044 | finished: | |
0e056f20 | 1045 | ldmfd sp!, {r0-r7, r9-r11} |
7d09e854 CM |
1046 | mov r10, #0 @ swith back to cache level 0 |
1047 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
7d09e854 | 1048 | iflush: |
c30c2f99 | 1049 | mcr p15, 0, r10, c7, c10, 4 @ DSB |
7d09e854 | 1050 | mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB |
c30c2f99 CM |
1051 | mcr p15, 0, r10, c7, c10, 4 @ DSB |
1052 | mcr p15, 0, r10, c7, c5, 4 @ ISB | |
7d09e854 CM |
1053 | mov pc, lr |
1054 | ||
15754bf9 NP |
1055 | __armv5tej_mmu_cache_flush: |
1056 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache | |
1057 | bne 1b | |
1058 | mcr p15, 0, r0, c7, c5, 0 @ flush I cache | |
1059 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
1060 | mov pc, lr | |
1061 | ||
c76b6b41 | 1062 | __armv4_mmu_cache_flush: |
1da177e4 LT |
1063 | mov r2, #64*1024 @ default: 32K dcache size (*2) |
1064 | mov r11, #32 @ default: 32 byte line size | |
1065 | mrc p15, 0, r3, c0, c0, 1 @ read cache type | |
98e12b5a | 1066 | teq r3, r9 @ cache ID register present? |
1da177e4 LT |
1067 | beq no_cache_id |
1068 | mov r1, r3, lsr #18 | |
1069 | and r1, r1, #7 | |
1070 | mov r2, #1024 | |
1071 | mov r2, r2, lsl r1 @ base dcache size *2 | |
1072 | tst r3, #1 << 14 @ test M bit | |
1073 | addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 | |
1074 | mov r3, r3, lsr #12 | |
1075 | and r3, r3, #3 | |
1076 | mov r11, #8 | |
1077 | mov r11, r11, lsl r3 @ cache line size in bytes | |
1078 | no_cache_id: | |
0e056f20 CM |
1079 | mov r1, pc |
1080 | bic r1, r1, #63 @ align to longest cache line | |
1da177e4 | 1081 | add r2, r1, r2 |
0e056f20 CM |
1082 | 1: |
1083 | ARM( ldr r3, [r1], r11 ) @ s/w flush D cache | |
1084 | THUMB( ldr r3, [r1] ) @ s/w flush D cache | |
1085 | THUMB( add r1, r1, r11 ) | |
1da177e4 LT |
1086 | teq r1, r2 |
1087 | bne 1b | |
1088 | ||
1089 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | |
1090 | mcr p15, 0, r1, c7, c6, 0 @ flush D cache | |
1091 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
1092 | mov pc, lr | |
1093 | ||
c76b6b41 | 1094 | __armv3_mmu_cache_flush: |
10c2df65 | 1095 | __armv3_mpu_cache_flush: |
1da177e4 | 1096 | mov r1, #0 |
63fa7187 | 1097 | mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3 |
1da177e4 LT |
1098 | mov pc, lr |
1099 | ||
1100 | /* | |
1101 | * Various debugging routines for printing hex characters and | |
1102 | * memory, which again must be relocatable. | |
1103 | */ | |
1104 | #ifdef DEBUG | |
88987ef9 | 1105 | .align 2 |
1da177e4 LT |
1106 | .type phexbuf,#object |
1107 | phexbuf: .space 12 | |
1108 | .size phexbuf, . - phexbuf | |
1109 | ||
be6f9f00 | 1110 | @ phex corrupts {r0, r1, r2, r3} |
1da177e4 LT |
1111 | phex: adr r3, phexbuf |
1112 | mov r2, #0 | |
1113 | strb r2, [r3, r1] | |
1114 | 1: subs r1, r1, #1 | |
1115 | movmi r0, r3 | |
1116 | bmi puts | |
1117 | and r2, r0, #15 | |
1118 | mov r0, r0, lsr #4 | |
1119 | cmp r2, #10 | |
1120 | addge r2, r2, #7 | |
1121 | add r2, r2, #'0' | |
1122 | strb r2, [r3, r1] | |
1123 | b 1b | |
1124 | ||
be6f9f00 | 1125 | @ puts corrupts {r0, r1, r2, r3} |
4e6d488a | 1126 | puts: loadsp r3, r1 |
1da177e4 LT |
1127 | 1: ldrb r2, [r0], #1 |
1128 | teq r2, #0 | |
1129 | moveq pc, lr | |
5cd0c344 | 1130 | 2: writeb r2, r3 |
1da177e4 LT |
1131 | mov r1, #0x00020000 |
1132 | 3: subs r1, r1, #1 | |
1133 | bne 3b | |
1134 | teq r2, #'\n' | |
1135 | moveq r2, #'\r' | |
1136 | beq 2b | |
1137 | teq r0, #0 | |
1138 | bne 1b | |
1139 | mov pc, lr | |
be6f9f00 | 1140 | @ putc corrupts {r0, r1, r2, r3} |
1da177e4 LT |
1141 | putc: |
1142 | mov r2, r0 | |
1143 | mov r0, #0 | |
4e6d488a | 1144 | loadsp r3, r1 |
1da177e4 LT |
1145 | b 2b |
1146 | ||
be6f9f00 | 1147 | @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr} |
1da177e4 LT |
1148 | memdump: mov r12, r0 |
1149 | mov r10, lr | |
1150 | mov r11, #0 | |
1151 | 2: mov r0, r11, lsl #2 | |
1152 | add r0, r0, r12 | |
1153 | mov r1, #8 | |
1154 | bl phex | |
1155 | mov r0, #':' | |
1156 | bl putc | |
1157 | 1: mov r0, #' ' | |
1158 | bl putc | |
1159 | ldr r0, [r12, r11, lsl #2] | |
1160 | mov r1, #8 | |
1161 | bl phex | |
1162 | and r0, r11, #7 | |
1163 | teq r0, #3 | |
1164 | moveq r0, #' ' | |
1165 | bleq putc | |
1166 | and r0, r11, #7 | |
1167 | add r11, r11, #1 | |
1168 | teq r0, #7 | |
1169 | bne 1b | |
1170 | mov r0, #'\n' | |
1171 | bl putc | |
1172 | cmp r11, #64 | |
1173 | blt 2b | |
1174 | mov pc, r10 | |
1175 | #endif | |
1176 | ||
92c83ff1 | 1177 | .ltorg |
adcc2591 | 1178 | reloc_code_end: |
1da177e4 LT |
1179 | |
1180 | .align | |
b0c4d4ee | 1181 | .section ".stack", "aw", %nobits |
8d7e4cc2 NP |
1182 | .L_user_stack: .space 4096 |
1183 | .L_user_stack_end: |