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ARM: dts: am57xx-beagle-x15: Include the commercial grade thresholds
[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / am57xx-beagle-x15.dts
CommitLineData
5a0f93c6
NM		 1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra74x.dtsi"
266e62f9 11#include "am57xx-commercial-grade.dtsi"
5a0f93c6
NM		 12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14
15/ {
16 model = "TI AM5728 BeagleBoard-X15";
17 compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
18
19 aliases {
20 rtc0 = &mcp_rtc;
21 rtc1 = &tps659038_rtc;
00edd317 22 rtc2 = &rtc;
0c534938 23 display0 = &hdmi0;
5a0f93c6
NM		 24 };
25
26 memory {
27 device_type = "memory";
dae320ec 28 reg = <0x0 0x80000000 0x0 0x80000000>;
5a0f93c6
NM		 29 };
30
31 vdd_3v3: fixedregulator-vdd_3v3 {
32 compatible = "regulator-fixed";
33 regulator-name = "vdd_3v3";
34 vin-supply = <&regen1>;
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
37 };
38
d929e8bb
PU		 39 aic_dvdd: fixedregulator-aic_dvdd {
40 compatible = "regulator-fixed";
41 regulator-name = "aic_dvdd_fixed";
42 vin-supply = <&vdd_3v3>;
43 regulator-min-microvolt = <1800000>;
44 regulator-max-microvolt = <1800000>;
45 };
46
5a0f93c6
NM		 47 vtt_fixed: fixedregulator-vtt {
48 /* TPS51200 */
49 compatible = "regulator-fixed";
50 regulator-name = "vtt_fixed";
51 vin-supply = <&smps3_reg>;
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
54 regulator-always-on;
55 regulator-boot-on;
56 enable-active-high;
57 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
58 };
59
60 leds {
61 compatible = "gpio-leds";
62 pinctrl-names = "default";
63 pinctrl-0 = <&leds_pins_default>;
64
65 led@0 {
66 label = "beagle-x15:usr0";
67 gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
68 linux,default-trigger = "heartbeat";
69 default-state = "off";
70 };
71
72 led@1 {
73 label = "beagle-x15:usr1";
74 gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
75 linux,default-trigger = "cpu0";
76 default-state = "off";
77 };
78
79 led@2 {
80 label = "beagle-x15:usr2";
81 gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
82 linux,default-trigger = "mmc0";
83 default-state = "off";
84 };
85
86 led@3 {
87 label = "beagle-x15:usr3";
88 gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
89 linux,default-trigger = "ide-disk";
90 default-state = "off";
91 };
92 };
7a03f2c0
NM		 93
94 gpio_fan: gpio_fan {
95 /* Based on 5v 500mA AFB02505HHB */
96 compatible = "gpio-fan";
ed12f102 97 gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>;
7a03f2c0
NM		 98 gpio-fan,speed-map = <0 0>,
99 <13000 1>;
d723cfea 100 #cooling-cells = <2>;
7a03f2c0 101 };
f60db98e
RQ		 102
103 extcon_usb1: extcon_usb1 {
104 compatible = "linux,extcon-usb-gpio";
105 id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&extcon_usb1_pins>;
108 };
109
0c534938
TV		 110 hdmi0: connector {
111 compatible = "hdmi-connector";
112 label = "hdmi";
113
114 type = "a";
115
116 port {
117 hdmi_connector_in: endpoint {
118 remote-endpoint = <&tpd12s015_out>;
119 };
120 };
121 };
122
123 tpd12s015: encoder {
124 compatible = "ti,tpd12s015";
125
126 pinctrl-names = "default";
127 pinctrl-0 = <&tpd12s015_pins>;
128
129 gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
130 <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */
131 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
132
133 ports {
134 #address-cells = <1>;
135 #size-cells = <0>;
136
137 port@0 {
138 reg = <0>;
139
140 tpd12s015_in: endpoint {
141 remote-endpoint = <&hdmi_out>;
142 };
143 };
144
145 port@1 {
146 reg = <1>;
147
148 tpd12s015_out: endpoint {
149 remote-endpoint = <&hdmi_connector_in>;
150 };
151 };
152 };
153 };
a00e368c 154
4e8603ef 155 sound0: sound0 {
a00e368c
PU		 156 compatible = "simple-audio-card";
157 simple-audio-card,name = "BeagleBoard-X15";
158 simple-audio-card,widgets =
159 "Line", "Line Out",
160 "Line", "Line In";
161 simple-audio-card,routing =
162 "Line Out", "LLOUT",
163 "Line Out", "RLOUT",
164 "MIC2L", "Line In",
165 "MIC2R", "Line In";
166 simple-audio-card,format = "dsp_b";
167 simple-audio-card,bitclock-master = <&sound0_master>;
168 simple-audio-card,frame-master = <&sound0_master>;
169 simple-audio-card,bitclock-inversion;
170
171 simple-audio-card,cpu {
172 sound-dai = <&mcasp3>;
173 };
174
175 sound0_master: simple-audio-card,codec {
176 sound-dai = <&tlv320aic3104>;
177 clocks = <&clkout2_clk>;
178 };
179 };
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NM		 180};
181
182&dra7_pmx_core {
183 leds_pins_default: leds_pins_default {
184 pinctrl-single,pins = <
f70dfa66
JMC		 185 DRA7XX_CORE_IOPAD(0x37a8, PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */
186 DRA7XX_CORE_IOPAD(0x37ac, PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */
187 DRA7XX_CORE_IOPAD(0x37c0, PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */
188 DRA7XX_CORE_IOPAD(0x37c4, PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */
5a0f93c6
NM		 189 >;
190 };
191
192 i2c1_pins_default: i2c1_pins_default {
193 pinctrl-single,pins = <
f70dfa66
JMC		 194 DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
195 DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
5a0f93c6
NM		 196 >;
197 };
198
0c534938
TV		 199 hdmi_pins: pinmux_hdmi_pins {
200 pinctrl-single,pins = <
f70dfa66
JMC		 201 DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
202 DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
0c534938
TV		 203 >;
204 };
205
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NM		 206 i2c3_pins_default: i2c3_pins_default {
207 pinctrl-single,pins = <
f70dfa66
JMC		 208 DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
209 DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
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NM		 210 >;
211 };
212
213 uart3_pins_default: uart3_pins_default {
214 pinctrl-single,pins = <
f70dfa66
JMC		 215 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */
216 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */
5a0f93c6
NM		 217 >;
218 };
219
220 mmc1_pins_default: mmc1_pins_default {
221 pinctrl-single,pins = <
f70dfa66
JMC		 222 DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
223 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
224 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
225 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
226 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
227 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
228 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
5a0f93c6
NM		 229 >;
230 };
231
232 mmc2_pins_default: mmc2_pins_default {
233 pinctrl-single,pins = <
f70dfa66
JMC		 234 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
235 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
236 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
237 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
238 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
239 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
240 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
241 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
242 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
243 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
5a0f93c6
NM		 244 >;
245 };
246
a75dacf8
FB		 247 cpsw_pins_default: cpsw_pins_default {
248 pinctrl-single,pins = <
249 /* Slave 1 */
f70dfa66
JMC		 250 DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
251 DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
252 DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
253 DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
254 DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
255 DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
256 DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
257 DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
258 DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
259 DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
260 DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
261 DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
a75dacf8
FB		 262
263 /* Slave 2 */
f70dfa66
JMC		 264 DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
265 DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
266 DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
267 DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
268 DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
269 DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
270 DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
271 DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
272 DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
273 DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
274 DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
275 DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
a75dacf8
FB		 276 >;
277
278 };
279
280 cpsw_pins_sleep: cpsw_pins_sleep {
281 pinctrl-single,pins = <
282 /* Slave 1 */
f70dfa66
JMC		 283 DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15)
284 DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15)
285 DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
286 DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
287 DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
288 DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
289 DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15)
290 DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15)
291 DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15)
292 DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)
293 DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
294 DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
a75dacf8
FB		 295
296 /* Slave 2 */
f70dfa66
JMC		 297 DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15)
298 DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15)
299 DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15)
300 DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15)
301 DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15)
302 DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15)
303 DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15)
304 DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15)
305 DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15)
306 DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15)
307 DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15)
308 DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15)
a75dacf8
FB		 309 >;
310 };
311
312 davinci_mdio_pins_default: davinci_mdio_pins_default {
313 pinctrl-single,pins = <
314 /* MDIO */
f70dfa66
JMC		 315 DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */
316 DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */
a75dacf8
FB		 317 >;
318 };
319
320 davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
321 pinctrl-single,pins = <
f70dfa66
JMC		 322 DRA7XX_CORE_IOPAD(0x363c, PIN_INPUT | MUX_MODE15)
323 DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT | MUX_MODE15)
a75dacf8
FB		 324 >;
325 };
326
5a0f93c6
NM		 327 tps659038_pins_default: tps659038_pins_default {
328 pinctrl-single,pins = <
f70dfa66 329 DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
5a0f93c6
NM		 330 >;
331 };
332
333 tmp102_pins_default: tmp102_pins_default {
334 pinctrl-single,pins = <
f70dfa66 335 DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */
5a0f93c6
NM		 336 >;
337 };
338
339 mcp79410_pins_default: mcp79410_pins_default {
340 pinctrl-single,pins = <
f70dfa66 341 DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
5a0f93c6
NM		 342 >;
343 };
344
345 usb1_pins: pinmux_usb1_pins {
346 pinctrl-single,pins = <
f70dfa66 347 DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
5a0f93c6
NM		 348 >;
349 };
350
f60db98e
RQ		 351 extcon_usb1_pins: extcon_usb1_pins {
352 pinctrl-single,pins = <
f70dfa66 353 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
f60db98e
RQ		 354 >;
355 };
356
0c534938
TV		 357 tpd12s015_pins: pinmux_tpd12s015_pins {
358 pinctrl-single,pins = <
f70dfa66
JMC		 359 DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */
360 DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
361 DRA7XX_CORE_IOPAD(0x3770, PIN_OUTPUT | MUX_MODE14) /* gpio6_28 LS_OE */
0c534938
TV		 362 >;
363 };
a00e368c
PU		 364
365 clkout2_pins_default: clkout2_pins_default {
366 pinctrl-single,pins = <
f70dfa66 367 DRA7XX_CORE_IOPAD(0x3694, PIN_OUTPUT_PULLDOWN | MUX_MODE9) /* xref_clk0.clkout2 */
a00e368c
PU		 368 >;
369 };
370
371 clkout2_pins_sleep: clkout2_pins_sleep {
372 pinctrl-single,pins = <
f70dfa66 373 DRA7XX_CORE_IOPAD(0x3694, PIN_INPUT | MUX_MODE15) /* xref_clk0.clkout2 */
a00e368c
PU		 374 >;
375 };
376
377 mcasp3_pins_default: mcasp3_pins_default {
378 pinctrl-single,pins = <
f70dfa66
JMC		 379 DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */
380 DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
381 DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
382 DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
a00e368c
PU		 383 >;
384 };
385
386 mcasp3_pins_sleep: mcasp3_pins_sleep {
387 pinctrl-single,pins = <
f70dfa66
JMC		 388 DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15)
389 DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15)
390 DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15)
391 DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15)
a00e368c
PU		 392 >;
393 };
5a0f93c6
NM		 394};
395
396&i2c1 {
397 status = "okay";
398 pinctrl-names = "default";
399 pinctrl-0 = <&i2c1_pins_default>;
400 clock-frequency = <400000>;
401
402 tps659038: tps659038@58 {
403 compatible = "ti,tps659038";
404 reg = <0x58>;
405 interrupt-parent = <&gpio1>;
406 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
407
408 pinctrl-names = "default";
409 pinctrl-0 = <&tps659038_pins_default>;
410
411 #interrupt-cells = <2>;
412 interrupt-controller;
413
414 ti,system-power-controller;
415
416 tps659038_pmic {
417 compatible = "ti,tps659038-pmic";
418
419 regulators {
420 smps12_reg: smps12 {
421 /* VDD_MPU */
422 regulator-name = "smps12";
423 regulator-min-microvolt = < 850000>;
424 regulator-max-microvolt = <1250000>;
425 regulator-always-on;
426 regulator-boot-on;
427 };
428
429 smps3_reg: smps3 {
430 /* VDD_DDR */
431 regulator-name = "smps3";
432 regulator-min-microvolt = <1350000>;
433 regulator-max-microvolt = <1350000>;
434 regulator-always-on;
435 regulator-boot-on;
436 };
437
438 smps45_reg: smps45 {
439 /* VDD_DSPEVE, VDD_IVA, VDD_GPU */
440 regulator-name = "smps45";
441 regulator-min-microvolt = < 850000>;
54d03c5d 442 regulator-max-microvolt = <1250000>;
5a0f93c6
NM		 443 regulator-always-on;
444 regulator-boot-on;
445 };
446
447 smps6_reg: smps6 {
448 /* VDD_CORE */
449 regulator-name = "smps6";
450 regulator-min-microvolt = <850000>;
54d03c5d 451 regulator-max-microvolt = <1150000>;
5a0f93c6
NM		 452 regulator-always-on;
453 regulator-boot-on;
454 };
455
456 /* SMPS7 unused */
457
458 smps8_reg: smps8 {
459 /* VDD_1V8 */
460 regulator-name = "smps8";
461 regulator-min-microvolt = <1800000>;
462 regulator-max-microvolt = <1800000>;
463 regulator-always-on;
464 regulator-boot-on;
465 };
466
467 /* SMPS9 unused */
468
469 ldo1_reg: ldo1 {
7e381ec6 470 /* VDD_SD / VDDSHV8 */
5a0f93c6
NM		 471 regulator-name = "ldo1";
472 regulator-min-microvolt = <1800000>;
473 regulator-max-microvolt = <3300000>;
474 regulator-boot-on;
7e381ec6 475 regulator-always-on;
5a0f93c6
NM		 476 };
477
478 ldo2_reg: ldo2 {
479 /* VDD_SHV5 */
480 regulator-name = "ldo2";
481 regulator-min-microvolt = <3300000>;
482 regulator-max-microvolt = <3300000>;
483 regulator-always-on;
484 regulator-boot-on;
485 };
486
487 ldo3_reg: ldo3 {
5005296e 488 /* VDDA_1V8_PHYA */
5a0f93c6
NM		 489 regulator-name = "ldo3";
490 regulator-min-microvolt = <1800000>;
491 regulator-max-microvolt = <1800000>;
492 regulator-always-on;
493 regulator-boot-on;
494 };
495
5005296e
NM		 496 ldo4_reg: ldo4 {
497 /* VDDA_1V8_PHYB */
498 regulator-name = "ldo4";
499 regulator-min-microvolt = <1800000>;
500 regulator-max-microvolt = <1800000>;
501 regulator-always-on;
502 regulator-boot-on;
503 };
504
5a0f93c6
NM		 505 ldo9_reg: ldo9 {
506 /* VDD_RTC */
507 regulator-name = "ldo9";
508 regulator-min-microvolt = <1050000>;
509 regulator-max-microvolt = <1050000>;
510 regulator-always-on;
511 regulator-boot-on;
512 };
513
514 ldoln_reg: ldoln {
515 /* VDDA_1V8_PLL */
516 regulator-name = "ldoln";
517 regulator-min-microvolt = <1800000>;
518 regulator-max-microvolt = <1800000>;
519 regulator-always-on;
520 regulator-boot-on;
521 };
522
523 ldousb_reg: ldousb {
524 /* VDDA_3V_USB: VDDA_USBHS33 */
525 regulator-name = "ldousb";
526 regulator-min-microvolt = <3300000>;
527 regulator-max-microvolt = <3300000>;
528 regulator-boot-on;
529 };
530
531 regen1: regen1 {
532 /* VDD_3V3_ON */
533 regulator-name = "regen1";
534 regulator-boot-on;
535 regulator-always-on;
536 };
537 };
538 };
539
540 tps659038_rtc: tps659038_rtc {
541 compatible = "ti,palmas-rtc";
542 interrupt-parent = <&tps659038>;
543 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
544 wakeup-source;
545 };
546
547 tps659038_pwr_button: tps659038_pwr_button {
548 compatible = "ti,palmas-pwrbutton";
549 interrupt-parent = <&tps659038>;
550 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
551 wakeup-source;
552 ti,palmas-long-press-seconds = <12>;
553 };
7a03f2c0
NM		 554
555 tps659038_gpio: tps659038_gpio {
556 compatible = "ti,palmas-gpio";
557 gpio-controller;
558 #gpio-cells = <2>;
559 };
84ad1bab
RQ		 560
561 extcon_usb2: tps659038_usb {
562 compatible = "ti,palmas-usb-vid";
563 ti,enable-vbus-detection;
0331966d 564 vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
84ad1bab
RQ		 565 };
566
5a0f93c6
NM		 567 };
568
569 tmp102: tmp102@48 {
570 compatible = "ti,tmp102";
571 reg = <0x48>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&tmp102_pins_default>;
574 interrupt-parent = <&gpio7>;
575 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
d723cfea 576 #thermal-sensor-cells = <1>;
5a0f93c6 577 };
a00e368c
PU		 578
579 tlv320aic3104: tlv320aic3104@18 {
580 #sound-dai-cells = <0>;
581 compatible = "ti,tlv320aic3104";
582 reg = <0x18>;
583 pinctrl-names = "default", "sleep";
584 pinctrl-0 = <&clkout2_pins_default>;
585 pinctrl-1 = <&clkout2_pins_sleep>;
e80ab5c9
PU		 586 assigned-clocks = <&clkoutmux2_clk_mux>;
587 assigned-clock-parents = <&sys_clk2_dclk_div>;
588
a00e368c
PU		 589 status = "okay";
590 adc-settle-ms = <40>;
591
592 AVDD-supply = <&vdd_3v3>;
593 IOVDD-supply = <&vdd_3v3>;
594 DRVDD-supply = <&vdd_3v3>;
595 DVDD-supply = <&aic_dvdd>;
596 };
b9d3ec1d
NM		 597
598 eeprom: eeprom@50 {
599 compatible = "at,24c32";
600 reg = <0x50>;
601 };
5a0f93c6
NM		 602};
603
604&i2c3 {
605 status = "okay";
606 pinctrl-names = "default";
607 pinctrl-0 = <&i2c3_pins_default>;
608 clock-frequency = <400000>;
609
610 mcp_rtc: rtc@6f {
611 compatible = "microchip,mcp7941x";
612 reg = <0x6f>;
c22c7f3e
NM		 613 interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
614 <&dra7_pmx_core 0x424>;
51c4cfef 615 interrupt-names = "irq", "wakeup";
5a0f93c6
NM		 616
617 pinctrl-names = "default";
618 pinctrl-0 = <&mcp79410_pins_default>;
619
620 vcc-supply = <&vdd_3v3>;
621 wakeup-source;
622 };
623};
624
625&gpio7 {
626 ti,no-reset-on-init;
627 ti,no-idle-on-init;
628};
629
630&cpu0 {
631 cpu0-supply = <&smps12_reg>;
632 voltage-tolerance = <1>;
633};
634
635&uart3 {
636 status = "okay";
783d3186 637 interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
5eb67198 638 <&dra7_pmx_core 0x3f8>;
5a0f93c6
NM		 639
640 pinctrl-names = "default";
641 pinctrl-0 = <&uart3_pins_default>;
642};
643
a75dacf8
FB		 644&mac {
645 status = "okay";
646 pinctrl-names = "default", "sleep";
647 pinctrl-0 = <&cpsw_pins_default>;
648 pinctrl-1 = <&cpsw_pins_sleep>;
649 dual_emac;
650};
651
652&cpsw_emac0 {
653 phy_id = <&davinci_mdio>, <1>;
654 phy-mode = "rgmii";
655 dual_emac_res_vlan = <1>;
656};
657
658&cpsw_emac1 {
659 phy_id = <&davinci_mdio>, <2>;
660 phy-mode = "rgmii";
661 dual_emac_res_vlan = <2>;
662};
663
664&davinci_mdio {
665 pinctrl-names = "default", "sleep";
666 pinctrl-0 = <&davinci_mdio_pins_default>;
667 pinctrl-1 = <&davinci_mdio_pins_sleep>;
668};
669
5a0f93c6
NM		 670&mmc1 {
671 status = "okay";
672
673 pinctrl-names = "default";
674 pinctrl-0 = <&mmc1_pins_default>;
675
676 vmmc-supply = <&ldo1_reg>;
5a0f93c6 677 bus-width = <4>;
267068d8 678 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
5a0f93c6
NM		 679};
680
681&mmc2 {
682 status = "okay";
683
684 pinctrl-names = "default";
685 pinctrl-0 = <&mmc2_pins_default>;
686
687 vmmc-supply = <&vdd_3v3>;
688 bus-width = <8>;
689 ti,non-removable;
690 cap-mmc-dual-data-rate;
691};
692
693&sata {
694 status = "okay";
695};
696
697&usb2_phy1 {
698 phy-supply = <&ldousb_reg>;
699};
700
9ab402ae
RQ		 701&usb2_phy2 {
702 phy-supply = <&ldousb_reg>;
703};
704
5a0f93c6
NM		 705&usb1 {
706 dr_mode = "host";
707 pinctrl-names = "default";
708 pinctrl-0 = <&usb1_pins>;
709};
f60db98e 710
a7b0aa19
RQ		 711&omap_dwc3_1 {
712 extcon = <&extcon_usb1>;
713};
714
715&omap_dwc3_2 {
716 extcon = <&extcon_usb2>;
717};
718
726806ad 719&usb2 {
84ad1bab
RQ		 720 /*
721 * Stand alone usage is peripheral only.
722 * However, with some resistor modifications
723 * this port can be used via expansion connectors
724 * as "host" or "dual-role". If so, provide
725 * the necessary dr_mode override in the expansion
726 * board's DT.
727 */
726806ad
RQ		 728 dr_mode = "peripheral";
729};
d723cfea
NM		 730
731&cpu_trips {
732 cpu_alert1: cpu_alert1 {
733 temperature = <50000>; /* millicelsius */
734 hysteresis = <2000>; /* millicelsius */
735 type = "active";
736 };
737};
738
739&cpu_cooling_maps {
740 map1 {
741 trip = <&cpu_alert1>;
742 cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
743 };
744};
745
746&thermal_zones {
747 board_thermal: board_thermal {
748 polling-delay-passive = <1250>; /* milliseconds */
749 polling-delay = <1500>; /* milliseconds */
750
751 /* sensor ID */
752 thermal-sensors = <&tmp102 0>;
753
754 board_trips: trips {
755 board_alert0: board_alert {
756 temperature = <40000>; /* millicelsius */
757 hysteresis = <2000>; /* millicelsius */
758 type = "active";
759 };
760
761 board_crit: board_crit {
762 temperature = <105000>; /* millicelsius */
763 hysteresis = <0>; /* millicelsius */
764 type = "critical";
765 };
766 };
767
768 board_cooling_maps: cooling-maps {
769 map0 {
770 trip = <&board_alert0>;
771 cooling-device =
772 <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
773 };
774 };
775 };
776};
0c534938
TV		 777
778&dss {
779 status = "ok";
780
781 vdda_video-supply = <&ldoln_reg>;
782};
783
784&hdmi {
785 status = "ok";
5005296e 786 vdda-supply = <&ldo4_reg>;
0c534938
TV		 787
788 pinctrl-names = "default";
789 pinctrl-0 = <&hdmi_pins>;
790
791 port {
792 hdmi_out: endpoint {
793 remote-endpoint = <&tpd12s015_in>;
794 };
795 };
796};
73c8f0cb
KVA		 797
798&pcie1 {
799 gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
800};
a00e368c
PU		 801
802&mcasp3 {
803 #sound-dai-cells = <0>;
804 pinctrl-names = "default", "sleep";
805 pinctrl-0 = <&mcasp3_pins_default>;
806 pinctrl-1 = <&mcasp3_pins_sleep>;
bf26927b
PU		 807 assigned-clocks = <&mcasp3_ahclkx_mux>;
808 assigned-clock-parents = <&sys_clkin2>;
a00e368c
PU		 809 status = "okay";
810
811 op-mode = <0>; /* MCASP_IIS_MODE */
812 tdm-slots = <2>;
813 /* 4 serializers */
814 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
815 1 2 0 0
816 >;
42b2274d
PU		 817 tx-num-evt = <32>;
818 rx-num-evt = <32>;
a00e368c 819};
ebbf93f0
SA		 820
821&mailbox5 {
822 status = "okay";
823 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
824 status = "okay";
825 };
826 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
827 status = "okay";
828 };
829};
830
831&mailbox6 {
832 status = "okay";
833 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
834 status = "okay";
835 };
836 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
837 status = "okay";
838 };
839};
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