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ca36855e | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
beb9ab5e RK |
2 | /* |
3 | * Device Tree file for SolidRun Clearfog Base revision A1 rev 2.0 (88F6828) | |
4 | * | |
5 | * Copyright (C) 2015 Russell King | |
beb9ab5e RK |
6 | */ |
7 | ||
8 | /dts-v1/; | |
9 | #include "armada-388-clearfog.dtsi" | |
10 | ||
11 | / { | |
12 | model = "SolidRun Clearfog Base A1"; | |
13 | compatible = "solidrun,clearfog-base-a1", | |
14 | "solidrun,clearfog-a1", "marvell,armada388", | |
15 | "marvell,armada385", "marvell,armada380"; | |
16 | ||
17 | gpio-keys { | |
18 | compatible = "gpio-keys"; | |
19 | pinctrl-0 = <&rear_button_pins>; | |
20 | pinctrl-names = "default"; | |
21 | ||
22 | button_0 { | |
23 | /* The rear SW3 button */ | |
24 | label = "Rear Button"; | |
25 | gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; | |
26 | linux,can-disable; | |
27 | linux,code = <BTN_0>; | |
28 | }; | |
29 | }; | |
30 | }; | |
31 | ||
32 | ð1 { | |
33 | phy = <&phy1>; | |
34 | }; | |
35 | ||
36 | &gpio0 { | |
37 | phy1_reset { | |
38 | gpio-hog; | |
39 | gpios = <19 GPIO_ACTIVE_LOW>; | |
40 | output-low; | |
41 | line-name = "phy1-reset"; | |
42 | }; | |
43 | }; | |
44 | ||
45 | &mdio { | |
46 | pinctrl-0 = <&mdio_pins µsom_phy_clk_pins &clearfog_phy_pins>; | |
47 | phy1: ethernet-phy@1 { | |
48 | /* | |
49 | * Annoyingly, the marvell phy driver configures the LED | |
50 | * register, rather than preserving reset-loaded setting. | |
51 | * We undo that rubbish here. | |
52 | */ | |
53 | marvell,reg-init = <3 16 0 0x101e>; | |
54 | reg = <1>; | |
55 | }; | |
56 | }; | |
57 | ||
58 | &pinctrl { | |
59 | /* phy1 reset */ | |
60 | clearfog_phy_pins: clearfog-phy-pins { | |
61 | marvell,pins = "mpp19"; | |
62 | marvell,function = "gpio"; | |
63 | }; | |
64 | rear_button_pins: rear-button-pins { | |
65 | marvell,pins = "mpp44"; | |
66 | marvell,function = "gpio"; | |
67 | }; | |
68 | }; |