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21dd0ece PR |
1 | /* |
2 | * at91-tse850-3.dts - Device Tree file for the Axentia TSE-850 3.0 board | |
3 | * | |
4 | * Copyright (C) 2017 Axentia Technologies AB | |
5 | * | |
6 | * Author: Peter Rosin <peda@axentia.se> | |
7 | * | |
8 | * Licensed under GPLv2 or later. | |
9 | */ | |
10 | /dts-v1/; | |
11 | #include <dt-bindings/pwm/pwm.h> | |
12 | #include "at91-linea.dtsi" | |
13 | ||
14 | / { | |
15 | model = "Axentia TSE-850 3.0"; | |
16 | compatible = "axentia,tse850v3", "axentia,linea", | |
17 | "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; | |
18 | ||
19 | ahb { | |
20 | apb { | |
21 | pinctrl@fffff200 { | |
22 | tse850 { | |
23 | pinctrl_usba_vbus: usba-vbus { | |
24 | atmel,pins = | |
25 | <AT91_PIOC 31 | |
26 | AT91_PERIPH_GPIO | |
27 | AT91_PINCTRL_DEGLITCH>; | |
28 | }; | |
29 | }; | |
30 | }; | |
31 | ||
32 | watchdog@fffffe40 { | |
33 | status = "okay"; | |
34 | }; | |
35 | }; | |
36 | }; | |
37 | ||
38 | sck: oscillator { | |
39 | compatible = "fixed-clock"; | |
40 | ||
41 | #clock-cells = <0>; | |
42 | clock-frequency = <16000000>; | |
43 | clock-output-names = "sck"; | |
44 | }; | |
45 | ||
46 | reg_3v3: regulator { | |
47 | compatible = "regulator-fixed"; | |
48 | ||
49 | regulator-name = "3v3-supply"; | |
50 | regulator-min-microvolt = <3300000>; | |
51 | regulator-max-microvolt = <3300000>; | |
52 | }; | |
53 | ||
54 | ana: reg-ana { | |
55 | compatible = "pwm-regulator"; | |
56 | ||
57 | regulator-name = "ANA"; | |
58 | ||
59 | pwms = <&pwm0 2 1000 PWM_POLARITY_INVERTED>; | |
60 | pwm-dutycycle-unit = <1000>; | |
61 | pwm-dutycycle-range = <100 1000>; | |
62 | ||
63 | regulator-min-microvolt = <2000000>; | |
64 | regulator-max-microvolt = <20000000>; | |
65 | regulator-ramp-delay = <1000>; | |
66 | }; | |
67 | ||
68 | sound { | |
69 | compatible = "axentia,tse850-pcm5142"; | |
70 | ||
71 | axentia,cpu-dai = <&ssc0>; | |
72 | axentia,audio-codec = <&pcm5142>; | |
73 | ||
74 | axentia,add-gpios = <&pioA 8 GPIO_ACTIVE_LOW>; | |
75 | axentia,loop1-gpios = <&pioA 10 GPIO_ACTIVE_LOW>; | |
76 | axentia,loop2-gpios = <&pioA 11 GPIO_ACTIVE_LOW>; | |
77 | ||
78 | axentia,ana-supply = <&ana>; | |
79 | }; | |
80 | ||
81 | dac: dpot-dac { | |
82 | compatible = "dpot-dac"; | |
83 | vref-supply = <®_3v3>; | |
84 | io-channels = <&dpot 0>; | |
85 | io-channel-names = "dpot"; | |
86 | #io-channel-cells = <1>; | |
87 | }; | |
88 | ||
e67cedc9 | 89 | env_det: envelope-detector { |
21dd0ece PR |
90 | compatible = "axentia,tse850-envelope-detector"; |
91 | io-channels = <&dac 0>; | |
92 | io-channel-names = "dac"; | |
e67cedc9 | 93 | #io-channel-cells = <1>; |
21dd0ece PR |
94 | |
95 | interrupt-parent = <&pioA>; | |
96 | interrupts = <3 IRQ_TYPE_EDGE_RISING>; | |
97 | interrupt-names = "comp"; | |
98 | }; | |
99 | ||
e67cedc9 PR |
100 | mux: mux-controller { |
101 | compatible = "gpio-mux"; | |
102 | #mux-control-cells = <0>; | |
103 | ||
104 | mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>, | |
105 | <&pioA 1 GPIO_ACTIVE_HIGH>, | |
106 | <&pioA 2 GPIO_ACTIVE_HIGH>; | |
107 | idle-state = <0>; | |
108 | }; | |
109 | ||
110 | envelope-detector-mux { | |
111 | compatible = "io-channel-mux"; | |
112 | io-channels = <&env_det 0>; | |
113 | io-channel-names = "parent"; | |
114 | ||
115 | mux-controls = <&mux>; | |
116 | ||
117 | channels = "", "", | |
118 | "sync-1", | |
119 | "in", | |
120 | "out", | |
121 | "sync-2", | |
122 | "sys-reg", | |
123 | "ana-reg"; | |
124 | }; | |
125 | ||
21dd0ece PR |
126 | leds { |
127 | compatible = "gpio-leds"; | |
128 | ||
129 | ch1-red { | |
130 | label = "ch-1:red"; | |
131 | gpios = <&pioA 23 GPIO_ACTIVE_LOW>; | |
132 | }; | |
133 | ch1-green { | |
134 | label = "ch-1:green"; | |
135 | gpios = <&pioA 22 GPIO_ACTIVE_LOW>; | |
136 | }; | |
137 | ch2-red { | |
138 | label = "ch-2:red"; | |
139 | gpios = <&pioA 21 GPIO_ACTIVE_LOW>; | |
140 | }; | |
141 | ch2-green { | |
142 | label = "ch-2:green"; | |
143 | gpios = <&pioA 20 GPIO_ACTIVE_LOW>; | |
144 | }; | |
145 | data-red { | |
146 | label = "data:red"; | |
147 | gpios = <&pioA 19 GPIO_ACTIVE_LOW>; | |
148 | }; | |
149 | data-green { | |
150 | label = "data:green"; | |
151 | gpios = <&pioA 18 GPIO_ACTIVE_LOW>; | |
152 | }; | |
153 | alarm-red { | |
154 | label = "alarm:red"; | |
155 | gpios = <&pioA 17 GPIO_ACTIVE_LOW>; | |
156 | }; | |
157 | alarm-green { | |
158 | label = "alarm:green"; | |
159 | gpios = <&pioA 16 GPIO_ACTIVE_LOW>; | |
160 | }; | |
161 | }; | |
162 | }; | |
163 | ||
1004a297 BB |
164 | &nand { |
165 | partitions { | |
166 | compatible = "fixed-partitions"; | |
167 | #address-cells = <1>; | |
168 | #size-cells = <1>; | |
169 | ||
170 | at91bootstrap@0 { | |
171 | label = "at91bootstrap"; | |
172 | reg = <0x0 0x40000>; | |
173 | }; | |
21dd0ece | 174 | |
1004a297 BB |
175 | barebox@40000 { |
176 | label = "bootloader"; | |
177 | reg = <0x40000 0x60000>; | |
178 | }; | |
21dd0ece | 179 | |
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180 | bareboxenv@c0000 { |
181 | label = "bareboxenv"; | |
182 | reg = <0xc0000 0x40000>; | |
183 | }; | |
21dd0ece | 184 | |
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185 | bareboxenv2@100000 { |
186 | label = "bareboxenv2"; | |
187 | reg = <0x100000 0x40000>; | |
188 | }; | |
21dd0ece | 189 | |
1004a297 BB |
190 | oftree@180000 { |
191 | label = "oftree"; | |
192 | reg = <0x180000 0x20000>; | |
193 | }; | |
21dd0ece | 194 | |
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195 | kernel@200000 { |
196 | label = "kernel"; | |
197 | reg = <0x200000 0x500000>; | |
198 | }; | |
21dd0ece | 199 | |
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200 | rootfs@800000 { |
201 | label = "rootfs"; | |
202 | reg = <0x800000 0x0f800000>; | |
203 | }; | |
21dd0ece | 204 | |
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205 | ovlfs@10000000 { |
206 | label = "ovlfs"; | |
207 | reg = <0x10000000 0x10000000>; | |
208 | }; | |
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209 | }; |
210 | }; | |
211 | ||
212 | &ssc0 { | |
213 | #sound-dai-cells = <0>; | |
214 | ||
215 | status = "okay"; | |
216 | }; | |
217 | ||
218 | &i2c0 { | |
219 | status = "okay"; | |
220 | ||
221 | jc42@18 { | |
222 | compatible = "nxp,se97b", "jedec,jc-42.4-temp"; | |
223 | reg = <0x18>; | |
bc53e3aa | 224 | smbus-timeout-disable; |
21dd0ece PR |
225 | }; |
226 | ||
227 | dpot: mcp4651-104@28 { | |
228 | compatible = "microchip,mcp4651-104"; | |
229 | reg = <0x28>; | |
230 | #io-channel-cells = <1>; | |
231 | }; | |
232 | ||
233 | pcm5142: pcm5142@4c { | |
234 | compatible = "ti,pcm5142"; | |
235 | ||
236 | reg = <0x4c>; | |
237 | ||
238 | AVDD-supply = <®_3v3>; | |
239 | DVDD-supply = <®_3v3>; | |
240 | CPVDD-supply = <®_3v3>; | |
241 | ||
242 | clocks = <&sck>; | |
243 | ||
244 | pll-in = <3>; | |
245 | pll-out = <6>; | |
246 | }; | |
247 | ||
248 | eeprom@50 { | |
43c3a448 | 249 | compatible = "nxp,24c02", "atmel,24c02"; |
21dd0ece PR |
250 | reg = <0x50>; |
251 | pagesize = <16>; | |
252 | }; | |
253 | }; | |
254 | ||
255 | &usart0 { | |
256 | status = "okay"; | |
257 | ||
258 | atmel,use-dma-rx; | |
259 | }; | |
260 | ||
261 | &pwm0 { | |
262 | status = "okay"; | |
263 | ||
264 | pinctrl-0 = <&pinctrl_pwm0_pwml2_1>; | |
265 | pinctrl-names = "default"; | |
266 | }; | |
267 | ||
268 | &macb1 { | |
269 | status = "okay"; | |
270 | ||
271 | phy-mode = "rgmii"; | |
272 | ||
273 | #address-cells = <1>; | |
274 | #size-cells = <0>; | |
275 | ||
276 | phy0: ethernet-phy@3 { | |
277 | reg = <3>; | |
278 | ||
279 | interrupt-parent = <&pioE>; | |
280 | interrupts = <31 IRQ_TYPE_EDGE_FALLING>; | |
281 | }; | |
282 | }; | |
283 | ||
284 | &usb0 { | |
285 | status = "okay"; | |
286 | ||
287 | pinctrl-names = "default"; | |
288 | pinctrl-0 = <&pinctrl_usba_vbus>; | |
289 | atmel,vbus-gpio = <&pioC 31 GPIO_ACTIVE_HIGH>; | |
290 | }; | |
291 | ||
292 | &usb1 { | |
293 | status = "okay"; | |
294 | ||
295 | num-ports = <1>; | |
296 | atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>; | |
297 | atmel,oc-gpio = <&pioC 15 GPIO_ACTIVE_LOW>; | |
298 | }; | |
299 | ||
300 | &usb2 { | |
301 | status = "okay"; | |
302 | }; | |
303 | ||
304 | &dbgu { | |
305 | status = "okay"; | |
306 | ||
307 | dmas = <0>, <0>; /* Do not use DMA for dbgu */ | |
308 | }; |