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467f1cf5 NF |
1 | /* |
2 | * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC | |
3 | * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, | |
4 | * AT91SAM9X25, AT91SAM9X35 SoC | |
5 | * | |
6 | * Copyright (C) 2012 Atmel, | |
7 | * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> | |
8 | * | |
9 | * Licensed under GPLv2 or later. | |
10 | */ | |
11 | ||
12 | /include/ "skeleton.dtsi" | |
13 | ||
14 | / { | |
15 | model = "Atmel AT91SAM9x5 family SoC"; | |
16 | compatible = "atmel,at91sam9x5"; | |
17 | interrupt-parent = <&aic>; | |
18 | ||
19 | aliases { | |
20 | serial0 = &dbgu; | |
21 | serial1 = &usart0; | |
22 | serial2 = &usart1; | |
23 | serial3 = &usart2; | |
24 | gpio0 = &pioA; | |
25 | gpio1 = &pioB; | |
26 | gpio2 = &pioC; | |
27 | gpio3 = &pioD; | |
28 | tcb0 = &tcb0; | |
29 | tcb1 = &tcb1; | |
05dcd361 LD |
30 | i2c0 = &i2c0; |
31 | i2c1 = &i2c1; | |
32 | i2c2 = &i2c2; | |
099343c6 | 33 | ssc0 = &ssc0; |
467f1cf5 NF |
34 | }; |
35 | cpus { | |
36 | cpu@0 { | |
37 | compatible = "arm,arm926ejs"; | |
38 | }; | |
39 | }; | |
40 | ||
dcce6ce8 | 41 | memory { |
467f1cf5 NF |
42 | reg = <0x20000000 0x10000000>; |
43 | }; | |
44 | ||
45 | ahb { | |
46 | compatible = "simple-bus"; | |
47 | #address-cells = <1>; | |
48 | #size-cells = <1>; | |
49 | ranges; | |
50 | ||
51 | apb { | |
52 | compatible = "simple-bus"; | |
53 | #address-cells = <1>; | |
54 | #size-cells = <1>; | |
55 | ranges; | |
56 | ||
57 | aic: interrupt-controller@fffff000 { | |
f8a073ee | 58 | #interrupt-cells = <3>; |
467f1cf5 NF |
59 | compatible = "atmel,at91rm9200-aic"; |
60 | interrupt-controller; | |
467f1cf5 | 61 | reg = <0xfffff000 0x200>; |
c6573943 | 62 | atmel,external-irqs = <31>; |
467f1cf5 NF |
63 | }; |
64 | ||
a7776ec6 JCPV |
65 | ramc0: ramc@ffffe800 { |
66 | compatible = "atmel,at91sam9g45-ddramc"; | |
67 | reg = <0xffffe800 0x200>; | |
68 | }; | |
69 | ||
eb5e76ff JCPV |
70 | pmc: pmc@fffffc00 { |
71 | compatible = "atmel,at91rm9200-pmc"; | |
72 | reg = <0xfffffc00 0x100>; | |
73 | }; | |
74 | ||
c8082d34 JCPV |
75 | rstc@fffffe00 { |
76 | compatible = "atmel,at91sam9g45-rstc"; | |
77 | reg = <0xfffffe00 0x10>; | |
78 | }; | |
79 | ||
82015c4e JCPV |
80 | shdwc@fffffe10 { |
81 | compatible = "atmel,at91sam9x5-shdwc"; | |
82 | reg = <0xfffffe10 0x10>; | |
83 | }; | |
84 | ||
467f1cf5 NF |
85 | pit: timer@fffffe30 { |
86 | compatible = "atmel,at91sam9260-pit"; | |
87 | reg = <0xfffffe30 0xf>; | |
f8a073ee | 88 | interrupts = <1 4 7>; |
467f1cf5 NF |
89 | }; |
90 | ||
099343c6 BS |
91 | ssc0: ssc@f0010000 { |
92 | compatible = "atmel,at91sam9g45-ssc"; | |
93 | reg = <0xf0010000 0x4000>; | |
94 | interrupts = <28 4 5>; | |
315656bc | 95 | status = "disabled"; |
099343c6 BS |
96 | }; |
97 | ||
467f1cf5 NF |
98 | tcb0: timer@f8008000 { |
99 | compatible = "atmel,at91sam9x5-tcb"; | |
100 | reg = <0xf8008000 0x100>; | |
f8a073ee | 101 | interrupts = <17 4 0>; |
467f1cf5 NF |
102 | }; |
103 | ||
104 | tcb1: timer@f800c000 { | |
105 | compatible = "atmel,at91sam9x5-tcb"; | |
106 | reg = <0xf800c000 0x100>; | |
f8a073ee | 107 | interrupts = <17 4 0>; |
467f1cf5 NF |
108 | }; |
109 | ||
110 | dma0: dma-controller@ffffec00 { | |
111 | compatible = "atmel,at91sam9g45-dma"; | |
112 | reg = <0xffffec00 0x200>; | |
f8a073ee | 113 | interrupts = <20 4 0>; |
467f1cf5 NF |
114 | }; |
115 | ||
116 | dma1: dma-controller@ffffee00 { | |
117 | compatible = "atmel,at91sam9g45-dma"; | |
118 | reg = <0xffffee00 0x200>; | |
f8a073ee | 119 | interrupts = <21 4 0>; |
467f1cf5 NF |
120 | }; |
121 | ||
ec6754a7 | 122 | pinctrl@fffff400 { |
e4541ff2 JCPV |
123 | #address-cells = <1>; |
124 | #size-cells = <1>; | |
5314ec8e | 125 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; |
e4541ff2 JCPV |
126 | ranges = <0xfffff400 0xfffff400 0x800>; |
127 | ||
5314ec8e | 128 | /* shared pinctrl settings */ |
ec6754a7 JCPV |
129 | dbgu { |
130 | pinctrl_dbgu: dbgu-0 { | |
131 | atmel,pins = | |
132 | <0 9 0x1 0x0 /* PA9 periph A */ | |
133 | 0 10 0x1 0x1>; /* PA10 periph A with pullup */ | |
134 | }; | |
135 | }; | |
136 | ||
9e3129e9 JCPV |
137 | usart0 { |
138 | pinctrl_usart0: usart0-0 { | |
ec6754a7 JCPV |
139 | atmel,pins = |
140 | <0 0 0x1 0x1 /* PA0 periph A with pullup */ | |
141 | 0 1 0x1 0x0>; /* PA1 periph A */ | |
142 | }; | |
143 | ||
c58c0c5a | 144 | pinctrl_usart0_rts: usart0_rts-0 { |
ec6754a7 | 145 | atmel,pins = |
c58c0c5a JCPV |
146 | <0 2 0x1 0x0>; /* PA2 periph A */ |
147 | }; | |
148 | ||
149 | pinctrl_usart0_cts: usart0_cts-0 { | |
150 | atmel,pins = | |
151 | <0 3 0x1 0x0>; /* PA3 periph A */ | |
ec6754a7 JCPV |
152 | }; |
153 | }; | |
154 | ||
9e3129e9 JCPV |
155 | usart1 { |
156 | pinctrl_usart1: usart1-0 { | |
ec6754a7 JCPV |
157 | atmel,pins = |
158 | <0 5 0x1 0x1 /* PA5 periph A with pullup */ | |
159 | 0 6 0x1 0x0>; /* PA6 periph A */ | |
160 | }; | |
161 | ||
c58c0c5a JCPV |
162 | pinctrl_usart1_rts: usart1_rts-0 { |
163 | atmel,pins = | |
164 | <3 27 0x3 0x0>; /* PC27 periph C */ | |
165 | }; | |
166 | ||
167 | pinctrl_usart1_cts: usart1_cts-0 { | |
ec6754a7 | 168 | atmel,pins = |
c58c0c5a | 169 | <3 28 0x3 0x0>; /* PC28 periph C */ |
ec6754a7 JCPV |
170 | }; |
171 | }; | |
172 | ||
9e3129e9 JCPV |
173 | usart2 { |
174 | pinctrl_usart2: usart2-0 { | |
ec6754a7 JCPV |
175 | atmel,pins = |
176 | <0 7 0x1 0x1 /* PA7 periph A with pullup */ | |
177 | 0 8 0x1 0x0>; /* PA8 periph A */ | |
178 | }; | |
179 | ||
c58c0c5a | 180 | pinctrl_uart2_rts: uart2_rts-0 { |
ec6754a7 | 181 | atmel,pins = |
c58c0c5a JCPV |
182 | <0 0 0x2 0x0>; /* PB0 periph B */ |
183 | }; | |
184 | ||
185 | pinctrl_uart2_cts: uart2_cts-0 { | |
186 | atmel,pins = | |
187 | <0 1 0x2 0x0>; /* PB1 periph B */ | |
ec6754a7 JCPV |
188 | }; |
189 | }; | |
190 | ||
9e3129e9 JCPV |
191 | usart3 { |
192 | pinctrl_uart3: usart3-0 { | |
ec6754a7 JCPV |
193 | atmel,pins = |
194 | <3 23 0x2 0x1 /* PC22 periph B with pullup */ | |
195 | 3 23 0x2 0x0>; /* PC23 periph B */ | |
196 | }; | |
197 | ||
c58c0c5a JCPV |
198 | pinctrl_usart3_rts: usart3_rts-0 { |
199 | atmel,pins = | |
200 | <3 24 0x2 0x0>; /* PC24 periph B */ | |
201 | }; | |
202 | ||
203 | pinctrl_usart3_cts: usart3_cts-0 { | |
ec6754a7 | 204 | atmel,pins = |
c58c0c5a | 205 | <3 25 0x2 0x0>; /* PC25 periph B */ |
ec6754a7 JCPV |
206 | }; |
207 | }; | |
208 | ||
9e3129e9 JCPV |
209 | uart0 { |
210 | pinctrl_uart0: uart0-0 { | |
ec6754a7 JCPV |
211 | atmel,pins = |
212 | <3 8 0x3 0x0 /* PC8 periph C */ | |
213 | 3 9 0x3 0x1>; /* PC9 periph C with pullup */ | |
214 | }; | |
215 | }; | |
216 | ||
9e3129e9 JCPV |
217 | uart1 { |
218 | pinctrl_uart1: uart1-0 { | |
ec6754a7 JCPV |
219 | atmel,pins = |
220 | <3 16 0x3 0x0 /* PC16 periph C */ | |
221 | 3 17 0x3 0x1>; /* PC17 periph C with pullup */ | |
222 | }; | |
223 | }; | |
5314ec8e | 224 | |
7a38d450 JCPV |
225 | nand { |
226 | pinctrl_nand: nand-0 { | |
227 | atmel,pins = | |
228 | <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */ | |
229 | 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */ | |
230 | }; | |
231 | }; | |
232 | ||
d9b4fe83 JCPV |
233 | macb0 { |
234 | pinctrl_macb0_rmii: macb0_rmii-0 { | |
235 | atmel,pins = | |
236 | <1 0 0x1 0x0 /* PB0 periph A */ | |
237 | 1 1 0x1 0x0 /* PB1 periph A */ | |
238 | 1 2 0x1 0x0 /* PB2 periph A */ | |
239 | 1 3 0x1 0x0 /* PB3 periph A */ | |
240 | 1 4 0x1 0x0 /* PB4 periph A */ | |
241 | 1 5 0x1 0x0 /* PB5 periph A */ | |
242 | 1 6 0x1 0x0 /* PB6 periph A */ | |
243 | 1 7 0x1 0x0 /* PB7 periph A */ | |
244 | 1 9 0x1 0x0 /* PB9 periph A */ | |
245 | 1 10 0x1 0x0>; /* PB10 periph A */ | |
246 | }; | |
247 | ||
248 | pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 { | |
249 | atmel,pins = | |
250 | <1 8 0x1 0x0 /* PA8 periph A */ | |
251 | 1 11 0x1 0x0 /* PA11 periph A */ | |
252 | 1 12 0x1 0x0 /* PA12 periph A */ | |
253 | 1 13 0x1 0x0 /* PA13 periph A */ | |
254 | 1 14 0x1 0x0 /* PA14 periph A */ | |
255 | 1 15 0x1 0x0 /* PA15 periph A */ | |
256 | 1 16 0x1 0x0 /* PA16 periph A */ | |
257 | 1 17 0x1 0x0>; /* PA17 periph A */ | |
258 | }; | |
259 | }; | |
260 | ||
d4fe9ac7 JCPV |
261 | mmc0 { |
262 | pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 { | |
263 | atmel,pins = | |
264 | <0 17 0x1 0x0 /* PA17 periph A */ | |
265 | 0 16 0x1 0x1 /* PA16 periph A with pullup */ | |
266 | 0 15 0x1 0x1>; /* PA15 periph A with pullup */ | |
267 | }; | |
268 | ||
269 | pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { | |
270 | atmel,pins = | |
271 | <0 18 0x1 0x1 /* PA18 periph A with pullup */ | |
272 | 0 19 0x1 0x1 /* PA19 periph A with pullup */ | |
273 | 0 20 0x1 0x1>; /* PA20 periph A with pullup */ | |
274 | }; | |
275 | }; | |
276 | ||
277 | mmc1 { | |
278 | pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 { | |
279 | atmel,pins = | |
280 | <0 13 0x2 0x0 /* PA13 periph B */ | |
281 | 0 12 0x2 0x1 /* PA12 periph B with pullup */ | |
282 | 0 11 0x2 0x1>; /* PA11 periph B with pullup */ | |
283 | }; | |
284 | ||
285 | pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 { | |
286 | atmel,pins = | |
287 | <0 2 0x2 0x1 /* PA2 periph B with pullup */ | |
288 | 0 3 0x2 0x1 /* PA3 periph B with pullup */ | |
289 | 0 4 0x2 0x1>; /* PA4 periph B with pullup */ | |
290 | }; | |
291 | }; | |
292 | ||
e4541ff2 JCPV |
293 | pioA: gpio@fffff400 { |
294 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
295 | reg = <0xfffff400 0x200>; | |
296 | interrupts = <2 4 1>; | |
297 | #gpio-cells = <2>; | |
298 | gpio-controller; | |
299 | interrupt-controller; | |
300 | #interrupt-cells = <2>; | |
301 | }; | |
302 | ||
303 | pioB: gpio@fffff600 { | |
304 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
305 | reg = <0xfffff600 0x200>; | |
306 | interrupts = <2 4 1>; | |
307 | #gpio-cells = <2>; | |
308 | gpio-controller; | |
fc33ff43 | 309 | #gpio-lines = <19>; |
e4541ff2 JCPV |
310 | interrupt-controller; |
311 | #interrupt-cells = <2>; | |
312 | }; | |
313 | ||
314 | pioC: gpio@fffff800 { | |
315 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
316 | reg = <0xfffff800 0x200>; | |
317 | interrupts = <3 4 1>; | |
318 | #gpio-cells = <2>; | |
319 | gpio-controller; | |
320 | interrupt-controller; | |
321 | #interrupt-cells = <2>; | |
322 | }; | |
323 | ||
324 | pioD: gpio@fffffa00 { | |
325 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
326 | reg = <0xfffffa00 0x200>; | |
327 | interrupts = <3 4 1>; | |
328 | #gpio-cells = <2>; | |
329 | gpio-controller; | |
fc33ff43 | 330 | #gpio-lines = <22>; |
e4541ff2 JCPV |
331 | interrupt-controller; |
332 | #interrupt-cells = <2>; | |
333 | }; | |
467f1cf5 NF |
334 | }; |
335 | ||
9873137a LD |
336 | mmc0: mmc@f0008000 { |
337 | compatible = "atmel,hsmci"; | |
338 | reg = <0xf0008000 0x600>; | |
339 | interrupts = <12 4 0>; | |
340 | #address-cells = <1>; | |
341 | #size-cells = <0>; | |
342 | status = "disabled"; | |
343 | }; | |
344 | ||
345 | mmc1: mmc@f000c000 { | |
346 | compatible = "atmel,hsmci"; | |
347 | reg = <0xf000c000 0x600>; | |
348 | interrupts = <26 4 0>; | |
349 | #address-cells = <1>; | |
350 | #size-cells = <0>; | |
351 | status = "disabled"; | |
352 | }; | |
353 | ||
467f1cf5 NF |
354 | dbgu: serial@fffff200 { |
355 | compatible = "atmel,at91sam9260-usart"; | |
356 | reg = <0xfffff200 0x200>; | |
f8a073ee | 357 | interrupts = <1 4 7>; |
ec6754a7 JCPV |
358 | pinctrl-names = "default"; |
359 | pinctrl-0 = <&pinctrl_dbgu>; | |
467f1cf5 NF |
360 | status = "disabled"; |
361 | }; | |
362 | ||
363 | usart0: serial@f801c000 { | |
364 | compatible = "atmel,at91sam9260-usart"; | |
365 | reg = <0xf801c000 0x200>; | |
f8a073ee | 366 | interrupts = <5 4 5>; |
467f1cf5 NF |
367 | atmel,use-dma-rx; |
368 | atmel,use-dma-tx; | |
ec6754a7 | 369 | pinctrl-names = "default"; |
9e3129e9 | 370 | pinctrl-0 = <&pinctrl_usart0>; |
467f1cf5 NF |
371 | status = "disabled"; |
372 | }; | |
373 | ||
374 | usart1: serial@f8020000 { | |
375 | compatible = "atmel,at91sam9260-usart"; | |
376 | reg = <0xf8020000 0x200>; | |
f8a073ee | 377 | interrupts = <6 4 5>; |
467f1cf5 NF |
378 | atmel,use-dma-rx; |
379 | atmel,use-dma-tx; | |
ec6754a7 | 380 | pinctrl-names = "default"; |
9e3129e9 | 381 | pinctrl-0 = <&pinctrl_usart1>; |
467f1cf5 NF |
382 | status = "disabled"; |
383 | }; | |
384 | ||
385 | usart2: serial@f8024000 { | |
386 | compatible = "atmel,at91sam9260-usart"; | |
387 | reg = <0xf8024000 0x200>; | |
f8a073ee | 388 | interrupts = <7 4 5>; |
467f1cf5 NF |
389 | atmel,use-dma-rx; |
390 | atmel,use-dma-tx; | |
ec6754a7 | 391 | pinctrl-names = "default"; |
9e3129e9 | 392 | pinctrl-0 = <&pinctrl_usart2>; |
467f1cf5 NF |
393 | status = "disabled"; |
394 | }; | |
395 | ||
396 | macb0: ethernet@f802c000 { | |
397 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | |
398 | reg = <0xf802c000 0x100>; | |
f8a073ee | 399 | interrupts = <24 4 3>; |
d9b4fe83 JCPV |
400 | pinctrl-names = "default"; |
401 | pinctrl-0 = <&pinctrl_macb0_rmii>; | |
467f1cf5 NF |
402 | status = "disabled"; |
403 | }; | |
404 | ||
405 | macb1: ethernet@f8030000 { | |
406 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | |
407 | reg = <0xf8030000 0x100>; | |
f8a073ee | 408 | interrupts = <27 4 3>; |
467f1cf5 NF |
409 | status = "disabled"; |
410 | }; | |
d029f371 | 411 | |
05dcd361 LD |
412 | i2c0: i2c@f8010000 { |
413 | compatible = "atmel,at91sam9x5-i2c"; | |
414 | reg = <0xf8010000 0x100>; | |
415 | interrupts = <9 4 6>; | |
416 | #address-cells = <1>; | |
417 | #size-cells = <0>; | |
418 | status = "disabled"; | |
419 | }; | |
420 | ||
421 | i2c1: i2c@f8014000 { | |
422 | compatible = "atmel,at91sam9x5-i2c"; | |
423 | reg = <0xf8014000 0x100>; | |
424 | interrupts = <10 4 6>; | |
425 | #address-cells = <1>; | |
426 | #size-cells = <0>; | |
427 | status = "disabled"; | |
428 | }; | |
429 | ||
430 | i2c2: i2c@f8018000 { | |
431 | compatible = "atmel,at91sam9x5-i2c"; | |
432 | reg = <0xf8018000 0x100>; | |
433 | interrupts = <11 4 6>; | |
434 | #address-cells = <1>; | |
435 | #size-cells = <0>; | |
436 | status = "disabled"; | |
437 | }; | |
438 | ||
d029f371 MR |
439 | adc0: adc@f804c000 { |
440 | compatible = "atmel,at91sam9260-adc"; | |
441 | reg = <0xf804c000 0x100>; | |
f8a073ee | 442 | interrupts = <19 4 0>; |
d029f371 MR |
443 | atmel,adc-use-external; |
444 | atmel,adc-channels-used = <0xffff>; | |
445 | atmel,adc-vref = <3300>; | |
446 | atmel,adc-num-channels = <12>; | |
447 | atmel,adc-startup-time = <40>; | |
448 | atmel,adc-channel-base = <0x50>; | |
449 | atmel,adc-drdy-mask = <0x1000000>; | |
450 | atmel,adc-status-register = <0x30>; | |
451 | atmel,adc-trigger-register = <0xc0>; | |
452 | ||
453 | trigger@0 { | |
454 | trigger-name = "external-rising"; | |
455 | trigger-value = <0x1>; | |
456 | trigger-external; | |
457 | }; | |
458 | ||
459 | trigger@1 { | |
460 | trigger-name = "external-falling"; | |
461 | trigger-value = <0x2>; | |
462 | trigger-external; | |
463 | }; | |
464 | ||
465 | trigger@2 { | |
466 | trigger-name = "external-any"; | |
467 | trigger-value = <0x3>; | |
468 | trigger-external; | |
469 | }; | |
470 | ||
471 | trigger@3 { | |
472 | trigger-name = "continuous"; | |
473 | trigger-value = <0x6>; | |
474 | }; | |
475 | }; | |
467f1cf5 | 476 | }; |
86a89f4f JCPV |
477 | |
478 | nand0: nand@40000000 { | |
479 | compatible = "atmel,at91rm9200-nand"; | |
480 | #address-cells = <1>; | |
481 | #size-cells = <1>; | |
482 | reg = <0x40000000 0x10000000 | |
483 | >; | |
484 | atmel,nand-addr-offset = <21>; | |
485 | atmel,nand-cmd-offset = <22>; | |
7a38d450 JCPV |
486 | pinctrl-names = "default"; |
487 | pinctrl-0 = <&pinctrl_nand>; | |
4352808c NF |
488 | gpios = <&pioD 5 0 |
489 | &pioD 4 0 | |
86a89f4f JCPV |
490 | 0 |
491 | >; | |
492 | status = "disabled"; | |
493 | }; | |
6a062459 JCPV |
494 | |
495 | usb0: ohci@00600000 { | |
496 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
497 | reg = <0x00600000 0x100000>; | |
f8a073ee | 498 | interrupts = <22 4 2>; |
6a062459 JCPV |
499 | status = "disabled"; |
500 | }; | |
62c5553a JCPV |
501 | |
502 | usb1: ehci@00700000 { | |
503 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
504 | reg = <0x00700000 0x100000>; | |
f8a073ee | 505 | interrupts = <22 4 2>; |
62c5553a JCPV |
506 | status = "disabled"; |
507 | }; | |
467f1cf5 | 508 | }; |
10f71c28 JCPV |
509 | |
510 | i2c@0 { | |
511 | compatible = "i2c-gpio"; | |
512 | gpios = <&pioA 30 0 /* sda */ | |
513 | &pioA 31 0 /* scl */ | |
514 | >; | |
515 | i2c-gpio,sda-open-drain; | |
516 | i2c-gpio,scl-open-drain; | |
517 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
518 | #address-cells = <1>; | |
519 | #size-cells = <0>; | |
520 | status = "disabled"; | |
521 | }; | |
522 | ||
523 | i2c@1 { | |
524 | compatible = "i2c-gpio"; | |
525 | gpios = <&pioC 0 0 /* sda */ | |
526 | &pioC 1 0 /* scl */ | |
527 | >; | |
528 | i2c-gpio,sda-open-drain; | |
529 | i2c-gpio,scl-open-drain; | |
530 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
531 | #address-cells = <1>; | |
532 | #size-cells = <0>; | |
533 | status = "disabled"; | |
534 | }; | |
535 | ||
536 | i2c@2 { | |
537 | compatible = "i2c-gpio"; | |
538 | gpios = <&pioB 4 0 /* sda */ | |
539 | &pioB 5 0 /* scl */ | |
540 | >; | |
541 | i2c-gpio,sda-open-drain; | |
542 | i2c-gpio,scl-open-drain; | |
543 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ | |
544 | #address-cells = <1>; | |
545 | #size-cells = <0>; | |
546 | status = "disabled"; | |
547 | }; | |
467f1cf5 | 548 | }; |