[mirror_ubuntu-bionic-kernel.git] / arch / arm / boot / dts / bcm-cygnus.dtsi

/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/bcm-cygnus.h>

#include "skeleton.dtsi"

/ {
	compatible = "brcm,cygnus";
	model = "Broadcom Cygnus SoC";
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
		};
	};

	/include/ "bcm-cygnus-clock.dtsi"

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	};

	core {
		compatible = "simple-bus";
		ranges = <0x00000000 0x19000000 0x1000000>;
		#address-cells = <1>;
		#size-cells = <1>;

		timer@20200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x20200 0x100>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
		};

		gic: interrupt-controller@21000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x21000 0x1000>,
			      <0x20100 0x100>;
		};

		L2: l2-cache {
			compatible = "arm,pl310-cache";
			reg = <0x22000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};
	};

	axi {
		compatible = "simple-bus";
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;

		otp: otp@0301c800 {
			compatible = "brcm,ocotp";
			reg = <0x0301c800 0x2c>;
			brcm,ocotp-size = <2048>;
			status = "disabled";
		};

		pcie_phy: phy@0301d0a0 {
			compatible = "brcm,cygnus-pcie-phy";
			reg = <0x0301d0a0 0x14>;
			#address-cells = <1>;
			#size-cells = <0>;

			pcie0_phy: phy@0 {
				reg = <0>;
				#phy-cells = <0>;
			};

			pcie1_phy: phy@1 {
				reg = <1>;
				#phy-cells = <0>;
			};
		};

		pinctrl: pinctrl@0301d0c8 {
			compatible = "brcm,cygnus-pinmux";
			reg = <0x0301d0c8 0x30>,
			      <0x0301d24c 0x2c>;

			spi_0: spi_0 {
				function = "spi0";
				groups = "spi0_grp";
			};

			spi_1: spi_1 {
				function = "spi1";
				groups = "spi1_grp";
			};

			spi_2: spi_2 {
				function = "spi2";
				groups = "spi2_grp";
			};
		};

		mailbox: mailbox@03024024 {
			compatible = "brcm,iproc-mailbox";
			reg = <0x03024024 0x40>;
			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			#interrupt-cells = <1>;
			interrupt-controller;
			#mbox-cells = <1>;
		};

		gpio_crmu: gpio@03024800 {
			compatible = "brcm,cygnus-crmu-gpio";
			reg = <0x03024800 0x50>,
			      <0x03024008 0x18>;
			ngpios = <6>;
			#gpio-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupt-parent = <&mailbox>;
			interrupts = <0>;
		};

		mdio: mdio@18002000 {
			compatible = "brcm,iproc-mdio";
			reg = <0x18002000 0x8>;
			#size-cells = <1>;
			#address-cells = <0>;
			status = "disabled";

			gphy0: ethernet-phy@0 {
				reg = <0>;
			};

			gphy1: ethernet-phy@1 {
				reg = <1>;
			};
		};

		switch: switch@18007000 {
			compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab";
			reg = <0x18007000 0x1000>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					phy-handle = <&gphy0>;
					phy-mode = "rgmii";
				};

				port@1 {
					reg = <1>;
					phy-handle = <&gphy1>;
					phy-mode = "rgmii";
				};

				port@8 {
					reg = <8>;
					label = "cpu";
					ethernet = <&eth0>;
					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};
			};
		};

		i2c0: i2c@18008000 {
			compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
			reg = <0x18008000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		wdt0: wdt@18009000 {
			compatible = "arm,sp805" , "arm,primecell";
			reg = <0x18009000 0x1000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&axi81_clk>;
			clock-names = "apb_pclk";
		};

		gpio_ccm: gpio@1800a000 {
			compatible = "brcm,cygnus-ccm-gpio";
			reg = <0x1800a000 0x50>,
			      <0x0301d164 0x20>;
			ngpios = <24>;
			#gpio-cells = <2>;
			gpio-controller;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
		};

		i2c1: i2c@1800b000 {
			compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
			reg = <0x1800b000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		pcie0: pcie@18012000 {
			compatible = "brcm,iproc-pcie";
			reg = <0x18012000 0x1000>;

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;

			linux,pci-domain = <0>;

			bus-range = <0x00 0xff>;

			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges = <0x81000000 0 0	  0x28000000 0 0x00010000
				  0x82000000 0 0x20000000 0x20000000 0 0x04000000>;

			phys = <&pcie0_phy>;
			phy-names = "pcie-phy";

			status = "disabled";

			msi-parent = <&msi0>;
			msi0: msi-controller {
				compatible = "brcm,iproc-msi";
				msi-controller;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
					     <GIC_SPI 97 IRQ_TYPE_NONE>,
					     <GIC_SPI 98 IRQ_TYPE_NONE>,
					     <GIC_SPI 99 IRQ_TYPE_NONE>;
			};
		};

		pcie1: pcie@18013000 {
			compatible = "brcm,iproc-pcie";
			reg = <0x18013000 0x1000>;

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;

			linux,pci-domain = <1>;

			bus-range = <0x00 0xff>;

			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			ranges = <0x81000000 0 0	  0x48000000 0 0x00010000
				  0x82000000 0 0x40000000 0x40000000 0 0x04000000>;

			phys = <&pcie1_phy>;
			phy-names = "pcie-phy";

			status = "disabled";

			msi-parent = <&msi1>;
			msi1: msi-controller {
				compatible = "brcm,iproc-msi";
				msi-controller;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>,
					     <GIC_SPI 103 IRQ_TYPE_NONE>,
					     <GIC_SPI 104 IRQ_TYPE_NONE>,
					     <GIC_SPI 105 IRQ_TYPE_NONE>;
			};
		};

		dma0: dma@18018000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x18018000 0x1000>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb_clk>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
		};

		uart0: serial@18020000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x18020000 0x100>;
			reg-shift = <2>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&axi81_clk>;
			clock-frequency = <100000000>;
			status = "disabled";
		};

		uart1: serial@18021000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x18021000 0x100>;
			reg-shift = <2>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&axi81_clk>;
			clock-frequency = <100000000>;
			status = "disabled";
		};

		uart2: serial@18022000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x18022000 0x100>;
			reg-shift = <2>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&axi81_clk>;
			clock-frequency = <100000000>;
			status = "disabled";
		};

		uart3: serial@18023000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x18023000 0x100>;
			reg-shift = <2>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&axi81_clk>;
			clock-frequency = <100000000>;
			status = "disabled";
		};

		spi0: spi@18028000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x18028000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&spi_0>;
			clocks = <&axi81_clk>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		spi1: spi@18029000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x18029000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&spi_1>;
			clocks = <&axi81_clk>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		spi2: spi@1802a000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x1802a000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-0 = <&spi_2>;
			clocks = <&axi81_clk>;
			clock-names = "apb_pclk";
			status = "disabled";
		};

		sdhci0: sdhci@18041000 {
			compatible = "brcm,sdhci-iproc-cygnus";
			reg = <0x18041000 0x100>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
			bus-width = <4>;
			sdhci,auto-cmd12;
			status = "disabled";
		};

		eth0: ethernet@18042000 {
			compatible = "brcm,amac";
			reg = <0x18042000 0x1000>,
			      <0x18110000 0x1000>;
			reg-names = "amac_base", "idm_base";
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci1: sdhci@18043000 {
			compatible = "brcm,sdhci-iproc-cygnus";
			reg = <0x18043000 0x100>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
			bus-width = <4>;
			sdhci,auto-cmd12;
			status = "disabled";
		};

		nand: nand@18046000 {
			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
			reg = <0x18046000 0x600>, <0xf8105408 0x600>,
			      <0x18046f00 0x20>;
			reg-names = "nand", "iproc-idm", "iproc-ext";
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;
			#size-cells = <0>;

			brcm,nand-has-wp;
		};

		ehci0: usb@18048000 {
			compatible = "generic-ehci";
			reg = <0x18048000 0x100>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		ohci0: usb@18048800 {
			compatible = "generic-ohci";
			reg = <0x18048800 0x100>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		v3d: v3d@180a2000 {
			compatible = "brcm,cygnus-v3d";
			reg = <0x180a2000 0x1000>;
			clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>;
			clock-names = "v3d_clk";
			interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		vc4: gpu {
			compatible = "brcm,cygnus-vc4";
		};

		gpio_asiu: gpio@180a5000 {
			compatible = "brcm,cygnus-asiu-gpio";
			reg = <0x180a5000 0x668>;
			ngpios = <146>;
			#gpio-cells = <2>;
			gpio-controller;

			interrupt-controller;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
			gpio-ranges = <&pinctrl 0 42 1>,
					<&pinctrl 1 44 3>,
					<&pinctrl 4 48 1>,
					<&pinctrl 5 50 3>,
					<&pinctrl 8 126 1>,
					<&pinctrl 9 155 1>,
					<&pinctrl 10 152 1>,
					<&pinctrl 11 154 1>,
					<&pinctrl 12 153 1>,
					<&pinctrl 13 127 3>,
					<&pinctrl 16 140 1>,
					<&pinctrl 17 145 7>,
					<&pinctrl 24 130 10>,
					<&pinctrl 34 141 4>,
					<&pinctrl 38 54 1>,
					<&pinctrl 39 56 3>,
					<&pinctrl 42 60 3>,
					<&pinctrl 45 64 3>,
					<&pinctrl 48 68 2>,
					<&pinctrl 50 84 6>,
					<&pinctrl 56 94 6>,
					<&pinctrl 62 72 1>,
					<&pinctrl 63 70 1>,
					<&pinctrl 64 80 1>,
					<&pinctrl 65 74 3>,
					<&pinctrl 68 78 1>,
					<&pinctrl 69 82 1>,
					<&pinctrl 70 156 17>,
					<&pinctrl 87 104 12>,
					<&pinctrl 99 102 2>,
					<&pinctrl 101 90 4>,
					<&pinctrl 105 116 6>,
					<&pinctrl 111 100 2>,
					<&pinctrl 113 122 4>,
					<&pinctrl 123 11 1>,
					<&pinctrl 124 38 4>,
					<&pinctrl 128 43 1>,
					<&pinctrl 129 47 1>,
					<&pinctrl 130 49 1>,
					<&pinctrl 131 53 1>,
					<&pinctrl 132 55 1>,
					<&pinctrl 133 59 1>,
					<&pinctrl 134 63 1>,
					<&pinctrl 135 67 1>,
					<&pinctrl 136 71 1>,
					<&pinctrl 137 73 1>,
					<&pinctrl 138 77 1>,
					<&pinctrl 139 79 1>,
					<&pinctrl 140 81 1>,
					<&pinctrl 141 83 1>,
					<&pinctrl 142 10 1>;
		};

		ts_adc_syscon: ts_adc_syscon@180a6000 {
			compatible = "brcm,iproc-ts-adc-syscon", "syscon";
			reg = <0x180a6000 0xc30>;
		};

		touchscreen: touchscreen@180a6000 {
			compatible = "brcm,iproc-touchscreen";
			#address-cells = <1>;
			#size-cells = <1>;
			ts_syscon = <&ts_adc_syscon>;
			clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
			clock-names = "tsc_clk";
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		adc: adc@180a6000 {
			compatible = "brcm,iproc-static-adc";
			#io-channel-cells = <1>;
			io-channel-ranges;
			adc-syscon = <&ts_adc_syscon>;
			clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
			clock-names = "tsc_clk";
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		keypad: keypad@180ac000 {
			compatible = "brcm,bcm-keypad";
			reg = <0x180ac000 0x14c>;
			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>;
			clock-names = "peri_clk";
			clock-frequency = <31250>;
			pull-up-enabled;
			col-debounce-filter-period = <0>;
			status-debounce-filter-period = <0>;
			row-output-enabled;
			status = "disabled";
		};
	};
};
Commit	Line	Data
c9ad7bc5 SB	1	/*
	2	* BSD LICENSE
	3	*
	4	* Copyright(c) 2014 Broadcom Corporation. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Broadcom Corporation nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
	34	#include <dt-bindings/interrupt-controller/irq.h>
35e372a3	35	#include <dt-bindings/clock/bcm-cygnus.h>
c9ad7bc5 SB	36
	37	#include "skeleton.dtsi"
	38
	39	/ {
	40	compatible = "brcm,cygnus";
	41	model = "Broadcom Cygnus SoC";
	42	interrupt-parent = <&gic>;
	43
	44	cpus {
	45	#address-cells = <1>;
	46	#size-cells = <0>;
	47
	48	cpu@0 {
	49	device_type = "cpu";
	50	compatible = "arm,cortex-a9";
	51	next-level-cache = <&L2>;
	52	reg = <0x0>;
	53	};
	54	};
	55
	56	/include/ "bcm-cygnus-clock.dtsi"
	57
0e50dc91 JU	58	pmu {
	59	compatible = "arm,cortex-a9-pmu";
	60	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	61	};
	62
ef5b812a RJ	63	core {
	64	compatible = "simple-bus";
	65	ranges = <0x00000000 0x19000000 0x1000000>;
	66	#address-cells = <1>;
	67	#size-cells = <1>;
	68
	69	timer@20200 {
	70	compatible = "arm,cortex-a9-global-timer";
	71	reg = <0x20200 0x100>;
	72	interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
	73	clocks = <&periph_clk>;
	74	};
	75
	76	gic: interrupt-controller@21000 {
	77	compatible = "arm,cortex-a9-gic";
	78	#interrupt-cells = <3>;
	79	#address-cells = <0>;
	80	interrupt-controller;
	81	reg = <0x21000 0x1000>,
	82	<0x20100 0x100>;
	83	};
	84
	85	L2: l2-cache {
	86	compatible = "arm,pl310-cache";
	87	reg = <0x22000 0x1000>;
	88	cache-unified;
	89	cache-level = <2>;
	90	};
	91	};
	92
0f0b21a8 RJ	93	axi {
	94	compatible = "simple-bus";
	95	ranges;
	96	#address-cells = <1>;
	97	#size-cells = <1>;
e6a4e5d5	98
7fa8b51b JR	99	otp: otp@0301c800 {
	100	compatible = "brcm,ocotp";
	101	reg = <0x0301c800 0x2c>;
	102	brcm,ocotp-size = <2048>;
	103	status = "disabled";
	104	};
	105
44a06fa4 RJ	106	pcie_phy: phy@0301d0a0 {
	107	compatible = "brcm,cygnus-pcie-phy";
	108	reg = <0x0301d0a0 0x14>;
	109	#address-cells = <1>;
	110	#size-cells = <0>;
	111
	112	pcie0_phy: phy@0 {
	113	reg = <0>;
	114	#phy-cells = <0>;
	115	};
	116
	117	pcie1_phy: phy@1 {
	118	reg = <1>;
	119	#phy-cells = <0>;
	120	};
	121	};
	122
b350e9dd	123	pinctrl: pinctrl@0301d0c8 {
0f0b21a8 RJ	124	compatible = "brcm,cygnus-pinmux";
	125	reg = <0x0301d0c8 0x30>,
	126	<0x0301d24c 0x2c>;
143d0d47 JR	127
	128	spi_0: spi_0 {
	129	function = "spi0";
	130	groups = "spi0_grp";
	131	};
	132
	133	spi_1: spi_1 {
	134	function = "spi1";
	135	groups = "spi1_grp";
	136	};
	137
	138	spi_2: spi_2 {
	139	function = "spi2";
	140	groups = "spi2_grp";
	141	};
0f0b21a8	142	};
5fa4b29c	143
77f923cb JR	144	mailbox: mailbox@03024024 {
	145	compatible = "brcm,iproc-mailbox";
	146	reg = <0x03024024 0x40>;
	147	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	148	#interrupt-cells = <1>;
	149	interrupt-controller;
	150	#mbox-cells = <1>;
	151	};
	152
0f0b21a8 RJ	153	gpio_crmu: gpio@03024800 {
	154	compatible = "brcm,cygnus-crmu-gpio";
	155	reg = <0x03024800 0x50>,
	156	<0x03024008 0x18>;
3ad8ff0e	157	ngpios = <6>;
0f0b21a8 RJ	158	#gpio-cells = <2>;
0f0b21a8 RJ	159	gpio-controller;
2c42d0f0 JR	160	interrupt-controller;
	161	interrupt-parent = <&mailbox>;
	162	interrupts = <0>;
0f0b21a8	163	};
5fa4b29c	164
40c26d3a EA	165	mdio: mdio@18002000 {
	166	compatible = "brcm,iproc-mdio";
	167	reg = <0x18002000 0x8>;
	168	#size-cells = <1>;
	169	#address-cells = <0>;
	170	status = "disabled";
	171
	172	gphy0: ethernet-phy@0 {
	173	reg = <0>;
	174	};
	175
	176	gphy1: ethernet-phy@1 {
	177	reg = <1>;
	178	};
	179	};
	180
	181	switch: switch@18007000 {
	182	compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab";
	183	reg = <0x18007000 0x1000>;
	184	status = "disabled";
	185
	186	ports {
	187	#address-cells = <1>;
	188	#size-cells = <0>;
	189
	190	port@0 {
	191	reg = <0>;
	192	phy-handle = <&gphy0>;
	193	phy-mode = "rgmii";
	194	};
	195
	196	port@1 {
	197	reg = <1>;
	198	phy-handle = <&gphy1>;
	199	phy-mode = "rgmii";
	200	};
	201
	202	port@8 {
	203	reg = <8>;
	204	label = "cpu";
	205	ethernet = <&eth0>;
	206	fixed-link {
	207	speed = <1000>;
	208	full-duplex;
	209	};
	210	};
	211	};
	212	};
	213
9c5101f7 RJ	214	i2c0: i2c@18008000 {
	215	compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
	216	reg = <0x18008000 0x100>;
	217	#address-cells = <1>;
	218	#size-cells = <0>;
	219	interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
	220	clock-frequency = <100000>;
	221	status = "disabled";
0f0b21a8	222	};
c9ad7bc5	223
0f0b21a8 RJ	224	wdt0: wdt@18009000 {
	225	compatible = "arm,sp805" , "arm,primecell";
	226	reg = <0x18009000 0x1000>;
	227	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	228	clocks = <&axi81_clk>;
	229	clock-names = "apb_pclk";
c9ad7bc5	230	};
c9ad7bc5	231
9c5101f7 RJ	232	gpio_ccm: gpio@1800a000 {
	233	compatible = "brcm,cygnus-ccm-gpio";
	234	reg = <0x1800a000 0x50>,
	235	<0x0301d164 0x20>;
3ad8ff0e	236	ngpios = <24>;
9c5101f7 RJ	237	#gpio-cells = <2>;
	238	gpio-controller;
	239	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	240	interrupt-controller;
0f0b21a8	241	};
b51c05a3	242
0f0b21a8 RJ	243	i2c1: i2c@1800b000 {
	244	compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
	245	reg = <0x1800b000 0x100>;
	246	#address-cells = <1>;
	247	#size-cells = <0>;
	248	interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
	249	clock-frequency = <100000>;
	250	status = "disabled";
	251	};
b51c05a3	252
0f0b21a8 RJ	253	pcie0: pcie@18012000 {
	254	compatible = "brcm,iproc-pcie";
	255	reg = <0x18012000 0x1000>;
cd590b50	256
0f0b21a8 RJ	257	#interrupt-cells = <1>;
	258	interrupt-map-mask = <0 0 0 0>;
	259	interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
cd590b50	260
0f0b21a8	261	linux,pci-domain = <0>;
cd590b50	262
0f0b21a8	263	bus-range = <0x00 0xff>;
cd590b50	264
0f0b21a8 RJ	265	#address-cells = <3>;
	266	#size-cells = <2>;
	267	device_type = "pci";
	268	ranges = <0x81000000 0 0 0x28000000 0 0x00010000
	269	0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
cd590b50	270
44a06fa4 RJ	271	phys = <&pcie0_phy>;
	272	phy-names = "pcie-phy";
	273
0f0b21a8	274	status = "disabled";
f6b88935 RJ	275
f6b88935 RJ	276	msi-parent = <&msi0>;
0f11736d	277	msi0: msi-controller {
f6b88935 RJ	278	compatible = "brcm,iproc-msi";
	279	msi-controller;
	280	interrupt-parent = <&gic>;
	281	interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
	282	<GIC_SPI 97 IRQ_TYPE_NONE>,
	283	<GIC_SPI 98 IRQ_TYPE_NONE>,
	284	<GIC_SPI 99 IRQ_TYPE_NONE>;
	285	};
0f0b21a8	286	};
cd590b50	287
0f0b21a8 RJ	288	pcie1: pcie@18013000 {
	289	compatible = "brcm,iproc-pcie";
	290	reg = <0x18013000 0x1000>;
cd590b50	291
0f0b21a8 RJ	292	#interrupt-cells = <1>;
	293	interrupt-map-mask = <0 0 0 0>;
	294	interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
cd590b50	295
0f0b21a8	296	linux,pci-domain = <1>;
cd590b50	297
0f0b21a8	298	bus-range = <0x00 0xff>;
cd590b50	299
0f0b21a8 RJ	300	#address-cells = <3>;
	301	#size-cells = <2>;
	302	device_type = "pci";
	303	ranges = <0x81000000 0 0 0x48000000 0 0x00010000
	304	0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
cd590b50	305
44a06fa4 RJ	306	phys = <&pcie1_phy>;
	307	phy-names = "pcie-phy";
	308
0f0b21a8	309	status = "disabled";
f6b88935 RJ	310
f6b88935 RJ	311	msi-parent = <&msi1>;
0f11736d	312	msi1: msi-controller {
f6b88935 RJ	313	compatible = "brcm,iproc-msi";
	314	msi-controller;
	315	interrupt-parent = <&gic>;
	316	interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>,
	317	<GIC_SPI 103 IRQ_TYPE_NONE>,
	318	<GIC_SPI 104 IRQ_TYPE_NONE>,
	319	<GIC_SPI 105 IRQ_TYPE_NONE>;
	320	};
0f0b21a8	321	};
cd590b50	322
143d0d47 JR	323	dma0: dma@18018000 {
	324	compatible = "arm,pl330", "arm,primecell";
	325	reg = <0x18018000 0x1000>;
	326	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	327	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	328	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	329	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	330	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	331	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	332	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	333	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	334	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
	335	clocks = <&apb_clk>;
	336	clock-names = "apb_pclk";
	337	#dma-cells = <1>;
	338	};
	339
0f0b21a8 RJ	340	uart0: serial@18020000 {
	341	compatible = "snps,dw-apb-uart";
	342	reg = <0x18020000 0x100>;
	343	reg-shift = <2>;
	344	reg-io-width = <4>;
	345	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	346	clocks = <&axi81_clk>;
	347	clock-frequency = <100000000>;
	348	status = "disabled";
	349	};
c9ad7bc5	350
0f0b21a8 RJ	351	uart1: serial@18021000 {
	352	compatible = "snps,dw-apb-uart";
	353	reg = <0x18021000 0x100>;
	354	reg-shift = <2>;
	355	reg-io-width = <4>;
	356	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	357	clocks = <&axi81_clk>;
	358	clock-frequency = <100000000>;
	359	status = "disabled";
	360	};
c9ad7bc5	361
0f0b21a8 RJ	362	uart2: serial@18022000 {
0f0b21a8 RJ	363	compatible = "snps,dw-apb-uart";
f5a5d8b4	364	reg = <0x18022000 0x100>;
0f0b21a8 RJ	365	reg-shift = <2>;
	366	reg-io-width = <4>;
	367	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	368	clocks = <&axi81_clk>;
	369	clock-frequency = <100000000>;
	370	status = "disabled";
	371	};
c9ad7bc5	372
0f0b21a8 RJ	373	uart3: serial@18023000 {
	374	compatible = "snps,dw-apb-uart";
	375	reg = <0x18023000 0x100>;
	376	reg-shift = <2>;
	377	reg-io-width = <4>;
	378	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	379	clocks = <&axi81_clk>;
	380	clock-frequency = <100000000>;
	381	status = "disabled";
	382	};
c9ad7bc5	383
143d0d47 JR	384	spi0: spi@18028000 {
	385	compatible = "arm,pl022", "arm,primecell";
	386	reg = <0x18028000 0x1000>;
	387	#address-cells = <1>;
	388	#size-cells = <0>;
	389	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
	390	pinctrl-0 = <&spi_0>;
	391	clocks = <&axi81_clk>;
	392	clock-names = "apb_pclk";
	393	status = "disabled";
	394	};
	395
	396	spi1: spi@18029000 {
	397	compatible = "arm,pl022", "arm,primecell";
	398	reg = <0x18029000 0x1000>;
	399	#address-cells = <1>;
	400	#size-cells = <0>;
	401	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	402	pinctrl-0 = <&spi_1>;
	403	clocks = <&axi81_clk>;
	404	clock-names = "apb_pclk";
	405	status = "disabled";
	406	};
	407
	408	spi2: spi@1802a000 {
	409	compatible = "arm,pl022", "arm,primecell";
	410	reg = <0x1802a000 0x1000>;
	411	#address-cells = <1>;
	412	#size-cells = <0>;
	413	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	414	pinctrl-0 = <&spi_2>;
	415	clocks = <&axi81_clk>;
	416	clock-names = "apb_pclk";
	417	status = "disabled";
	418	};
	419
	420	sdhci0: sdhci@18041000 {
	421	compatible = "brcm,sdhci-iproc-cygnus";
	422	reg = <0x18041000 0x100>;
	423	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	424	clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
	425	bus-width = <4>;
	426	sdhci,auto-cmd12;
	427	status = "disabled";
	428	};
	429
40c26d3a EA	430	eth0: ethernet@18042000 {
	431	compatible = "brcm,amac";
	432	reg = <0x18042000 0x1000>,
	433	<0x18110000 0x1000>;
	434	reg-names = "amac_base", "idm_base";
	435	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
	436	status = "disabled";
	437	};
	438
143d0d47 JR	439	sdhci1: sdhci@18043000 {
	440	compatible = "brcm,sdhci-iproc-cygnus";
	441	reg = <0x18043000 0x100>;
	442	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	443	clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
	444	bus-width = <4>;
	445	sdhci,auto-cmd12;
	446	status = "disabled";
	447	};
	448
0f0b21a8	449	nand: nand@18046000 {
08668d9d	450	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
0f0b21a8 RJ	451	reg = <0x18046000 0x600>, <0xf8105408 0x600>,
	452	<0x18046f00 0x20>;
	453	reg-names = "nand", "iproc-idm", "iproc-ext";
	454	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
874d5f1b	455
0f0b21a8 RJ	456	#address-cells = <1>;
0f0b21a8 RJ	457	#size-cells = <0>;
874d5f1b	458
0f0b21a8 RJ	459	brcm,nand-has-wp;
0f0b21a8 RJ	460	};
9c5101f7	461
fdacf095 RP	462	ehci0: usb@18048000 {
	463	compatible = "generic-ehci";
	464	reg = <0x18048000 0x100>;
	465	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	466	status = "disabled";
	467	};
	468
	469	ohci0: usb@18048800 {
	470	compatible = "generic-ohci";
	471	reg = <0x18048800 0x100>;
	472	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	473	status = "disabled";
	474	};
	475
8b9b666d SB	476	v3d: v3d@180a2000 {
	477	compatible = "brcm,cygnus-v3d";
	478	reg = <0x180a2000 0x1000>;
	479	clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>;
	480	clock-names = "v3d_clk";
	481	interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
	482	status = "disabled";
	483	};
	484
	485	vc4: gpu {
	486	compatible = "brcm,cygnus-vc4";
	487	};
	488
9c5101f7 RJ	489	gpio_asiu: gpio@180a5000 {
	490	compatible = "brcm,cygnus-asiu-gpio";
	491	reg = <0x180a5000 0x668>;
3ad8ff0e	492	ngpios = <146>;
9c5101f7 RJ	493	#gpio-cells = <2>;
	494	gpio-controller;
	495
9c5101f7 RJ	496	interrupt-controller;
9c5101f7 RJ	497	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3890ab2b PK	498	gpio-ranges = <&pinctrl 0 42 1>,
	499	<&pinctrl 1 44 3>,
	500	<&pinctrl 4 48 1>,
	501	<&pinctrl 5 50 3>,
	502	<&pinctrl 8 126 1>,
	503	<&pinctrl 9 155 1>,
	504	<&pinctrl 10 152 1>,
	505	<&pinctrl 11 154 1>,
	506	<&pinctrl 12 153 1>,
	507	<&pinctrl 13 127 3>,
	508	<&pinctrl 16 140 1>,
	509	<&pinctrl 17 145 7>,
	510	<&pinctrl 24 130 10>,
	511	<&pinctrl 34 141 4>,
	512	<&pinctrl 38 54 1>,
	513	<&pinctrl 39 56 3>,
	514	<&pinctrl 42 60 3>,
	515	<&pinctrl 45 64 3>,
	516	<&pinctrl 48 68 2>,
	517	<&pinctrl 50 84 6>,
	518	<&pinctrl 56 94 6>,
	519	<&pinctrl 62 72 1>,
	520	<&pinctrl 63 70 1>,
	521	<&pinctrl 64 80 1>,
	522	<&pinctrl 65 74 3>,
	523	<&pinctrl 68 78 1>,
	524	<&pinctrl 69 82 1>,
	525	<&pinctrl 70 156 17>,
	526	<&pinctrl 87 104 12>,
	527	<&pinctrl 99 102 2>,
	528	<&pinctrl 101 90 4>,
	529	<&pinctrl 105 116 6>,
	530	<&pinctrl 111 100 2>,
	531	<&pinctrl 113 122 4>,
	532	<&pinctrl 123 11 1>,
	533	<&pinctrl 124 38 4>,
	534	<&pinctrl 128 43 1>,
	535	<&pinctrl 129 47 1>,
	536	<&pinctrl 130 49 1>,
	537	<&pinctrl 131 53 1>,
	538	<&pinctrl 132 55 1>,
	539	<&pinctrl 133 59 1>,
	540	<&pinctrl 134 63 1>,
	541	<&pinctrl 135 67 1>,
	542	<&pinctrl 136 71 1>,
	543	<&pinctrl 137 73 1>,
	544	<&pinctrl 138 77 1>,
	545	<&pinctrl 139 79 1>,
	546	<&pinctrl 140 81 1>,
	547	<&pinctrl 141 83 1>,
	548	<&pinctrl 142 10 1>;
9c5101f7	549	};
35e372a3	550
74813ceb RP	551	ts_adc_syscon: ts_adc_syscon@180a6000 {
	552	compatible = "brcm,iproc-ts-adc-syscon", "syscon";
	553	reg = <0x180a6000 0xc30>;
	554	};
	555
	556	touchscreen: touchscreen@180a6000 {
35e372a3	557	compatible = "brcm,iproc-touchscreen";
74813ceb RP	558	#address-cells = <1>;
	559	#size-cells = <1>;
	560	ts_syscon = <&ts_adc_syscon>;
35e372a3 RJ	561	clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
	562	clock-names = "tsc_clk";
	563	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	564	status = "disabled";
	565	};
fd048c6b RP	566
	567	adc: adc@180a6000 {
	568	compatible = "brcm,iproc-static-adc";
	569	#io-channel-cells = <1>;
	570	io-channel-ranges;
	571	adc-syscon = <&ts_adc_syscon>;
	572	clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
	573	clock-names = "tsc_clk";
	574	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	575	status = "disabled";
	576	};
143d0d47 JR	577
	578	keypad: keypad@180ac000 {
	579	compatible = "brcm,bcm-keypad";
	580	reg = <0x180ac000 0x14c>;
	581	interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
	582	clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>;
	583	clock-names = "peri_clk";
	584	clock-frequency = <31250>;
	585	pull-up-enabled;
	586	col-debounce-filter-period = <0>;
	587	status-debounce-filter-period = <0>;
	588	row-output-enabled;
	589	status = "disabled";
	590	};
874d5f1b	591	};
c9ad7bc5	592	};