]>
Commit | Line | Data |
---|---|---|
549fce06 TL |
1 | &l4_cfg { /* 0x4a000000 */ |
2 | compatible = "ti,dra7-l4-cfg", "simple-bus"; | |
3 | reg = <0x4a000000 0x800>, | |
4 | <0x4a000800 0x800>, | |
5 | <0x4a001000 0x1000>; | |
6 | reg-names = "ap", "la", "ia0"; | |
7 | #address-cells = <1>; | |
8 | #size-cells = <1>; | |
9 | ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ | |
10 | <0x00100000 0x4a100000 0x100000>, /* segment 1 */ | |
11 | <0x00200000 0x4a200000 0x100000>; /* segment 2 */ | |
12 | ||
13 | segment@0 { /* 0x4a000000 */ | |
14 | compatible = "simple-bus"; | |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ | |
18 | <0x00000800 0x00000800 0x000800>, /* ap 1 */ | |
19 | <0x00001000 0x00001000 0x001000>, /* ap 2 */ | |
20 | <0x00002000 0x00002000 0x002000>, /* ap 3 */ | |
21 | <0x00004000 0x00004000 0x001000>, /* ap 4 */ | |
22 | <0x00005000 0x00005000 0x001000>, /* ap 5 */ | |
23 | <0x00006000 0x00006000 0x001000>, /* ap 6 */ | |
24 | <0x00008000 0x00008000 0x002000>, /* ap 7 */ | |
25 | <0x0000a000 0x0000a000 0x001000>, /* ap 8 */ | |
26 | <0x00056000 0x00056000 0x001000>, /* ap 9 */ | |
27 | <0x00057000 0x00057000 0x001000>, /* ap 10 */ | |
28 | <0x0005e000 0x0005e000 0x002000>, /* ap 11 */ | |
29 | <0x00060000 0x00060000 0x001000>, /* ap 12 */ | |
30 | <0x00080000 0x00080000 0x008000>, /* ap 13 */ | |
31 | <0x00088000 0x00088000 0x001000>, /* ap 14 */ | |
32 | <0x000a0000 0x000a0000 0x008000>, /* ap 15 */ | |
33 | <0x000a8000 0x000a8000 0x001000>, /* ap 16 */ | |
34 | <0x000d9000 0x000d9000 0x001000>, /* ap 17 */ | |
35 | <0x000da000 0x000da000 0x001000>, /* ap 18 */ | |
36 | <0x000dd000 0x000dd000 0x001000>, /* ap 19 */ | |
37 | <0x000de000 0x000de000 0x001000>, /* ap 20 */ | |
38 | <0x000e0000 0x000e0000 0x001000>, /* ap 21 */ | |
39 | <0x000e1000 0x000e1000 0x001000>, /* ap 22 */ | |
40 | <0x000f4000 0x000f4000 0x001000>, /* ap 23 */ | |
41 | <0x000f5000 0x000f5000 0x001000>, /* ap 24 */ | |
42 | <0x000f6000 0x000f6000 0x001000>, /* ap 25 */ | |
43 | <0x000f7000 0x000f7000 0x001000>, /* ap 26 */ | |
44 | <0x00090000 0x00090000 0x008000>, /* ap 59 */ | |
45 | <0x00098000 0x00098000 0x001000>; /* ap 60 */ | |
46 | ||
47 | target-module@2000 { /* 0x4a002000, ap 3 08.0 */ | |
4ed0dfe3 TL |
48 | compatible = "ti,sysc-omap4", "ti,sysc"; |
49 | reg = <0x2000 0x4>; | |
50 | reg-names = "rev"; | |
549fce06 TL |
51 | #address-cells = <1>; |
52 | #size-cells = <1>; | |
53 | ranges = <0x0 0x2000 0x2000>; | |
4ed0dfe3 TL |
54 | |
55 | scm: scm@0 { | |
56 | compatible = "ti,dra7-scm-core", "simple-bus"; | |
57 | reg = <0 0x2000>; | |
58 | #address-cells = <1>; | |
59 | #size-cells = <1>; | |
60 | ranges = <0 0 0x2000>; | |
61 | ||
62 | scm_conf: scm_conf@0 { | |
63 | compatible = "syscon", "simple-bus"; | |
64 | reg = <0x0 0x1400>; | |
65 | #address-cells = <1>; | |
66 | #size-cells = <1>; | |
67 | ranges = <0 0x0 0x1400>; | |
68 | ||
69 | pbias_regulator: pbias_regulator@e00 { | |
70 | compatible = "ti,pbias-dra7", "ti,pbias-omap"; | |
71 | reg = <0xe00 0x4>; | |
72 | syscon = <&scm_conf>; | |
73 | pbias_mmc_reg: pbias_mmc_omap5 { | |
74 | regulator-name = "pbias_mmc_omap5"; | |
75 | regulator-min-microvolt = <1800000>; | |
76 | regulator-max-microvolt = <3300000>; | |
77 | }; | |
78 | }; | |
79 | ||
e8acd856 GS |
80 | phy_gmii_sel: phy-gmii-sel { |
81 | compatible = "ti,dra7xx-phy-gmii-sel"; | |
82 | reg = <0x554 0x4>; | |
83 | #phy-cells = <1>; | |
84 | }; | |
85 | ||
4ed0dfe3 TL |
86 | scm_conf_clocks: clocks { |
87 | #address-cells = <1>; | |
88 | #size-cells = <0>; | |
89 | }; | |
90 | }; | |
91 | ||
4ed0dfe3 TL |
92 | dra7_pmx_core: pinmux@1400 { |
93 | compatible = "ti,dra7-padconf", | |
94 | "pinctrl-single"; | |
95 | reg = <0x1400 0x0468>; | |
96 | #address-cells = <1>; | |
97 | #size-cells = <0>; | |
98 | #pinctrl-cells = <1>; | |
99 | #interrupt-cells = <1>; | |
100 | interrupt-controller; | |
101 | pinctrl-single,register-width = <32>; | |
102 | pinctrl-single,function-mask = <0x3fffffff>; | |
103 | }; | |
104 | ||
105 | scm_conf1: scm_conf@1c04 { | |
106 | compatible = "syscon"; | |
107 | reg = <0x1c04 0x0020>; | |
108 | #syscon-cells = <2>; | |
109 | }; | |
110 | ||
111 | scm_conf_pcie: scm_conf@1c24 { | |
112 | compatible = "syscon"; | |
113 | reg = <0x1c24 0x0024>; | |
114 | }; | |
115 | ||
116 | sdma_xbar: dma-router@b78 { | |
117 | compatible = "ti,dra7-dma-crossbar"; | |
118 | reg = <0xb78 0xfc>; | |
119 | #dma-cells = <1>; | |
120 | dma-requests = <205>; | |
121 | ti,dma-safe-map = <0>; | |
122 | dma-masters = <&sdma>; | |
123 | }; | |
124 | ||
125 | edma_xbar: dma-router@c78 { | |
126 | compatible = "ti,dra7-dma-crossbar"; | |
127 | reg = <0xc78 0x7c>; | |
128 | #dma-cells = <2>; | |
129 | dma-requests = <204>; | |
130 | ti,dma-safe-map = <0>; | |
131 | dma-masters = <&edma>; | |
132 | }; | |
133 | }; | |
549fce06 TL |
134 | }; |
135 | ||
136 | target-module@5000 { /* 0x4a005000, ap 5 10.0 */ | |
4ed0dfe3 TL |
137 | compatible = "ti,sysc-omap4", "ti,sysc"; |
138 | reg = <0x5000 0x4>; | |
139 | reg-names = "rev"; | |
549fce06 TL |
140 | #address-cells = <1>; |
141 | #size-cells = <1>; | |
142 | ranges = <0x0 0x5000 0x1000>; | |
4ed0dfe3 TL |
143 | |
144 | cm_core_aon: cm_core_aon@0 { | |
145 | compatible = "ti,dra7-cm-core-aon", | |
146 | "simple-bus"; | |
147 | #address-cells = <1>; | |
148 | #size-cells = <1>; | |
149 | reg = <0 0x2000>; | |
150 | ranges = <0 0 0x2000>; | |
151 | ||
152 | cm_core_aon_clocks: clocks { | |
153 | #address-cells = <1>; | |
154 | #size-cells = <0>; | |
155 | }; | |
156 | ||
157 | cm_core_aon_clockdomains: clockdomains { | |
158 | }; | |
159 | }; | |
549fce06 TL |
160 | }; |
161 | ||
162 | target-module@8000 { /* 0x4a008000, ap 7 0e.0 */ | |
4ed0dfe3 TL |
163 | compatible = "ti,sysc-omap4", "ti,sysc"; |
164 | reg = <0x8000 0x4>; | |
165 | reg-names = "rev"; | |
549fce06 TL |
166 | #address-cells = <1>; |
167 | #size-cells = <1>; | |
168 | ranges = <0x0 0x8000 0x2000>; | |
4ed0dfe3 TL |
169 | |
170 | cm_core: cm_core@0 { | |
171 | compatible = "ti,dra7-cm-core", "simple-bus"; | |
172 | #address-cells = <1>; | |
173 | #size-cells = <1>; | |
174 | reg = <0 0x3000>; | |
175 | ranges = <0 0 0x3000>; | |
176 | ||
177 | cm_core_clocks: clocks { | |
178 | #address-cells = <1>; | |
179 | #size-cells = <0>; | |
180 | }; | |
181 | ||
182 | cm_core_clockdomains: clockdomains { | |
183 | }; | |
184 | }; | |
549fce06 TL |
185 | }; |
186 | ||
187 | target-module@56000 { /* 0x4a056000, ap 9 02.0 */ | |
188 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
189 | ti,hwmods = "dma_system"; | |
190 | reg = <0x56000 0x4>, | |
191 | <0x5602c 0x4>, | |
192 | <0x56028 0x4>; | |
193 | reg-names = "rev", "sysc", "syss"; | |
194 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | | |
195 | SYSC_OMAP2_EMUFREE | | |
196 | SYSC_OMAP2_SOFTRESET | | |
197 | SYSC_OMAP2_AUTOIDLE)>; | |
198 | ti,sysc-midle = <SYSC_IDLE_FORCE>, | |
199 | <SYSC_IDLE_NO>, | |
200 | <SYSC_IDLE_SMART>, | |
201 | <SYSC_IDLE_SMART_WKUP>; | |
202 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
203 | <SYSC_IDLE_NO>, | |
204 | <SYSC_IDLE_SMART>, | |
205 | <SYSC_IDLE_SMART_WKUP>; | |
206 | ti,syss-mask = <1>; | |
207 | /* Domains (P, C): core_pwrdm, dma_clkdm */ | |
208 | clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>; | |
209 | clock-names = "fck"; | |
210 | #address-cells = <1>; | |
211 | #size-cells = <1>; | |
212 | ranges = <0x0 0x56000 0x1000>; | |
4ed0dfe3 TL |
213 | |
214 | sdma: dma-controller@0 { | |
215 | compatible = "ti,omap4430-sdma"; | |
216 | reg = <0x0 0x1000>; | |
217 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
218 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
219 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
220 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
221 | #dma-cells = <1>; | |
222 | dma-channels = <32>; | |
223 | dma-requests = <127>; | |
224 | }; | |
549fce06 TL |
225 | }; |
226 | ||
227 | target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */ | |
228 | compatible = "ti,sysc"; | |
229 | status = "disabled"; | |
230 | #address-cells = <1>; | |
231 | #size-cells = <1>; | |
232 | ranges = <0x0 0x5e000 0x2000>; | |
233 | }; | |
234 | ||
235 | target-module@80000 { /* 0x4a080000, ap 13 20.0 */ | |
236 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
237 | ti,hwmods = "ocp2scp1"; | |
238 | reg = <0x80000 0x4>, | |
239 | <0x80010 0x4>, | |
240 | <0x80014 0x4>; | |
241 | reg-names = "rev", "sysc", "syss"; | |
242 | ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | | |
243 | SYSC_OMAP2_AUTOIDLE)>; | |
244 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
245 | <SYSC_IDLE_NO>, | |
246 | <SYSC_IDLE_SMART>; | |
247 | ti,syss-mask = <1>; | |
248 | /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ | |
249 | clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>; | |
250 | clock-names = "fck"; | |
251 | #address-cells = <1>; | |
252 | #size-cells = <1>; | |
253 | ranges = <0x0 0x80000 0x8000>; | |
4ed0dfe3 TL |
254 | |
255 | ocp2scp@0 { | |
256 | compatible = "ti,omap-ocp2scp"; | |
257 | #address-cells = <1>; | |
258 | #size-cells = <1>; | |
259 | ranges = <0 0 0x8000>; | |
260 | reg = <0x0 0x20>; | |
261 | ||
262 | usb2_phy1: phy@4000 { | |
263 | compatible = "ti,dra7x-usb2", "ti,omap-usb2"; | |
264 | reg = <0x4000 0x400>; | |
265 | syscon-phy-power = <&scm_conf 0x300>; | |
266 | clocks = <&usb_phy1_always_on_clk32k>, | |
267 | <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; | |
268 | clock-names = "wkupclk", | |
269 | "refclk"; | |
270 | #phy-cells = <0>; | |
271 | }; | |
272 | ||
273 | usb2_phy2: phy@5000 { | |
274 | compatible = "ti,dra7x-usb2-phy2", | |
275 | "ti,omap-usb2"; | |
276 | reg = <0x5000 0x400>; | |
277 | syscon-phy-power = <&scm_conf 0xe74>; | |
278 | clocks = <&usb_phy2_always_on_clk32k>, | |
279 | <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; | |
280 | clock-names = "wkupclk", | |
281 | "refclk"; | |
282 | #phy-cells = <0>; | |
283 | }; | |
284 | ||
285 | usb3_phy1: phy@4400 { | |
286 | compatible = "ti,omap-usb3"; | |
287 | reg = <0x4400 0x80>, | |
288 | <0x4800 0x64>, | |
289 | <0x4c00 0x40>; | |
290 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
291 | syscon-phy-power = <&scm_conf 0x370>; | |
292 | clocks = <&usb_phy3_always_on_clk32k>, | |
293 | <&sys_clkin1>, | |
294 | <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; | |
295 | clock-names = "wkupclk", | |
296 | "sysclk", | |
297 | "refclk"; | |
298 | #phy-cells = <0>; | |
299 | }; | |
300 | }; | |
549fce06 TL |
301 | }; |
302 | ||
303 | target-module@90000 { /* 0x4a090000, ap 59 42.0 */ | |
304 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
305 | ti,hwmods = "ocp2scp3"; | |
306 | reg = <0x90000 0x4>, | |
307 | <0x90010 0x4>, | |
308 | <0x90014 0x4>; | |
309 | reg-names = "rev", "sysc", "syss"; | |
310 | ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | | |
311 | SYSC_OMAP2_AUTOIDLE)>; | |
312 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
313 | <SYSC_IDLE_NO>, | |
314 | <SYSC_IDLE_SMART>; | |
315 | ti,syss-mask = <1>; | |
316 | /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ | |
317 | clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>; | |
318 | clock-names = "fck"; | |
319 | #address-cells = <1>; | |
320 | #size-cells = <1>; | |
321 | ranges = <0x0 0x90000 0x8000>; | |
4ed0dfe3 TL |
322 | |
323 | ocp2scp@0 { | |
324 | compatible = "ti,omap-ocp2scp"; | |
325 | #address-cells = <1>; | |
326 | #size-cells = <1>; | |
327 | ranges = <0 0 0x8000>; | |
328 | reg = <0x0 0x20>; | |
329 | ||
330 | pcie1_phy: pciephy@4000 { | |
331 | compatible = "ti,phy-pipe3-pcie"; | |
332 | reg = <0x4000 0x80>, /* phy_rx */ | |
333 | <0x4400 0x64>; /* phy_tx */ | |
334 | reg-names = "phy_rx", "phy_tx"; | |
335 | syscon-phy-power = <&scm_conf_pcie 0x1c>; | |
336 | syscon-pcs = <&scm_conf_pcie 0x10>; | |
337 | clocks = <&dpll_pcie_ref_ck>, | |
338 | <&dpll_pcie_ref_m2ldo_ck>, | |
339 | <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>, | |
340 | <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, | |
341 | <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>, | |
342 | <&optfclk_pciephy_div>, | |
343 | <&sys_clkin1>; | |
344 | clock-names = "dpll_ref", "dpll_ref_m2", | |
345 | "wkupclk", "refclk", | |
346 | "div-clk", "phy-div", "sysclk"; | |
347 | #phy-cells = <0>; | |
348 | }; | |
349 | ||
350 | pcie2_phy: pciephy@5000 { | |
351 | compatible = "ti,phy-pipe3-pcie"; | |
352 | reg = <0x5000 0x80>, /* phy_rx */ | |
353 | <0x5400 0x64>; /* phy_tx */ | |
354 | reg-names = "phy_rx", "phy_tx"; | |
355 | syscon-phy-power = <&scm_conf_pcie 0x20>; | |
356 | syscon-pcs = <&scm_conf_pcie 0x10>; | |
357 | clocks = <&dpll_pcie_ref_ck>, | |
358 | <&dpll_pcie_ref_m2ldo_ck>, | |
359 | <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>, | |
360 | <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, | |
361 | <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>, | |
362 | <&optfclk_pciephy_div>, | |
363 | <&sys_clkin1>; | |
364 | clock-names = "dpll_ref", "dpll_ref_m2", | |
365 | "wkupclk", "refclk", | |
366 | "div-clk", "phy-div", "sysclk"; | |
367 | #phy-cells = <0>; | |
368 | status = "disabled"; | |
369 | }; | |
370 | ||
371 | sata_phy: phy@6000 { | |
372 | compatible = "ti,phy-pipe3-sata"; | |
373 | reg = <0x6000 0x80>, /* phy_rx */ | |
374 | <0x6400 0x64>, /* phy_tx */ | |
375 | <0x6800 0x40>; /* pll_ctrl */ | |
376 | reg-names = "phy_rx", "phy_tx", "pll_ctrl"; | |
377 | syscon-phy-power = <&scm_conf 0x374>; | |
378 | clocks = <&sys_clkin1>, | |
379 | <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; | |
380 | clock-names = "sysclk", "refclk"; | |
381 | syscon-pllreset = <&scm_conf 0x3fc>; | |
382 | #phy-cells = <0>; | |
383 | }; | |
384 | }; | |
549fce06 TL |
385 | }; |
386 | ||
387 | target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */ | |
388 | compatible = "ti,sysc"; | |
389 | status = "disabled"; | |
390 | #address-cells = <1>; | |
391 | #size-cells = <1>; | |
392 | ranges = <0x0 0xa0000 0x8000>; | |
393 | }; | |
394 | ||
395 | target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */ | |
4ed0dfe3 | 396 | compatible = "ti,sysc-omap4-sr", "ti,sysc"; |
549fce06 TL |
397 | ti,hwmods = "smartreflex_mpu"; |
398 | reg = <0xd9038 0x4>; | |
399 | reg-names = "sysc"; | |
400 | ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; | |
401 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
402 | <SYSC_IDLE_NO>, | |
403 | <SYSC_IDLE_SMART>, | |
404 | <SYSC_IDLE_SMART_WKUP>; | |
405 | /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ | |
406 | clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>; | |
407 | clock-names = "fck"; | |
408 | #address-cells = <1>; | |
409 | #size-cells = <1>; | |
410 | ranges = <0x0 0xd9000 0x1000>; | |
4ed0dfe3 TL |
411 | |
412 | /* SmartReflex child device marked reserved in TRM */ | |
549fce06 TL |
413 | }; |
414 | ||
415 | target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */ | |
4ed0dfe3 | 416 | compatible = "ti,sysc-omap4-sr", "ti,sysc"; |
549fce06 TL |
417 | ti,hwmods = "smartreflex_core"; |
418 | reg = <0xdd038 0x4>; | |
419 | reg-names = "sysc"; | |
420 | ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; | |
421 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
422 | <SYSC_IDLE_NO>, | |
423 | <SYSC_IDLE_SMART>, | |
424 | <SYSC_IDLE_SMART_WKUP>; | |
425 | /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ | |
426 | clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>; | |
427 | clock-names = "fck"; | |
428 | #address-cells = <1>; | |
429 | #size-cells = <1>; | |
430 | ranges = <0x0 0xdd000 0x1000>; | |
4ed0dfe3 TL |
431 | |
432 | /* SmartReflex child device marked reserved in TRM */ | |
549fce06 TL |
433 | }; |
434 | ||
435 | target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */ | |
436 | compatible = "ti,sysc"; | |
437 | status = "disabled"; | |
438 | #address-cells = <1>; | |
439 | #size-cells = <1>; | |
440 | ranges = <0x0 0xe0000 0x1000>; | |
441 | }; | |
442 | ||
443 | target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */ | |
444 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
445 | ti,hwmods = "mailbox1"; | |
446 | reg = <0xf4000 0x4>, | |
447 | <0xf4010 0x4>; | |
448 | reg-names = "rev", "sysc"; | |
449 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
450 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
451 | <SYSC_IDLE_NO>, | |
452 | <SYSC_IDLE_SMART>; | |
453 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
454 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>; | |
455 | clock-names = "fck"; | |
456 | #address-cells = <1>; | |
457 | #size-cells = <1>; | |
458 | ranges = <0x0 0xf4000 0x1000>; | |
4ed0dfe3 TL |
459 | |
460 | mailbox1: mailbox@0 { | |
461 | compatible = "ti,omap4-mailbox"; | |
462 | reg = <0x0 0x200>; | |
463 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, | |
464 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
465 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; | |
466 | #mbox-cells = <1>; | |
467 | ti,mbox-num-users = <3>; | |
468 | ti,mbox-num-fifos = <8>; | |
469 | status = "disabled"; | |
470 | }; | |
549fce06 TL |
471 | }; |
472 | ||
473 | target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */ | |
474 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
475 | ti,hwmods = "spinlock"; | |
476 | reg = <0xf6000 0x4>, | |
477 | <0xf6010 0x4>, | |
478 | <0xf6014 0x4>; | |
479 | reg-names = "rev", "sysc", "syss"; | |
480 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
481 | SYSC_OMAP2_SOFTRESET | | |
482 | SYSC_OMAP2_AUTOIDLE)>; | |
483 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
484 | <SYSC_IDLE_NO>, | |
485 | <SYSC_IDLE_SMART>; | |
486 | ti,syss-mask = <1>; | |
487 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
488 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>; | |
489 | clock-names = "fck"; | |
490 | #address-cells = <1>; | |
491 | #size-cells = <1>; | |
492 | ranges = <0x0 0xf6000 0x1000>; | |
4ed0dfe3 TL |
493 | |
494 | hwspinlock: spinlock@0 { | |
495 | compatible = "ti,omap4-hwspinlock"; | |
496 | reg = <0x0 0x1000>; | |
497 | #hwlock-cells = <1>; | |
498 | }; | |
549fce06 TL |
499 | }; |
500 | }; | |
501 | ||
502 | segment@100000 { /* 0x4a100000 */ | |
503 | compatible = "simple-bus"; | |
504 | #address-cells = <1>; | |
505 | #size-cells = <1>; | |
506 | ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */ | |
507 | <0x00003000 0x00103000 0x001000>, /* ap 28 */ | |
508 | <0x00008000 0x00108000 0x001000>, /* ap 29 */ | |
509 | <0x00009000 0x00109000 0x001000>, /* ap 30 */ | |
510 | <0x00040000 0x00140000 0x010000>, /* ap 31 */ | |
511 | <0x00050000 0x00150000 0x001000>, /* ap 32 */ | |
512 | <0x00051000 0x00151000 0x001000>, /* ap 33 */ | |
513 | <0x00052000 0x00152000 0x001000>, /* ap 34 */ | |
514 | <0x00053000 0x00153000 0x001000>, /* ap 35 */ | |
515 | <0x00054000 0x00154000 0x001000>, /* ap 36 */ | |
516 | <0x00055000 0x00155000 0x001000>, /* ap 37 */ | |
517 | <0x00056000 0x00156000 0x001000>, /* ap 38 */ | |
518 | <0x00057000 0x00157000 0x001000>, /* ap 39 */ | |
519 | <0x00058000 0x00158000 0x001000>, /* ap 40 */ | |
520 | <0x0005b000 0x0015b000 0x001000>, /* ap 41 */ | |
521 | <0x0005c000 0x0015c000 0x001000>, /* ap 42 */ | |
522 | <0x0005d000 0x0015d000 0x001000>, /* ap 45 */ | |
523 | <0x0005e000 0x0015e000 0x001000>, /* ap 46 */ | |
524 | <0x0005f000 0x0015f000 0x001000>, /* ap 47 */ | |
525 | <0x00060000 0x00160000 0x001000>, /* ap 48 */ | |
526 | <0x00061000 0x00161000 0x001000>, /* ap 49 */ | |
527 | <0x00062000 0x00162000 0x001000>, /* ap 50 */ | |
528 | <0x00063000 0x00163000 0x001000>, /* ap 51 */ | |
529 | <0x00064000 0x00164000 0x001000>, /* ap 52 */ | |
530 | <0x00065000 0x00165000 0x001000>, /* ap 53 */ | |
531 | <0x00066000 0x00166000 0x001000>, /* ap 54 */ | |
532 | <0x00067000 0x00167000 0x001000>, /* ap 55 */ | |
533 | <0x00068000 0x00168000 0x001000>, /* ap 56 */ | |
534 | <0x0006d000 0x0016d000 0x001000>, /* ap 57 */ | |
535 | <0x0006e000 0x0016e000 0x001000>, /* ap 58 */ | |
536 | <0x00071000 0x00171000 0x001000>, /* ap 61 */ | |
537 | <0x00072000 0x00172000 0x001000>, /* ap 62 */ | |
538 | <0x00073000 0x00173000 0x001000>, /* ap 63 */ | |
539 | <0x00074000 0x00174000 0x001000>, /* ap 64 */ | |
540 | <0x00075000 0x00175000 0x001000>, /* ap 65 */ | |
541 | <0x00076000 0x00176000 0x001000>, /* ap 66 */ | |
542 | <0x00077000 0x00177000 0x001000>, /* ap 67 */ | |
543 | <0x00078000 0x00178000 0x001000>, /* ap 68 */ | |
544 | <0x00081000 0x00181000 0x001000>, /* ap 69 */ | |
545 | <0x00082000 0x00182000 0x001000>, /* ap 70 */ | |
546 | <0x00083000 0x00183000 0x001000>, /* ap 71 */ | |
547 | <0x00084000 0x00184000 0x001000>, /* ap 72 */ | |
548 | <0x00085000 0x00185000 0x001000>, /* ap 73 */ | |
549 | <0x00086000 0x00186000 0x001000>, /* ap 74 */ | |
550 | <0x00087000 0x00187000 0x001000>, /* ap 75 */ | |
551 | <0x00088000 0x00188000 0x001000>, /* ap 76 */ | |
552 | <0x00069000 0x00169000 0x001000>, /* ap 103 */ | |
553 | <0x0006a000 0x0016a000 0x001000>, /* ap 104 */ | |
554 | <0x00079000 0x00179000 0x001000>, /* ap 105 */ | |
555 | <0x0007a000 0x0017a000 0x001000>, /* ap 106 */ | |
556 | <0x0006b000 0x0016b000 0x001000>, /* ap 107 */ | |
557 | <0x0006c000 0x0016c000 0x001000>, /* ap 108 */ | |
558 | <0x0007b000 0x0017b000 0x001000>, /* ap 121 */ | |
559 | <0x0007c000 0x0017c000 0x001000>, /* ap 122 */ | |
560 | <0x0007d000 0x0017d000 0x001000>, /* ap 123 */ | |
561 | <0x0007e000 0x0017e000 0x001000>, /* ap 124 */ | |
562 | <0x00059000 0x00159000 0x001000>, /* ap 125 */ | |
563 | <0x0005a000 0x0015a000 0x001000>; /* ap 126 */ | |
564 | ||
565 | target-module@2000 { /* 0x4a102000, ap 27 3c.0 */ | |
566 | compatible = "ti,sysc"; | |
567 | status = "disabled"; | |
568 | #address-cells = <1>; | |
569 | #size-cells = <1>; | |
570 | ranges = <0x0 0x2000 0x1000>; | |
571 | }; | |
572 | ||
573 | target-module@8000 { /* 0x4a108000, ap 29 1e.0 */ | |
574 | compatible = "ti,sysc"; | |
575 | status = "disabled"; | |
576 | #address-cells = <1>; | |
577 | #size-cells = <1>; | |
578 | ranges = <0x0 0x8000 0x1000>; | |
579 | }; | |
580 | ||
581 | target-module@40000 { /* 0x4a140000, ap 31 06.0 */ | |
582 | compatible = "ti,sysc"; | |
583 | status = "disabled"; | |
584 | #address-cells = <1>; | |
585 | #size-cells = <1>; | |
586 | ranges = <0x0 0x40000 0x10000>; | |
587 | }; | |
588 | ||
589 | target-module@51000 { /* 0x4a151000, ap 33 50.0 */ | |
590 | compatible = "ti,sysc"; | |
591 | status = "disabled"; | |
592 | #address-cells = <1>; | |
593 | #size-cells = <1>; | |
594 | ranges = <0x0 0x51000 0x1000>; | |
595 | }; | |
596 | ||
597 | target-module@53000 { /* 0x4a153000, ap 35 54.0 */ | |
598 | compatible = "ti,sysc"; | |
599 | status = "disabled"; | |
600 | #address-cells = <1>; | |
601 | #size-cells = <1>; | |
602 | ranges = <0x0 0x53000 0x1000>; | |
603 | }; | |
604 | ||
605 | target-module@55000 { /* 0x4a155000, ap 37 46.0 */ | |
606 | compatible = "ti,sysc"; | |
607 | status = "disabled"; | |
608 | #address-cells = <1>; | |
609 | #size-cells = <1>; | |
610 | ranges = <0x0 0x55000 0x1000>; | |
611 | }; | |
612 | ||
613 | target-module@57000 { /* 0x4a157000, ap 39 58.0 */ | |
614 | compatible = "ti,sysc"; | |
615 | status = "disabled"; | |
616 | #address-cells = <1>; | |
617 | #size-cells = <1>; | |
618 | ranges = <0x0 0x57000 0x1000>; | |
619 | }; | |
620 | ||
621 | target-module@59000 { /* 0x4a159000, ap 125 6a.0 */ | |
622 | compatible = "ti,sysc"; | |
623 | status = "disabled"; | |
624 | #address-cells = <1>; | |
625 | #size-cells = <1>; | |
626 | ranges = <0x0 0x59000 0x1000>; | |
627 | }; | |
628 | ||
629 | target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */ | |
630 | compatible = "ti,sysc"; | |
631 | status = "disabled"; | |
632 | #address-cells = <1>; | |
633 | #size-cells = <1>; | |
634 | ranges = <0x0 0x5b000 0x1000>; | |
635 | }; | |
636 | ||
637 | target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */ | |
638 | compatible = "ti,sysc"; | |
639 | status = "disabled"; | |
640 | #address-cells = <1>; | |
641 | #size-cells = <1>; | |
642 | ranges = <0x0 0x5d000 0x1000>; | |
643 | }; | |
644 | ||
645 | target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */ | |
646 | compatible = "ti,sysc"; | |
647 | status = "disabled"; | |
648 | #address-cells = <1>; | |
649 | #size-cells = <1>; | |
650 | ranges = <0x0 0x5f000 0x1000>; | |
651 | }; | |
652 | ||
653 | target-module@61000 { /* 0x4a161000, ap 49 32.0 */ | |
654 | compatible = "ti,sysc"; | |
655 | status = "disabled"; | |
656 | #address-cells = <1>; | |
657 | #size-cells = <1>; | |
658 | ranges = <0x0 0x61000 0x1000>; | |
659 | }; | |
660 | ||
661 | target-module@63000 { /* 0x4a163000, ap 51 5c.0 */ | |
662 | compatible = "ti,sysc"; | |
663 | status = "disabled"; | |
664 | #address-cells = <1>; | |
665 | #size-cells = <1>; | |
666 | ranges = <0x0 0x63000 0x1000>; | |
667 | }; | |
668 | ||
669 | target-module@65000 { /* 0x4a165000, ap 53 4e.0 */ | |
670 | compatible = "ti,sysc"; | |
671 | status = "disabled"; | |
672 | #address-cells = <1>; | |
673 | #size-cells = <1>; | |
674 | ranges = <0x0 0x65000 0x1000>; | |
675 | }; | |
676 | ||
677 | target-module@67000 { /* 0x4a167000, ap 55 5e.0 */ | |
678 | compatible = "ti,sysc"; | |
679 | status = "disabled"; | |
680 | #address-cells = <1>; | |
681 | #size-cells = <1>; | |
682 | ranges = <0x0 0x67000 0x1000>; | |
683 | }; | |
684 | ||
685 | target-module@69000 { /* 0x4a169000, ap 103 4a.0 */ | |
686 | compatible = "ti,sysc"; | |
687 | status = "disabled"; | |
688 | #address-cells = <1>; | |
689 | #size-cells = <1>; | |
690 | ranges = <0x0 0x69000 0x1000>; | |
691 | }; | |
692 | ||
693 | target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */ | |
694 | compatible = "ti,sysc"; | |
695 | status = "disabled"; | |
696 | #address-cells = <1>; | |
697 | #size-cells = <1>; | |
698 | ranges = <0x0 0x6b000 0x1000>; | |
699 | }; | |
700 | ||
701 | target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */ | |
702 | compatible = "ti,sysc"; | |
703 | status = "disabled"; | |
704 | #address-cells = <1>; | |
705 | #size-cells = <1>; | |
706 | ranges = <0x0 0x6d000 0x1000>; | |
707 | }; | |
708 | ||
709 | target-module@71000 { /* 0x4a171000, ap 61 48.0 */ | |
710 | compatible = "ti,sysc"; | |
711 | status = "disabled"; | |
712 | #address-cells = <1>; | |
713 | #size-cells = <1>; | |
714 | ranges = <0x0 0x71000 0x1000>; | |
715 | }; | |
716 | ||
717 | target-module@73000 { /* 0x4a173000, ap 63 2a.0 */ | |
718 | compatible = "ti,sysc"; | |
719 | status = "disabled"; | |
720 | #address-cells = <1>; | |
721 | #size-cells = <1>; | |
722 | ranges = <0x0 0x73000 0x1000>; | |
723 | }; | |
724 | ||
725 | target-module@75000 { /* 0x4a175000, ap 65 64.0 */ | |
726 | compatible = "ti,sysc"; | |
727 | status = "disabled"; | |
728 | #address-cells = <1>; | |
729 | #size-cells = <1>; | |
730 | ranges = <0x0 0x75000 0x1000>; | |
731 | }; | |
732 | ||
733 | target-module@77000 { /* 0x4a177000, ap 67 66.0 */ | |
734 | compatible = "ti,sysc"; | |
735 | status = "disabled"; | |
736 | #address-cells = <1>; | |
737 | #size-cells = <1>; | |
738 | ranges = <0x0 0x77000 0x1000>; | |
739 | }; | |
740 | ||
741 | target-module@79000 { /* 0x4a179000, ap 105 34.0 */ | |
742 | compatible = "ti,sysc"; | |
743 | status = "disabled"; | |
744 | #address-cells = <1>; | |
745 | #size-cells = <1>; | |
746 | ranges = <0x0 0x79000 0x1000>; | |
747 | }; | |
748 | ||
749 | target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */ | |
750 | compatible = "ti,sysc"; | |
751 | status = "disabled"; | |
752 | #address-cells = <1>; | |
753 | #size-cells = <1>; | |
754 | ranges = <0x0 0x7b000 0x1000>; | |
755 | }; | |
756 | ||
757 | target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */ | |
758 | compatible = "ti,sysc"; | |
759 | status = "disabled"; | |
760 | #address-cells = <1>; | |
761 | #size-cells = <1>; | |
762 | ranges = <0x0 0x7d000 0x1000>; | |
763 | }; | |
764 | ||
765 | target-module@81000 { /* 0x4a181000, ap 69 26.0 */ | |
766 | compatible = "ti,sysc"; | |
767 | status = "disabled"; | |
768 | #address-cells = <1>; | |
769 | #size-cells = <1>; | |
770 | ranges = <0x0 0x81000 0x1000>; | |
771 | }; | |
772 | ||
773 | target-module@83000 { /* 0x4a183000, ap 71 2e.0 */ | |
774 | compatible = "ti,sysc"; | |
775 | status = "disabled"; | |
776 | #address-cells = <1>; | |
777 | #size-cells = <1>; | |
778 | ranges = <0x0 0x83000 0x1000>; | |
779 | }; | |
780 | ||
781 | target-module@85000 { /* 0x4a185000, ap 73 36.0 */ | |
782 | compatible = "ti,sysc"; | |
783 | status = "disabled"; | |
784 | #address-cells = <1>; | |
785 | #size-cells = <1>; | |
786 | ranges = <0x0 0x85000 0x1000>; | |
787 | }; | |
788 | ||
789 | target-module@87000 { /* 0x4a187000, ap 75 74.0 */ | |
790 | compatible = "ti,sysc"; | |
791 | status = "disabled"; | |
792 | #address-cells = <1>; | |
793 | #size-cells = <1>; | |
794 | ranges = <0x0 0x87000 0x1000>; | |
795 | }; | |
796 | }; | |
797 | ||
798 | segment@200000 { /* 0x4a200000 */ | |
799 | compatible = "simple-bus"; | |
800 | #address-cells = <1>; | |
801 | #size-cells = <1>; | |
802 | ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */ | |
803 | <0x00019000 0x00219000 0x001000>, /* ap 44 */ | |
804 | <0x00000000 0x00200000 0x001000>, /* ap 77 */ | |
805 | <0x00001000 0x00201000 0x001000>, /* ap 78 */ | |
806 | <0x0000a000 0x0020a000 0x001000>, /* ap 79 */ | |
807 | <0x0000b000 0x0020b000 0x001000>, /* ap 80 */ | |
808 | <0x0000c000 0x0020c000 0x001000>, /* ap 81 */ | |
809 | <0x0000d000 0x0020d000 0x001000>, /* ap 82 */ | |
810 | <0x0000e000 0x0020e000 0x001000>, /* ap 83 */ | |
811 | <0x0000f000 0x0020f000 0x001000>, /* ap 84 */ | |
812 | <0x00010000 0x00210000 0x001000>, /* ap 85 */ | |
813 | <0x00011000 0x00211000 0x001000>, /* ap 86 */ | |
814 | <0x00012000 0x00212000 0x001000>, /* ap 87 */ | |
815 | <0x00013000 0x00213000 0x001000>, /* ap 88 */ | |
816 | <0x00014000 0x00214000 0x001000>, /* ap 89 */ | |
817 | <0x00015000 0x00215000 0x001000>, /* ap 90 */ | |
818 | <0x0002a000 0x0022a000 0x001000>, /* ap 91 */ | |
819 | <0x0002b000 0x0022b000 0x001000>, /* ap 92 */ | |
820 | <0x0001c000 0x0021c000 0x001000>, /* ap 93 */ | |
821 | <0x0001d000 0x0021d000 0x001000>, /* ap 94 */ | |
822 | <0x0001e000 0x0021e000 0x001000>, /* ap 95 */ | |
823 | <0x0001f000 0x0021f000 0x001000>, /* ap 96 */ | |
824 | <0x00020000 0x00220000 0x001000>, /* ap 97 */ | |
825 | <0x00021000 0x00221000 0x001000>, /* ap 98 */ | |
826 | <0x00024000 0x00224000 0x001000>, /* ap 99 */ | |
827 | <0x00025000 0x00225000 0x001000>, /* ap 100 */ | |
828 | <0x00026000 0x00226000 0x001000>, /* ap 101 */ | |
829 | <0x00027000 0x00227000 0x001000>, /* ap 102 */ | |
830 | <0x0002c000 0x0022c000 0x001000>, /* ap 109 */ | |
831 | <0x0002d000 0x0022d000 0x001000>, /* ap 110 */ | |
832 | <0x0002e000 0x0022e000 0x001000>, /* ap 111 */ | |
833 | <0x0002f000 0x0022f000 0x001000>, /* ap 112 */ | |
834 | <0x00030000 0x00230000 0x001000>, /* ap 113 */ | |
835 | <0x00031000 0x00231000 0x001000>, /* ap 114 */ | |
836 | <0x00032000 0x00232000 0x001000>, /* ap 115 */ | |
837 | <0x00033000 0x00233000 0x001000>, /* ap 116 */ | |
838 | <0x00034000 0x00234000 0x001000>, /* ap 117 */ | |
839 | <0x00035000 0x00235000 0x001000>, /* ap 118 */ | |
840 | <0x00036000 0x00236000 0x001000>, /* ap 119 */ | |
841 | <0x00037000 0x00237000 0x001000>, /* ap 120 */ | |
842 | <0x0001a000 0x0021a000 0x001000>, /* ap 127 */ | |
843 | <0x0001b000 0x0021b000 0x001000>; /* ap 128 */ | |
844 | ||
845 | target-module@0 { /* 0x4a200000, ap 77 3e.0 */ | |
846 | compatible = "ti,sysc"; | |
847 | status = "disabled"; | |
848 | #address-cells = <1>; | |
849 | #size-cells = <1>; | |
850 | ranges = <0x0 0x0 0x1000>; | |
851 | }; | |
852 | ||
853 | target-module@a000 { /* 0x4a20a000, ap 79 30.0 */ | |
854 | compatible = "ti,sysc"; | |
855 | status = "disabled"; | |
856 | #address-cells = <1>; | |
857 | #size-cells = <1>; | |
858 | ranges = <0x0 0xa000 0x1000>; | |
859 | }; | |
860 | ||
861 | target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */ | |
862 | compatible = "ti,sysc"; | |
863 | status = "disabled"; | |
864 | #address-cells = <1>; | |
865 | #size-cells = <1>; | |
866 | ranges = <0x0 0xc000 0x1000>; | |
867 | }; | |
868 | ||
869 | target-module@e000 { /* 0x4a20e000, ap 83 22.0 */ | |
870 | compatible = "ti,sysc"; | |
871 | status = "disabled"; | |
872 | #address-cells = <1>; | |
873 | #size-cells = <1>; | |
874 | ranges = <0x0 0xe000 0x1000>; | |
875 | }; | |
876 | ||
877 | target-module@10000 { /* 0x4a210000, ap 85 14.0 */ | |
878 | compatible = "ti,sysc"; | |
879 | status = "disabled"; | |
880 | #address-cells = <1>; | |
881 | #size-cells = <1>; | |
882 | ranges = <0x0 0x10000 0x1000>; | |
883 | }; | |
884 | ||
885 | target-module@12000 { /* 0x4a212000, ap 87 16.0 */ | |
886 | compatible = "ti,sysc"; | |
887 | status = "disabled"; | |
888 | #address-cells = <1>; | |
889 | #size-cells = <1>; | |
890 | ranges = <0x0 0x12000 0x1000>; | |
891 | }; | |
892 | ||
893 | target-module@14000 { /* 0x4a214000, ap 89 1c.0 */ | |
894 | compatible = "ti,sysc"; | |
895 | status = "disabled"; | |
896 | #address-cells = <1>; | |
897 | #size-cells = <1>; | |
898 | ranges = <0x0 0x14000 0x1000>; | |
899 | }; | |
900 | ||
901 | target-module@18000 { /* 0x4a218000, ap 43 12.0 */ | |
902 | compatible = "ti,sysc"; | |
903 | status = "disabled"; | |
904 | #address-cells = <1>; | |
905 | #size-cells = <1>; | |
906 | ranges = <0x0 0x18000 0x1000>; | |
907 | }; | |
908 | ||
909 | target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */ | |
910 | compatible = "ti,sysc"; | |
911 | status = "disabled"; | |
912 | #address-cells = <1>; | |
913 | #size-cells = <1>; | |
914 | ranges = <0x0 0x1a000 0x1000>; | |
915 | }; | |
916 | ||
917 | target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */ | |
918 | compatible = "ti,sysc"; | |
919 | status = "disabled"; | |
920 | #address-cells = <1>; | |
921 | #size-cells = <1>; | |
922 | ranges = <0x0 0x1c000 0x1000>; | |
923 | }; | |
924 | ||
925 | target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */ | |
926 | compatible = "ti,sysc"; | |
927 | status = "disabled"; | |
928 | #address-cells = <1>; | |
929 | #size-cells = <1>; | |
930 | ranges = <0x0 0x1e000 0x1000>; | |
931 | }; | |
932 | ||
933 | target-module@20000 { /* 0x4a220000, ap 97 24.0 */ | |
934 | compatible = "ti,sysc"; | |
935 | status = "disabled"; | |
936 | #address-cells = <1>; | |
937 | #size-cells = <1>; | |
938 | ranges = <0x0 0x20000 0x1000>; | |
939 | }; | |
940 | ||
941 | target-module@24000 { /* 0x4a224000, ap 99 44.0 */ | |
942 | compatible = "ti,sysc"; | |
943 | status = "disabled"; | |
944 | #address-cells = <1>; | |
945 | #size-cells = <1>; | |
946 | ranges = <0x0 0x24000 0x1000>; | |
947 | }; | |
948 | ||
949 | target-module@26000 { /* 0x4a226000, ap 101 2c.0 */ | |
950 | compatible = "ti,sysc"; | |
951 | status = "disabled"; | |
952 | #address-cells = <1>; | |
953 | #size-cells = <1>; | |
954 | ranges = <0x0 0x26000 0x1000>; | |
955 | }; | |
956 | ||
957 | target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */ | |
958 | compatible = "ti,sysc"; | |
959 | status = "disabled"; | |
960 | #address-cells = <1>; | |
961 | #size-cells = <1>; | |
962 | ranges = <0x0 0x2a000 0x1000>; | |
963 | }; | |
964 | ||
965 | target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */ | |
966 | compatible = "ti,sysc"; | |
967 | status = "disabled"; | |
968 | #address-cells = <1>; | |
969 | #size-cells = <1>; | |
970 | ranges = <0x0 0x2c000 0x1000>; | |
971 | }; | |
972 | ||
973 | target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */ | |
974 | compatible = "ti,sysc"; | |
975 | status = "disabled"; | |
976 | #address-cells = <1>; | |
977 | #size-cells = <1>; | |
978 | ranges = <0x0 0x2e000 0x1000>; | |
979 | }; | |
980 | ||
981 | target-module@30000 { /* 0x4a230000, ap 113 70.0 */ | |
982 | compatible = "ti,sysc"; | |
983 | status = "disabled"; | |
984 | #address-cells = <1>; | |
985 | #size-cells = <1>; | |
986 | ranges = <0x0 0x30000 0x1000>; | |
987 | }; | |
988 | ||
989 | target-module@32000 { /* 0x4a232000, ap 115 5a.0 */ | |
990 | compatible = "ti,sysc"; | |
991 | status = "disabled"; | |
992 | #address-cells = <1>; | |
993 | #size-cells = <1>; | |
994 | ranges = <0x0 0x32000 0x1000>; | |
995 | }; | |
996 | ||
997 | target-module@34000 { /* 0x4a234000, ap 117 76.1 */ | |
998 | compatible = "ti,sysc"; | |
999 | status = "disabled"; | |
1000 | #address-cells = <1>; | |
1001 | #size-cells = <1>; | |
1002 | ranges = <0x0 0x34000 0x1000>; | |
1003 | }; | |
1004 | ||
1005 | target-module@36000 { /* 0x4a236000, ap 119 62.0 */ | |
1006 | compatible = "ti,sysc"; | |
1007 | status = "disabled"; | |
1008 | #address-cells = <1>; | |
1009 | #size-cells = <1>; | |
1010 | ranges = <0x0 0x36000 0x1000>; | |
1011 | }; | |
1012 | }; | |
1013 | }; | |
1014 | ||
1015 | &l4_per1 { /* 0x48000000 */ | |
1016 | compatible = "ti,dra7-l4-per1", "simple-bus"; | |
1017 | reg = <0x48000000 0x800>, | |
1018 | <0x48000800 0x800>, | |
1019 | <0x48001000 0x400>, | |
1020 | <0x48001400 0x400>, | |
1021 | <0x48001800 0x400>, | |
1022 | <0x48001c00 0x400>; | |
1023 | reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; | |
1024 | #address-cells = <1>; | |
1025 | #size-cells = <1>; | |
1026 | ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ | |
1027 | <0x00200000 0x48200000 0x200000>; /* segment 1 */ | |
1028 | ||
1029 | segment@0 { /* 0x48000000 */ | |
1030 | compatible = "simple-bus"; | |
1031 | #address-cells = <1>; | |
1032 | #size-cells = <1>; | |
1033 | ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ | |
1034 | <0x00001000 0x00001000 0x000400>, /* ap 1 */ | |
1035 | <0x00000800 0x00000800 0x000800>, /* ap 2 */ | |
1036 | <0x00020000 0x00020000 0x001000>, /* ap 3 */ | |
1037 | <0x00021000 0x00021000 0x001000>, /* ap 4 */ | |
1038 | <0x00032000 0x00032000 0x001000>, /* ap 5 */ | |
1039 | <0x00033000 0x00033000 0x001000>, /* ap 6 */ | |
1040 | <0x00034000 0x00034000 0x001000>, /* ap 7 */ | |
1041 | <0x00035000 0x00035000 0x001000>, /* ap 8 */ | |
1042 | <0x00036000 0x00036000 0x001000>, /* ap 9 */ | |
1043 | <0x00037000 0x00037000 0x001000>, /* ap 10 */ | |
1044 | <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ | |
1045 | <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ | |
1046 | <0x00055000 0x00055000 0x001000>, /* ap 13 */ | |
1047 | <0x00056000 0x00056000 0x001000>, /* ap 14 */ | |
1048 | <0x00057000 0x00057000 0x001000>, /* ap 15 */ | |
1049 | <0x00058000 0x00058000 0x001000>, /* ap 16 */ | |
1050 | <0x00059000 0x00059000 0x001000>, /* ap 17 */ | |
1051 | <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ | |
1052 | <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ | |
1053 | <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ | |
1054 | <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ | |
1055 | <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ | |
1056 | <0x00060000 0x00060000 0x001000>, /* ap 23 */ | |
1057 | <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ | |
1058 | <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ | |
1059 | <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ | |
1060 | <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ | |
1061 | <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ | |
1062 | <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ | |
1063 | <0x00070000 0x00070000 0x001000>, /* ap 30 */ | |
1064 | <0x00071000 0x00071000 0x001000>, /* ap 31 */ | |
1065 | <0x00072000 0x00072000 0x001000>, /* ap 32 */ | |
1066 | <0x00073000 0x00073000 0x001000>, /* ap 33 */ | |
1067 | <0x00061000 0x00061000 0x001000>, /* ap 34 */ | |
1068 | <0x00053000 0x00053000 0x001000>, /* ap 35 */ | |
1069 | <0x00054000 0x00054000 0x001000>, /* ap 36 */ | |
1070 | <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ | |
1071 | <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ | |
1072 | <0x00078000 0x00078000 0x001000>, /* ap 39 */ | |
1073 | <0x00079000 0x00079000 0x001000>, /* ap 40 */ | |
1074 | <0x00086000 0x00086000 0x001000>, /* ap 41 */ | |
1075 | <0x00087000 0x00087000 0x001000>, /* ap 42 */ | |
1076 | <0x00088000 0x00088000 0x001000>, /* ap 43 */ | |
1077 | <0x00089000 0x00089000 0x001000>, /* ap 44 */ | |
1078 | <0x00051000 0x00051000 0x001000>, /* ap 45 */ | |
1079 | <0x00052000 0x00052000 0x001000>, /* ap 46 */ | |
1080 | <0x00098000 0x00098000 0x001000>, /* ap 47 */ | |
1081 | <0x00099000 0x00099000 0x001000>, /* ap 48 */ | |
1082 | <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ | |
1083 | <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ | |
1084 | <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ | |
1085 | <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ | |
1086 | <0x00068000 0x00068000 0x001000>, /* ap 53 */ | |
1087 | <0x00069000 0x00069000 0x001000>, /* ap 54 */ | |
1088 | <0x00090000 0x00090000 0x002000>, /* ap 55 */ | |
1089 | <0x00092000 0x00092000 0x001000>, /* ap 56 */ | |
1090 | <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ | |
1091 | <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ | |
1092 | <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ | |
1093 | <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ | |
1094 | <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ | |
1095 | <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ | |
1096 | <0x00066000 0x00066000 0x001000>, /* ap 63 */ | |
1097 | <0x00067000 0x00067000 0x001000>, /* ap 64 */ | |
1098 | <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ | |
1099 | <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ | |
1100 | <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ | |
1101 | <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ | |
1102 | <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ | |
1103 | <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ | |
1104 | <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ | |
1105 | <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ | |
1106 | <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ | |
1107 | <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ | |
1108 | <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ | |
1109 | <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ | |
1110 | <0x00001400 0x00001400 0x000400>, /* ap 77 */ | |
1111 | <0x00001800 0x00001800 0x000400>, /* ap 78 */ | |
1112 | <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ | |
1113 | <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ | |
1114 | <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ | |
1115 | <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ | |
1116 | <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ | |
1117 | <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ | |
1118 | ||
1119 | target-module@20000 { /* 0x48020000, ap 3 04.0 */ | |
1120 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1121 | ti,hwmods = "uart3"; | |
1122 | reg = <0x20050 0x4>, | |
1123 | <0x20054 0x4>, | |
1124 | <0x20058 0x4>; | |
1125 | reg-names = "rev", "sysc", "syss"; | |
1126 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
1127 | SYSC_OMAP2_SOFTRESET | | |
1128 | SYSC_OMAP2_AUTOIDLE)>; | |
1129 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1130 | <SYSC_IDLE_NO>, | |
1131 | <SYSC_IDLE_SMART>, | |
1132 | <SYSC_IDLE_SMART_WKUP>; | |
1133 | ti,syss-mask = <1>; | |
549fce06 TL |
1134 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ |
1135 | clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>; | |
1136 | clock-names = "fck"; | |
1137 | #address-cells = <1>; | |
1138 | #size-cells = <1>; | |
1139 | ranges = <0x0 0x20000 0x1000>; | |
4ed0dfe3 TL |
1140 | |
1141 | uart3: serial@0 { | |
1142 | compatible = "ti,dra742-uart", "ti,omap4-uart"; | |
1143 | reg = <0x0 0x100>; | |
1144 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
1145 | clock-frequency = <48000000>; | |
1146 | status = "disabled"; | |
1147 | dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; | |
1148 | dma-names = "tx", "rx"; | |
1149 | }; | |
549fce06 TL |
1150 | }; |
1151 | ||
1152 | target-module@32000 { /* 0x48032000, ap 5 3e.0 */ | |
1153 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
1154 | ti,hwmods = "timer2"; | |
1155 | reg = <0x32000 0x4>, | |
1156 | <0x32010 0x4>; | |
1157 | reg-names = "rev", "sysc"; | |
1158 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
1159 | SYSC_OMAP4_SOFTRESET)>; | |
1160 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1161 | <SYSC_IDLE_NO>, | |
1162 | <SYSC_IDLE_SMART>, | |
1163 | <SYSC_IDLE_SMART_WKUP>; | |
1164 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1165 | clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>; | |
1166 | clock-names = "fck"; | |
1167 | #address-cells = <1>; | |
1168 | #size-cells = <1>; | |
1169 | ranges = <0x0 0x32000 0x1000>; | |
4ed0dfe3 TL |
1170 | |
1171 | timer2: timer@0 { | |
1172 | compatible = "ti,omap5430-timer"; | |
1173 | reg = <0x0 0x80>; | |
1174 | clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>; | |
1175 | clock-names = "fck"; | |
1176 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
1177 | }; | |
549fce06 TL |
1178 | }; |
1179 | ||
1180 | target-module@34000 { /* 0x48034000, ap 7 46.0 */ | |
1181 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
1182 | ti,hwmods = "timer3"; | |
1183 | reg = <0x34000 0x4>, | |
1184 | <0x34010 0x4>; | |
1185 | reg-names = "rev", "sysc"; | |
1186 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
1187 | SYSC_OMAP4_SOFTRESET)>; | |
1188 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1189 | <SYSC_IDLE_NO>, | |
1190 | <SYSC_IDLE_SMART>, | |
1191 | <SYSC_IDLE_SMART_WKUP>; | |
1192 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1193 | clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>; | |
1194 | clock-names = "fck"; | |
1195 | #address-cells = <1>; | |
1196 | #size-cells = <1>; | |
1197 | ranges = <0x0 0x34000 0x1000>; | |
4ed0dfe3 TL |
1198 | |
1199 | timer3: timer@0 { | |
1200 | compatible = "ti,omap5430-timer"; | |
1201 | reg = <0x0 0x80>; | |
1202 | clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>; | |
1203 | clock-names = "fck"; | |
1204 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
1205 | }; | |
549fce06 TL |
1206 | }; |
1207 | ||
1208 | target-module@36000 { /* 0x48036000, ap 9 4e.0 */ | |
1209 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
1210 | ti,hwmods = "timer4"; | |
1211 | reg = <0x36000 0x4>, | |
1212 | <0x36010 0x4>; | |
1213 | reg-names = "rev", "sysc"; | |
1214 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
1215 | SYSC_OMAP4_SOFTRESET)>; | |
1216 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1217 | <SYSC_IDLE_NO>, | |
1218 | <SYSC_IDLE_SMART>, | |
1219 | <SYSC_IDLE_SMART_WKUP>; | |
1220 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1221 | clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>; | |
1222 | clock-names = "fck"; | |
1223 | #address-cells = <1>; | |
1224 | #size-cells = <1>; | |
1225 | ranges = <0x0 0x36000 0x1000>; | |
4ed0dfe3 TL |
1226 | |
1227 | timer4: timer@0 { | |
1228 | compatible = "ti,omap5430-timer"; | |
1229 | reg = <0x0 0x80>; | |
1230 | clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>; | |
1231 | clock-names = "fck"; | |
1232 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
1233 | }; | |
549fce06 TL |
1234 | }; |
1235 | ||
1236 | target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ | |
1237 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
1238 | ti,hwmods = "timer9"; | |
1239 | reg = <0x3e000 0x4>, | |
1240 | <0x3e010 0x4>; | |
1241 | reg-names = "rev", "sysc"; | |
1242 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
1243 | SYSC_OMAP4_SOFTRESET)>; | |
1244 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1245 | <SYSC_IDLE_NO>, | |
1246 | <SYSC_IDLE_SMART>, | |
1247 | <SYSC_IDLE_SMART_WKUP>; | |
1248 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1249 | clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>; | |
1250 | clock-names = "fck"; | |
1251 | #address-cells = <1>; | |
1252 | #size-cells = <1>; | |
1253 | ranges = <0x0 0x3e000 0x1000>; | |
4ed0dfe3 TL |
1254 | |
1255 | timer9: timer@0 { | |
1256 | compatible = "ti,omap5430-timer"; | |
1257 | reg = <0x0 0x80>; | |
1258 | clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>; | |
1259 | clock-names = "fck"; | |
1260 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
1261 | }; | |
549fce06 TL |
1262 | }; |
1263 | ||
2e8647bb | 1264 | gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */ |
549fce06 TL |
1265 | compatible = "ti,sysc-omap2", "ti,sysc"; |
1266 | ti,hwmods = "gpio7"; | |
1267 | reg = <0x51000 0x4>, | |
1268 | <0x51010 0x4>, | |
1269 | <0x51114 0x4>; | |
1270 | reg-names = "rev", "sysc", "syss"; | |
1271 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
1272 | SYSC_OMAP2_SOFTRESET | | |
1273 | SYSC_OMAP2_AUTOIDLE)>; | |
1274 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1275 | <SYSC_IDLE_NO>, | |
1276 | <SYSC_IDLE_SMART>, | |
1277 | <SYSC_IDLE_SMART_WKUP>; | |
1278 | ti,syss-mask = <1>; | |
549fce06 TL |
1279 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ |
1280 | clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>, | |
1281 | <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>; | |
1282 | clock-names = "fck", "dbclk"; | |
1283 | #address-cells = <1>; | |
1284 | #size-cells = <1>; | |
1285 | ranges = <0x0 0x51000 0x1000>; | |
4ed0dfe3 TL |
1286 | |
1287 | gpio7: gpio@0 { | |
1288 | compatible = "ti,omap4-gpio"; | |
1289 | reg = <0x0 0x200>; | |
1290 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
1291 | gpio-controller; | |
1292 | #gpio-cells = <2>; | |
1293 | interrupt-controller; | |
1294 | #interrupt-cells = <2>; | |
1295 | }; | |
549fce06 TL |
1296 | }; |
1297 | ||
1298 | target-module@53000 { /* 0x48053000, ap 35 36.0 */ | |
1299 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1300 | ti,hwmods = "gpio8"; | |
1301 | reg = <0x53000 0x4>, | |
1302 | <0x53010 0x4>, | |
1303 | <0x53114 0x4>; | |
1304 | reg-names = "rev", "sysc", "syss"; | |
1305 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
1306 | SYSC_OMAP2_SOFTRESET | | |
1307 | SYSC_OMAP2_AUTOIDLE)>; | |
1308 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1309 | <SYSC_IDLE_NO>, | |
1310 | <SYSC_IDLE_SMART>, | |
1311 | <SYSC_IDLE_SMART_WKUP>; | |
1312 | ti,syss-mask = <1>; | |
1313 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1314 | clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>, | |
1315 | <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>; | |
1316 | clock-names = "fck", "dbclk"; | |
1317 | #address-cells = <1>; | |
1318 | #size-cells = <1>; | |
1319 | ranges = <0x0 0x53000 0x1000>; | |
4ed0dfe3 TL |
1320 | |
1321 | gpio8: gpio@0 { | |
1322 | compatible = "ti,omap4-gpio"; | |
1323 | reg = <0x0 0x200>; | |
1324 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
1325 | gpio-controller; | |
1326 | #gpio-cells = <2>; | |
1327 | interrupt-controller; | |
1328 | #interrupt-cells = <2>; | |
1329 | }; | |
549fce06 TL |
1330 | }; |
1331 | ||
1332 | target-module@55000 { /* 0x48055000, ap 13 0e.0 */ | |
1333 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1334 | ti,hwmods = "gpio2"; | |
1335 | reg = <0x55000 0x4>, | |
1336 | <0x55010 0x4>, | |
1337 | <0x55114 0x4>; | |
1338 | reg-names = "rev", "sysc", "syss"; | |
1339 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
1340 | SYSC_OMAP2_SOFTRESET | | |
1341 | SYSC_OMAP2_AUTOIDLE)>; | |
1342 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1343 | <SYSC_IDLE_NO>, | |
1344 | <SYSC_IDLE_SMART>, | |
1345 | <SYSC_IDLE_SMART_WKUP>; | |
1346 | ti,syss-mask = <1>; | |
1347 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1348 | clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>, | |
1349 | <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>; | |
1350 | clock-names = "fck", "dbclk"; | |
1351 | #address-cells = <1>; | |
1352 | #size-cells = <1>; | |
1353 | ranges = <0x0 0x55000 0x1000>; | |
4ed0dfe3 TL |
1354 | |
1355 | gpio2: gpio@0 { | |
1356 | compatible = "ti,omap4-gpio"; | |
1357 | reg = <0x0 0x200>; | |
1358 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
1359 | gpio-controller; | |
1360 | #gpio-cells = <2>; | |
1361 | interrupt-controller; | |
1362 | #interrupt-cells = <2>; | |
1363 | }; | |
549fce06 TL |
1364 | }; |
1365 | ||
1366 | target-module@57000 { /* 0x48057000, ap 15 06.0 */ | |
1367 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1368 | ti,hwmods = "gpio3"; | |
1369 | reg = <0x57000 0x4>, | |
1370 | <0x57010 0x4>, | |
1371 | <0x57114 0x4>; | |
1372 | reg-names = "rev", "sysc", "syss"; | |
1373 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
1374 | SYSC_OMAP2_SOFTRESET | | |
1375 | SYSC_OMAP2_AUTOIDLE)>; | |
1376 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1377 | <SYSC_IDLE_NO>, | |
1378 | <SYSC_IDLE_SMART>, | |
1379 | <SYSC_IDLE_SMART_WKUP>; | |
1380 | ti,syss-mask = <1>; | |
1381 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1382 | clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>, | |
1383 | <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>; | |
1384 | clock-names = "fck", "dbclk"; | |
1385 | #address-cells = <1>; | |
1386 | #size-cells = <1>; | |
1387 | ranges = <0x0 0x57000 0x1000>; | |
4ed0dfe3 TL |
1388 | |
1389 | gpio3: gpio@0 { | |
1390 | compatible = "ti,omap4-gpio"; | |
1391 | reg = <0x0 0x200>; | |
1392 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
1393 | gpio-controller; | |
1394 | #gpio-cells = <2>; | |
1395 | interrupt-controller; | |
1396 | #interrupt-cells = <2>; | |
1397 | }; | |
549fce06 TL |
1398 | }; |
1399 | ||
1400 | target-module@59000 { /* 0x48059000, ap 17 16.0 */ | |
1401 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1402 | ti,hwmods = "gpio4"; | |
1403 | reg = <0x59000 0x4>, | |
1404 | <0x59010 0x4>, | |
1405 | <0x59114 0x4>; | |
1406 | reg-names = "rev", "sysc", "syss"; | |
1407 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
1408 | SYSC_OMAP2_SOFTRESET | | |
1409 | SYSC_OMAP2_AUTOIDLE)>; | |
1410 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1411 | <SYSC_IDLE_NO>, | |
1412 | <SYSC_IDLE_SMART>, | |
1413 | <SYSC_IDLE_SMART_WKUP>; | |
1414 | ti,syss-mask = <1>; | |
1415 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1416 | clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>, | |
1417 | <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>; | |
1418 | clock-names = "fck", "dbclk"; | |
1419 | #address-cells = <1>; | |
1420 | #size-cells = <1>; | |
1421 | ranges = <0x0 0x59000 0x1000>; | |
4ed0dfe3 TL |
1422 | |
1423 | gpio4: gpio@0 { | |
1424 | compatible = "ti,omap4-gpio"; | |
1425 | reg = <0x0 0x200>; | |
1426 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
1427 | gpio-controller; | |
1428 | #gpio-cells = <2>; | |
1429 | interrupt-controller; | |
1430 | #interrupt-cells = <2>; | |
1431 | }; | |
549fce06 TL |
1432 | }; |
1433 | ||
1434 | target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ | |
1435 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1436 | ti,hwmods = "gpio5"; | |
1437 | reg = <0x5b000 0x4>, | |
1438 | <0x5b010 0x4>, | |
1439 | <0x5b114 0x4>; | |
1440 | reg-names = "rev", "sysc", "syss"; | |
1441 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
1442 | SYSC_OMAP2_SOFTRESET | | |
1443 | SYSC_OMAP2_AUTOIDLE)>; | |
1444 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1445 | <SYSC_IDLE_NO>, | |
1446 | <SYSC_IDLE_SMART>, | |
1447 | <SYSC_IDLE_SMART_WKUP>; | |
1448 | ti,syss-mask = <1>; | |
1449 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1450 | clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>, | |
1451 | <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>; | |
1452 | clock-names = "fck", "dbclk"; | |
1453 | #address-cells = <1>; | |
1454 | #size-cells = <1>; | |
1455 | ranges = <0x0 0x5b000 0x1000>; | |
4ed0dfe3 TL |
1456 | |
1457 | gpio5: gpio@0 { | |
1458 | compatible = "ti,omap4-gpio"; | |
1459 | reg = <0x0 0x200>; | |
1460 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
1461 | gpio-controller; | |
1462 | #gpio-cells = <2>; | |
1463 | interrupt-controller; | |
1464 | #interrupt-cells = <2>; | |
1465 | }; | |
549fce06 TL |
1466 | }; |
1467 | ||
1468 | target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ | |
1469 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1470 | ti,hwmods = "gpio6"; | |
1471 | reg = <0x5d000 0x4>, | |
1472 | <0x5d010 0x4>, | |
1473 | <0x5d114 0x4>; | |
1474 | reg-names = "rev", "sysc", "syss"; | |
1475 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
1476 | SYSC_OMAP2_SOFTRESET | | |
1477 | SYSC_OMAP2_AUTOIDLE)>; | |
1478 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1479 | <SYSC_IDLE_NO>, | |
1480 | <SYSC_IDLE_SMART>, | |
1481 | <SYSC_IDLE_SMART_WKUP>; | |
1482 | ti,syss-mask = <1>; | |
1483 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1484 | clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>, | |
1485 | <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>; | |
1486 | clock-names = "fck", "dbclk"; | |
1487 | #address-cells = <1>; | |
1488 | #size-cells = <1>; | |
1489 | ranges = <0x0 0x5d000 0x1000>; | |
4ed0dfe3 TL |
1490 | |
1491 | gpio6: gpio@0 { | |
1492 | compatible = "ti,omap4-gpio"; | |
1493 | reg = <0x0 0x200>; | |
1494 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
1495 | gpio-controller; | |
1496 | #gpio-cells = <2>; | |
1497 | interrupt-controller; | |
1498 | #interrupt-cells = <2>; | |
1499 | }; | |
549fce06 TL |
1500 | }; |
1501 | ||
1502 | target-module@60000 { /* 0x48060000, ap 23 32.0 */ | |
1503 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1504 | ti,hwmods = "i2c3"; | |
1505 | reg = <0x60000 0x8>, | |
1506 | <0x60010 0x8>, | |
1507 | <0x60090 0x8>; | |
1508 | reg-names = "rev", "sysc", "syss"; | |
1509 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | | |
1510 | SYSC_OMAP2_ENAWAKEUP | | |
1511 | SYSC_OMAP2_SOFTRESET | | |
1512 | SYSC_OMAP2_AUTOIDLE)>; | |
1513 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1514 | <SYSC_IDLE_NO>, | |
1515 | <SYSC_IDLE_SMART>, | |
1516 | <SYSC_IDLE_SMART_WKUP>; | |
1517 | ti,syss-mask = <1>; | |
1518 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1519 | clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>; | |
1520 | clock-names = "fck"; | |
1521 | #address-cells = <1>; | |
1522 | #size-cells = <1>; | |
1523 | ranges = <0x0 0x60000 0x1000>; | |
4ed0dfe3 TL |
1524 | |
1525 | i2c3: i2c@0 { | |
1526 | compatible = "ti,omap4-i2c"; | |
1527 | reg = <0x0 0x100>; | |
1528 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
1529 | #address-cells = <1>; | |
1530 | #size-cells = <0>; | |
1531 | status = "disabled"; | |
1532 | }; | |
549fce06 TL |
1533 | }; |
1534 | ||
1535 | target-module@66000 { /* 0x48066000, ap 63 14.0 */ | |
1536 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1537 | ti,hwmods = "uart5"; | |
1538 | reg = <0x66050 0x4>, | |
1539 | <0x66054 0x4>, | |
1540 | <0x66058 0x4>; | |
1541 | reg-names = "rev", "sysc", "syss"; | |
1542 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
1543 | SYSC_OMAP2_SOFTRESET | | |
1544 | SYSC_OMAP2_AUTOIDLE)>; | |
1545 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1546 | <SYSC_IDLE_NO>, | |
1547 | <SYSC_IDLE_SMART>, | |
1548 | <SYSC_IDLE_SMART_WKUP>; | |
1549 | ti,syss-mask = <1>; | |
1550 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1551 | clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>; | |
1552 | clock-names = "fck"; | |
1553 | #address-cells = <1>; | |
1554 | #size-cells = <1>; | |
1555 | ranges = <0x0 0x66000 0x1000>; | |
4ed0dfe3 TL |
1556 | |
1557 | uart5: serial@0 { | |
1558 | compatible = "ti,dra742-uart", "ti,omap4-uart"; | |
1559 | reg = <0x0 0x100>; | |
1560 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
1561 | clock-frequency = <48000000>; | |
1562 | status = "disabled"; | |
1563 | dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; | |
1564 | dma-names = "tx", "rx"; | |
1565 | }; | |
549fce06 TL |
1566 | }; |
1567 | ||
1568 | target-module@68000 { /* 0x48068000, ap 53 1c.0 */ | |
1569 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1570 | ti,hwmods = "uart6"; | |
1571 | reg = <0x68050 0x4>, | |
1572 | <0x68054 0x4>, | |
1573 | <0x68058 0x4>; | |
1574 | reg-names = "rev", "sysc", "syss"; | |
1575 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
1576 | SYSC_OMAP2_SOFTRESET | | |
1577 | SYSC_OMAP2_AUTOIDLE)>; | |
1578 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1579 | <SYSC_IDLE_NO>, | |
1580 | <SYSC_IDLE_SMART>, | |
1581 | <SYSC_IDLE_SMART_WKUP>; | |
1582 | ti,syss-mask = <1>; | |
1583 | /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ | |
1584 | clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>; | |
1585 | clock-names = "fck"; | |
1586 | #address-cells = <1>; | |
1587 | #size-cells = <1>; | |
1588 | ranges = <0x0 0x68000 0x1000>; | |
4ed0dfe3 TL |
1589 | |
1590 | uart6: serial@0 { | |
1591 | compatible = "ti,dra742-uart", "ti,omap4-uart"; | |
1592 | reg = <0x0 0x100>; | |
1593 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
1594 | clock-frequency = <48000000>; | |
1595 | status = "disabled"; | |
1596 | dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; | |
1597 | dma-names = "tx", "rx"; | |
1598 | }; | |
549fce06 TL |
1599 | }; |
1600 | ||
1601 | target-module@6a000 { /* 0x4806a000, ap 24 24.0 */ | |
1602 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1603 | ti,hwmods = "uart1"; | |
1604 | reg = <0x6a050 0x4>, | |
1605 | <0x6a054 0x4>, | |
1606 | <0x6a058 0x4>; | |
1607 | reg-names = "rev", "sysc", "syss"; | |
1608 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
1609 | SYSC_OMAP2_SOFTRESET | | |
1610 | SYSC_OMAP2_AUTOIDLE)>; | |
1611 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1612 | <SYSC_IDLE_NO>, | |
1613 | <SYSC_IDLE_SMART>, | |
1614 | <SYSC_IDLE_SMART_WKUP>; | |
1615 | ti,syss-mask = <1>; | |
1616 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1617 | clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>; | |
1618 | clock-names = "fck"; | |
1619 | #address-cells = <1>; | |
1620 | #size-cells = <1>; | |
1621 | ranges = <0x0 0x6a000 0x1000>; | |
4ed0dfe3 TL |
1622 | |
1623 | uart1: serial@0 { | |
1624 | compatible = "ti,dra742-uart", "ti,omap4-uart"; | |
1625 | reg = <0x0 0x100>; | |
1626 | interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
1627 | clock-frequency = <48000000>; | |
1628 | status = "disabled"; | |
1629 | dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; | |
1630 | dma-names = "tx", "rx"; | |
1631 | }; | |
549fce06 TL |
1632 | }; |
1633 | ||
1634 | target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */ | |
1635 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1636 | ti,hwmods = "uart2"; | |
1637 | reg = <0x6c050 0x4>, | |
1638 | <0x6c054 0x4>, | |
1639 | <0x6c058 0x4>; | |
1640 | reg-names = "rev", "sysc", "syss"; | |
1641 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
1642 | SYSC_OMAP2_SOFTRESET | | |
1643 | SYSC_OMAP2_AUTOIDLE)>; | |
1644 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1645 | <SYSC_IDLE_NO>, | |
1646 | <SYSC_IDLE_SMART>, | |
1647 | <SYSC_IDLE_SMART_WKUP>; | |
1648 | ti,syss-mask = <1>; | |
1649 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1650 | clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>; | |
1651 | clock-names = "fck"; | |
1652 | #address-cells = <1>; | |
1653 | #size-cells = <1>; | |
1654 | ranges = <0x0 0x6c000 0x1000>; | |
4ed0dfe3 TL |
1655 | |
1656 | uart2: serial@0 { | |
1657 | compatible = "ti,dra742-uart", "ti,omap4-uart"; | |
1658 | reg = <0x0 0x100>; | |
1659 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | |
1660 | clock-frequency = <48000000>; | |
1661 | status = "disabled"; | |
1662 | dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; | |
1663 | dma-names = "tx", "rx"; | |
1664 | }; | |
549fce06 TL |
1665 | }; |
1666 | ||
1667 | target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */ | |
1668 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1669 | ti,hwmods = "uart4"; | |
1670 | reg = <0x6e050 0x4>, | |
1671 | <0x6e054 0x4>, | |
1672 | <0x6e058 0x4>; | |
1673 | reg-names = "rev", "sysc", "syss"; | |
1674 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
1675 | SYSC_OMAP2_SOFTRESET | | |
1676 | SYSC_OMAP2_AUTOIDLE)>; | |
1677 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1678 | <SYSC_IDLE_NO>, | |
1679 | <SYSC_IDLE_SMART>, | |
1680 | <SYSC_IDLE_SMART_WKUP>; | |
1681 | ti,syss-mask = <1>; | |
1682 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1683 | clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>; | |
1684 | clock-names = "fck"; | |
1685 | #address-cells = <1>; | |
1686 | #size-cells = <1>; | |
1687 | ranges = <0x0 0x6e000 0x1000>; | |
4ed0dfe3 TL |
1688 | |
1689 | uart4: serial@0 { | |
1690 | compatible = "ti,dra742-uart", "ti,omap4-uart"; | |
1691 | reg = <0x0 0x100>; | |
1692 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; | |
1693 | clock-frequency = <48000000>; | |
1694 | status = "disabled"; | |
1695 | dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; | |
1696 | dma-names = "tx", "rx"; | |
1697 | }; | |
549fce06 TL |
1698 | }; |
1699 | ||
1700 | target-module@70000 { /* 0x48070000, ap 30 22.0 */ | |
1701 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1702 | ti,hwmods = "i2c1"; | |
1703 | reg = <0x70000 0x8>, | |
1704 | <0x70010 0x8>, | |
1705 | <0x70090 0x8>; | |
1706 | reg-names = "rev", "sysc", "syss"; | |
1707 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | | |
1708 | SYSC_OMAP2_ENAWAKEUP | | |
1709 | SYSC_OMAP2_SOFTRESET | | |
1710 | SYSC_OMAP2_AUTOIDLE)>; | |
1711 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1712 | <SYSC_IDLE_NO>, | |
1713 | <SYSC_IDLE_SMART>, | |
1714 | <SYSC_IDLE_SMART_WKUP>; | |
1715 | ti,syss-mask = <1>; | |
1716 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1717 | clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>; | |
1718 | clock-names = "fck"; | |
1719 | #address-cells = <1>; | |
1720 | #size-cells = <1>; | |
1721 | ranges = <0x0 0x70000 0x1000>; | |
4ed0dfe3 TL |
1722 | |
1723 | i2c1: i2c@0 { | |
1724 | compatible = "ti,omap4-i2c"; | |
1725 | reg = <0x0 0x100>; | |
1726 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
1727 | #address-cells = <1>; | |
1728 | #size-cells = <0>; | |
1729 | status = "disabled"; | |
1730 | }; | |
549fce06 TL |
1731 | }; |
1732 | ||
1733 | target-module@72000 { /* 0x48072000, ap 32 2a.0 */ | |
1734 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1735 | ti,hwmods = "i2c2"; | |
1736 | reg = <0x72000 0x8>, | |
1737 | <0x72010 0x8>, | |
1738 | <0x72090 0x8>; | |
1739 | reg-names = "rev", "sysc", "syss"; | |
1740 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | | |
1741 | SYSC_OMAP2_ENAWAKEUP | | |
1742 | SYSC_OMAP2_SOFTRESET | | |
1743 | SYSC_OMAP2_AUTOIDLE)>; | |
1744 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1745 | <SYSC_IDLE_NO>, | |
1746 | <SYSC_IDLE_SMART>, | |
1747 | <SYSC_IDLE_SMART_WKUP>; | |
1748 | ti,syss-mask = <1>; | |
1749 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1750 | clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>; | |
1751 | clock-names = "fck"; | |
1752 | #address-cells = <1>; | |
1753 | #size-cells = <1>; | |
1754 | ranges = <0x0 0x72000 0x1000>; | |
4ed0dfe3 TL |
1755 | |
1756 | i2c2: i2c@0 { | |
1757 | compatible = "ti,omap4-i2c"; | |
1758 | reg = <0x0 0x100>; | |
1759 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
1760 | #address-cells = <1>; | |
1761 | #size-cells = <0>; | |
1762 | status = "disabled"; | |
1763 | }; | |
549fce06 TL |
1764 | }; |
1765 | ||
1766 | target-module@78000 { /* 0x48078000, ap 39 0a.0 */ | |
1767 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1768 | ti,hwmods = "elm"; | |
1769 | reg = <0x78000 0x4>, | |
1770 | <0x78010 0x4>, | |
1771 | <0x78014 0x4>; | |
1772 | reg-names = "rev", "sysc", "syss"; | |
1773 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | | |
1774 | SYSC_OMAP2_SOFTRESET | | |
1775 | SYSC_OMAP2_AUTOIDLE)>; | |
1776 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1777 | <SYSC_IDLE_NO>, | |
1778 | <SYSC_IDLE_SMART>, | |
1779 | <SYSC_IDLE_SMART_WKUP>; | |
1780 | ti,syss-mask = <1>; | |
1781 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1782 | clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>; | |
1783 | clock-names = "fck"; | |
1784 | #address-cells = <1>; | |
1785 | #size-cells = <1>; | |
1786 | ranges = <0x0 0x78000 0x1000>; | |
4ed0dfe3 TL |
1787 | |
1788 | elm: elm@0 { | |
1789 | compatible = "ti,am3352-elm"; | |
1790 | reg = <0x0 0xfc0>; /* device IO registers */ | |
1791 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
1792 | status = "disabled"; | |
1793 | }; | |
549fce06 TL |
1794 | }; |
1795 | ||
1796 | target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */ | |
1797 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1798 | ti,hwmods = "i2c4"; | |
1799 | reg = <0x7a000 0x8>, | |
1800 | <0x7a010 0x8>, | |
1801 | <0x7a090 0x8>; | |
1802 | reg-names = "rev", "sysc", "syss"; | |
1803 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | | |
1804 | SYSC_OMAP2_ENAWAKEUP | | |
1805 | SYSC_OMAP2_SOFTRESET | | |
1806 | SYSC_OMAP2_AUTOIDLE)>; | |
1807 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1808 | <SYSC_IDLE_NO>, | |
1809 | <SYSC_IDLE_SMART>, | |
1810 | <SYSC_IDLE_SMART_WKUP>; | |
1811 | ti,syss-mask = <1>; | |
1812 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1813 | clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>; | |
1814 | clock-names = "fck"; | |
1815 | #address-cells = <1>; | |
1816 | #size-cells = <1>; | |
1817 | ranges = <0x0 0x7a000 0x1000>; | |
4ed0dfe3 TL |
1818 | |
1819 | i2c4: i2c@0 { | |
1820 | compatible = "ti,omap4-i2c"; | |
1821 | reg = <0x0 0x100>; | |
1822 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
1823 | #address-cells = <1>; | |
1824 | #size-cells = <0>; | |
1825 | status = "disabled"; | |
1826 | }; | |
549fce06 TL |
1827 | }; |
1828 | ||
1829 | target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */ | |
1830 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1831 | ti,hwmods = "i2c5"; | |
1832 | reg = <0x7c000 0x8>, | |
1833 | <0x7c010 0x8>, | |
1834 | <0x7c090 0x8>; | |
1835 | reg-names = "rev", "sysc", "syss"; | |
1836 | ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | | |
1837 | SYSC_OMAP2_ENAWAKEUP | | |
1838 | SYSC_OMAP2_SOFTRESET | | |
1839 | SYSC_OMAP2_AUTOIDLE)>; | |
1840 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1841 | <SYSC_IDLE_NO>, | |
1842 | <SYSC_IDLE_SMART>, | |
1843 | <SYSC_IDLE_SMART_WKUP>; | |
1844 | ti,syss-mask = <1>; | |
1845 | /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ | |
1846 | clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>; | |
1847 | clock-names = "fck"; | |
1848 | #address-cells = <1>; | |
1849 | #size-cells = <1>; | |
1850 | ranges = <0x0 0x7c000 0x1000>; | |
4ed0dfe3 TL |
1851 | |
1852 | i2c5: i2c@0 { | |
1853 | compatible = "ti,omap4-i2c"; | |
1854 | reg = <0x0 0x100>; | |
1855 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
1856 | #address-cells = <1>; | |
1857 | #size-cells = <0>; | |
1858 | status = "disabled"; | |
1859 | }; | |
549fce06 TL |
1860 | }; |
1861 | ||
1862 | target-module@86000 { /* 0x48086000, ap 41 5e.0 */ | |
1863 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
1864 | ti,hwmods = "timer10"; | |
1865 | reg = <0x86000 0x4>, | |
1866 | <0x86010 0x4>; | |
1867 | reg-names = "rev", "sysc"; | |
1868 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
1869 | SYSC_OMAP4_SOFTRESET)>; | |
1870 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1871 | <SYSC_IDLE_NO>, | |
1872 | <SYSC_IDLE_SMART>, | |
1873 | <SYSC_IDLE_SMART_WKUP>; | |
1874 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1875 | clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>; | |
1876 | clock-names = "fck"; | |
1877 | #address-cells = <1>; | |
1878 | #size-cells = <1>; | |
1879 | ranges = <0x0 0x86000 0x1000>; | |
4ed0dfe3 TL |
1880 | |
1881 | timer10: timer@0 { | |
1882 | compatible = "ti,omap5430-timer"; | |
1883 | reg = <0x0 0x80>; | |
1884 | clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>; | |
1885 | clock-names = "fck"; | |
1886 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
1887 | }; | |
549fce06 TL |
1888 | }; |
1889 | ||
1890 | target-module@88000 { /* 0x48088000, ap 43 66.0 */ | |
1891 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
1892 | ti,hwmods = "timer11"; | |
1893 | reg = <0x88000 0x4>, | |
1894 | <0x88010 0x4>; | |
1895 | reg-names = "rev", "sysc"; | |
1896 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
1897 | SYSC_OMAP4_SOFTRESET)>; | |
1898 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1899 | <SYSC_IDLE_NO>, | |
1900 | <SYSC_IDLE_SMART>, | |
1901 | <SYSC_IDLE_SMART_WKUP>; | |
1902 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1903 | clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>; | |
1904 | clock-names = "fck"; | |
1905 | #address-cells = <1>; | |
1906 | #size-cells = <1>; | |
1907 | ranges = <0x0 0x88000 0x1000>; | |
4ed0dfe3 TL |
1908 | |
1909 | timer11: timer@0 { | |
1910 | compatible = "ti,omap5430-timer"; | |
1911 | reg = <0x0 0x80>; | |
1912 | clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>; | |
1913 | clock-names = "fck"; | |
1914 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
1915 | }; | |
549fce06 TL |
1916 | }; |
1917 | ||
1918 | target-module@90000 { /* 0x48090000, ap 55 12.0 */ | |
1919 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
1920 | ti,hwmods = "rng"; | |
1921 | reg = <0x91fe0 0x4>, | |
1922 | <0x91fe4 0x4>; | |
1923 | reg-names = "rev", "sysc"; | |
1924 | ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; | |
1925 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1926 | <SYSC_IDLE_NO>; | |
1927 | /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ | |
1928 | clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>; | |
1929 | clock-names = "fck"; | |
1930 | #address-cells = <1>; | |
1931 | #size-cells = <1>; | |
1932 | ranges = <0x0 0x90000 0x2000>; | |
4ed0dfe3 TL |
1933 | |
1934 | rng: rng@0 { | |
1935 | compatible = "ti,omap4-rng"; | |
1936 | reg = <0x0 0x2000>; | |
1937 | interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; | |
1938 | clocks = <&l3_iclk_div>; | |
1939 | clock-names = "fck"; | |
1940 | }; | |
549fce06 TL |
1941 | }; |
1942 | ||
1943 | target-module@98000 { /* 0x48098000, ap 47 08.0 */ | |
1944 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
1945 | ti,hwmods = "mcspi1"; | |
1946 | reg = <0x98000 0x4>, | |
1947 | <0x98010 0x4>; | |
1948 | reg-names = "rev", "sysc"; | |
1949 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
1950 | SYSC_OMAP4_SOFTRESET)>; | |
1951 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1952 | <SYSC_IDLE_NO>, | |
1953 | <SYSC_IDLE_SMART>, | |
1954 | <SYSC_IDLE_SMART_WKUP>; | |
1955 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1956 | clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>; | |
1957 | clock-names = "fck"; | |
1958 | #address-cells = <1>; | |
1959 | #size-cells = <1>; | |
1960 | ranges = <0x0 0x98000 0x1000>; | |
4ed0dfe3 TL |
1961 | |
1962 | mcspi1: spi@0 { | |
1963 | compatible = "ti,omap4-mcspi"; | |
1964 | reg = <0x0 0x200>; | |
1965 | interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; | |
1966 | #address-cells = <1>; | |
1967 | #size-cells = <0>; | |
1968 | ti,spi-num-cs = <4>; | |
1969 | dmas = <&sdma_xbar 35>, | |
1970 | <&sdma_xbar 36>, | |
1971 | <&sdma_xbar 37>, | |
1972 | <&sdma_xbar 38>, | |
1973 | <&sdma_xbar 39>, | |
1974 | <&sdma_xbar 40>, | |
1975 | <&sdma_xbar 41>, | |
1976 | <&sdma_xbar 42>; | |
1977 | dma-names = "tx0", "rx0", "tx1", "rx1", | |
1978 | "tx2", "rx2", "tx3", "rx3"; | |
1979 | status = "disabled"; | |
1980 | }; | |
549fce06 TL |
1981 | }; |
1982 | ||
1983 | target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ | |
1984 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
1985 | ti,hwmods = "mcspi2"; | |
1986 | reg = <0x9a000 0x4>, | |
1987 | <0x9a010 0x4>; | |
1988 | reg-names = "rev", "sysc"; | |
1989 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
1990 | SYSC_OMAP4_SOFTRESET)>; | |
1991 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
1992 | <SYSC_IDLE_NO>, | |
1993 | <SYSC_IDLE_SMART>, | |
1994 | <SYSC_IDLE_SMART_WKUP>; | |
1995 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
1996 | clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>; | |
1997 | clock-names = "fck"; | |
1998 | #address-cells = <1>; | |
1999 | #size-cells = <1>; | |
2000 | ranges = <0x0 0x9a000 0x1000>; | |
4ed0dfe3 TL |
2001 | |
2002 | mcspi2: spi@0 { | |
2003 | compatible = "ti,omap4-mcspi"; | |
2004 | reg = <0x0 0x200>; | |
2005 | interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; | |
2006 | #address-cells = <1>; | |
2007 | #size-cells = <0>; | |
2008 | ti,spi-num-cs = <2>; | |
2009 | dmas = <&sdma_xbar 43>, | |
2010 | <&sdma_xbar 44>, | |
2011 | <&sdma_xbar 45>, | |
2012 | <&sdma_xbar 46>; | |
2013 | dma-names = "tx0", "rx0", "tx1", "rx1"; | |
2014 | status = "disabled"; | |
2015 | }; | |
549fce06 TL |
2016 | }; |
2017 | ||
2018 | target-module@9c000 { /* 0x4809c000, ap 51 38.0 */ | |
2019 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
2020 | ti,hwmods = "mmc1"; | |
2021 | reg = <0x9c000 0x4>, | |
2022 | <0x9c010 0x4>; | |
2023 | reg-names = "rev", "sysc"; | |
2024 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
2025 | SYSC_OMAP4_SOFTRESET)>; | |
2026 | ti,sysc-midle = <SYSC_IDLE_FORCE>, | |
2027 | <SYSC_IDLE_NO>, | |
2028 | <SYSC_IDLE_SMART>, | |
2029 | <SYSC_IDLE_SMART_WKUP>; | |
2030 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2031 | <SYSC_IDLE_NO>, | |
2032 | <SYSC_IDLE_SMART>, | |
2033 | <SYSC_IDLE_SMART_WKUP>; | |
2034 | /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ | |
2035 | clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>; | |
2036 | clock-names = "fck"; | |
2037 | #address-cells = <1>; | |
2038 | #size-cells = <1>; | |
2039 | ranges = <0x0 0x9c000 0x1000>; | |
4ed0dfe3 TL |
2040 | |
2041 | mmc1: mmc@0 { | |
2042 | compatible = "ti,dra7-sdhci"; | |
2043 | reg = <0x0 0x400>; | |
2044 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
2045 | status = "disabled"; | |
2046 | pbias-supply = <&pbias_mmc_reg>; | |
2047 | max-frequency = <192000000>; | |
2048 | mmc-ddr-1_8v; | |
2049 | mmc-ddr-3_3v; | |
2050 | }; | |
549fce06 TL |
2051 | }; |
2052 | ||
2053 | target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ | |
2054 | compatible = "ti,sysc"; | |
2055 | status = "disabled"; | |
2056 | #address-cells = <1>; | |
2057 | #size-cells = <1>; | |
2058 | ranges = <0x0 0xa2000 0x1000>; | |
2059 | }; | |
2060 | ||
2061 | target-module@a4000 { /* 0x480a4000, ap 57 42.0 */ | |
2062 | compatible = "ti,sysc"; | |
2063 | status = "disabled"; | |
2064 | #address-cells = <1>; | |
2065 | #size-cells = <1>; | |
2066 | ranges = <0x00000000 0x000a4000 0x00001000>, | |
2067 | <0x00001000 0x000a5000 0x00001000>; | |
2068 | }; | |
2069 | ||
2070 | target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */ | |
2071 | compatible = "ti,sysc"; | |
2072 | status = "disabled"; | |
2073 | #address-cells = <1>; | |
2074 | #size-cells = <1>; | |
2075 | ranges = <0x0 0xa8000 0x4000>; | |
2076 | }; | |
2077 | ||
2078 | target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ | |
2079 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
2080 | ti,hwmods = "mmc3"; | |
2081 | reg = <0xad000 0x4>, | |
2082 | <0xad010 0x4>; | |
2083 | reg-names = "rev", "sysc"; | |
2084 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
2085 | SYSC_OMAP4_SOFTRESET)>; | |
2086 | ti,sysc-midle = <SYSC_IDLE_FORCE>, | |
2087 | <SYSC_IDLE_NO>, | |
2088 | <SYSC_IDLE_SMART>, | |
2089 | <SYSC_IDLE_SMART_WKUP>; | |
2090 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2091 | <SYSC_IDLE_NO>, | |
2092 | <SYSC_IDLE_SMART>, | |
2093 | <SYSC_IDLE_SMART_WKUP>; | |
2094 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
2095 | clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>; | |
2096 | clock-names = "fck"; | |
2097 | #address-cells = <1>; | |
2098 | #size-cells = <1>; | |
2099 | ranges = <0x0 0xad000 0x1000>; | |
4ed0dfe3 TL |
2100 | |
2101 | mmc3: mmc@0 { | |
2102 | compatible = "ti,dra7-sdhci"; | |
2103 | reg = <0x0 0x400>; | |
2104 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
2105 | status = "disabled"; | |
2106 | /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ | |
2107 | max-frequency = <64000000>; | |
2108 | /* SDMA is not supported */ | |
2109 | sdhci-caps-mask = <0x0 0x400000>; | |
2110 | }; | |
549fce06 TL |
2111 | }; |
2112 | ||
2113 | target-module@b2000 { /* 0x480b2000, ap 37 52.0 */ | |
2114 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
2115 | ti,hwmods = "hdq1w"; | |
2116 | reg = <0xb2000 0x4>, | |
2117 | <0xb2014 0x4>, | |
2118 | <0xb2018 0x4>; | |
2119 | reg-names = "rev", "sysc", "syss"; | |
2120 | ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | | |
2121 | SYSC_OMAP2_AUTOIDLE)>; | |
2122 | ti,syss-mask = <1>; | |
2123 | ti,no-reset-on-init; | |
2124 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
2125 | clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>; | |
2126 | clock-names = "fck"; | |
2127 | #address-cells = <1>; | |
2128 | #size-cells = <1>; | |
2129 | ranges = <0x0 0xb2000 0x1000>; | |
4ed0dfe3 TL |
2130 | |
2131 | hdqw1w: 1w@0 { | |
2132 | compatible = "ti,omap3-1w"; | |
2133 | reg = <0x0 0x1000>; | |
2134 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; | |
2135 | }; | |
549fce06 TL |
2136 | }; |
2137 | ||
2138 | target-module@b4000 { /* 0x480b4000, ap 65 40.0 */ | |
2139 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
2140 | ti,hwmods = "mmc2"; | |
2141 | reg = <0xb4000 0x4>, | |
2142 | <0xb4010 0x4>; | |
2143 | reg-names = "rev", "sysc"; | |
2144 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
2145 | SYSC_OMAP4_SOFTRESET)>; | |
2146 | ti,sysc-midle = <SYSC_IDLE_FORCE>, | |
2147 | <SYSC_IDLE_NO>, | |
2148 | <SYSC_IDLE_SMART>, | |
2149 | <SYSC_IDLE_SMART_WKUP>; | |
2150 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2151 | <SYSC_IDLE_NO>, | |
2152 | <SYSC_IDLE_SMART>, | |
2153 | <SYSC_IDLE_SMART_WKUP>; | |
2154 | /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ | |
2155 | clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>; | |
2156 | clock-names = "fck"; | |
2157 | #address-cells = <1>; | |
2158 | #size-cells = <1>; | |
2159 | ranges = <0x0 0xb4000 0x1000>; | |
4ed0dfe3 TL |
2160 | |
2161 | mmc2: mmc@0 { | |
2162 | compatible = "ti,dra7-sdhci"; | |
2163 | reg = <0x0 0x400>; | |
2164 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
2165 | status = "disabled"; | |
2166 | max-frequency = <192000000>; | |
2167 | /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ | |
2168 | sdhci-caps-mask = <0x7 0x0>; | |
2169 | mmc-hs200-1_8v; | |
2170 | mmc-ddr-1_8v; | |
2171 | mmc-ddr-3_3v; | |
2172 | }; | |
549fce06 TL |
2173 | }; |
2174 | ||
2175 | target-module@b8000 { /* 0x480b8000, ap 67 48.0 */ | |
2176 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
2177 | ti,hwmods = "mcspi3"; | |
2178 | reg = <0xb8000 0x4>, | |
2179 | <0xb8010 0x4>; | |
2180 | reg-names = "rev", "sysc"; | |
2181 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
2182 | SYSC_OMAP4_SOFTRESET)>; | |
2183 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2184 | <SYSC_IDLE_NO>, | |
2185 | <SYSC_IDLE_SMART>, | |
2186 | <SYSC_IDLE_SMART_WKUP>; | |
2187 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
2188 | clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>; | |
2189 | clock-names = "fck"; | |
2190 | #address-cells = <1>; | |
2191 | #size-cells = <1>; | |
2192 | ranges = <0x0 0xb8000 0x1000>; | |
4ed0dfe3 TL |
2193 | |
2194 | mcspi3: spi@0 { | |
2195 | compatible = "ti,omap4-mcspi"; | |
2196 | reg = <0x0 0x200>; | |
2197 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
2198 | #address-cells = <1>; | |
2199 | #size-cells = <0>; | |
2200 | ti,spi-num-cs = <2>; | |
2201 | dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; | |
2202 | dma-names = "tx0", "rx0"; | |
2203 | status = "disabled"; | |
2204 | }; | |
549fce06 TL |
2205 | }; |
2206 | ||
2207 | target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ | |
2208 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
2209 | ti,hwmods = "mcspi4"; | |
2210 | reg = <0xba000 0x4>, | |
2211 | <0xba010 0x4>; | |
2212 | reg-names = "rev", "sysc"; | |
2213 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
2214 | SYSC_OMAP4_SOFTRESET)>; | |
2215 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2216 | <SYSC_IDLE_NO>, | |
2217 | <SYSC_IDLE_SMART>, | |
2218 | <SYSC_IDLE_SMART_WKUP>; | |
2219 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
2220 | clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>; | |
2221 | clock-names = "fck"; | |
2222 | #address-cells = <1>; | |
2223 | #size-cells = <1>; | |
2224 | ranges = <0x0 0xba000 0x1000>; | |
4ed0dfe3 TL |
2225 | |
2226 | mcspi4: spi@0 { | |
2227 | compatible = "ti,omap4-mcspi"; | |
2228 | reg = <0x0 0x200>; | |
2229 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
2230 | #address-cells = <1>; | |
2231 | #size-cells = <0>; | |
2232 | ti,spi-num-cs = <1>; | |
2233 | dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; | |
2234 | dma-names = "tx0", "rx0"; | |
2235 | status = "disabled"; | |
2236 | }; | |
549fce06 TL |
2237 | }; |
2238 | ||
2239 | target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ | |
2240 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
2241 | ti,hwmods = "mmc4"; | |
2242 | reg = <0xd1000 0x4>, | |
2243 | <0xd1010 0x4>; | |
2244 | reg-names = "rev", "sysc"; | |
2245 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
2246 | SYSC_OMAP4_SOFTRESET)>; | |
2247 | ti,sysc-midle = <SYSC_IDLE_FORCE>, | |
2248 | <SYSC_IDLE_NO>, | |
2249 | <SYSC_IDLE_SMART>, | |
2250 | <SYSC_IDLE_SMART_WKUP>; | |
2251 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2252 | <SYSC_IDLE_NO>, | |
2253 | <SYSC_IDLE_SMART>, | |
2254 | <SYSC_IDLE_SMART_WKUP>; | |
2255 | /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ | |
2256 | clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>; | |
2257 | clock-names = "fck"; | |
2258 | #address-cells = <1>; | |
2259 | #size-cells = <1>; | |
2260 | ranges = <0x0 0xd1000 0x1000>; | |
4ed0dfe3 TL |
2261 | |
2262 | mmc4: mmc@0 { | |
2263 | compatible = "ti,dra7-sdhci"; | |
2264 | reg = <0x0 0x400>; | |
2265 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
2266 | status = "disabled"; | |
2267 | max-frequency = <192000000>; | |
2268 | /* SDMA is not supported */ | |
2269 | sdhci-caps-mask = <0x0 0x400000>; | |
2270 | }; | |
549fce06 TL |
2271 | }; |
2272 | ||
2273 | target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ | |
2274 | compatible = "ti,sysc"; | |
2275 | status = "disabled"; | |
2276 | #address-cells = <1>; | |
2277 | #size-cells = <1>; | |
2278 | ranges = <0x0 0xd5000 0x1000>; | |
2279 | }; | |
2280 | }; | |
2281 | ||
2282 | segment@200000 { /* 0x48200000 */ | |
2283 | compatible = "simple-bus"; | |
2284 | #address-cells = <1>; | |
2285 | #size-cells = <1>; | |
2286 | }; | |
2287 | }; | |
2288 | ||
2289 | &l4_per2 { /* 0x48400000 */ | |
2290 | compatible = "ti,dra7-l4-per2", "simple-bus"; | |
2291 | reg = <0x48400000 0x800>, | |
2292 | <0x48400800 0x800>, | |
2293 | <0x48401000 0x400>, | |
2294 | <0x48401400 0x400>, | |
2295 | <0x48401800 0x400>; | |
2296 | reg-names = "ap", "la", "ia0", "ia1", "ia2"; | |
2297 | #address-cells = <1>; | |
2298 | #size-cells = <1>; | |
5241ccbf TL |
2299 | ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */ |
2300 | <0x45800000 0x45800000 0x400000>, /* L3 data port */ | |
2301 | <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ | |
2302 | <0x46000000 0x46000000 0x400000>, /* L3 data port */ | |
2303 | <0x48436000 0x48436000 0x400000>, /* L3 data port */ | |
2304 | <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ | |
2305 | <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ | |
2306 | <0x48450000 0x48450000 0x400000>, /* L3 data port */ | |
2307 | <0x48454000 0x48454000 0x400000>; /* L3 data port */ | |
549fce06 TL |
2308 | |
2309 | segment@0 { /* 0x48400000 */ | |
2310 | compatible = "simple-bus"; | |
2311 | #address-cells = <1>; | |
2312 | #size-cells = <1>; | |
2313 | ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ | |
2314 | <0x00001000 0x00001000 0x000400>, /* ap 1 */ | |
2315 | <0x00000800 0x00000800 0x000800>, /* ap 2 */ | |
2316 | <0x00084000 0x00084000 0x004000>, /* ap 3 */ | |
2317 | <0x00001400 0x00001400 0x000400>, /* ap 4 */ | |
2318 | <0x00001800 0x00001800 0x000400>, /* ap 5 */ | |
2319 | <0x00088000 0x00088000 0x001000>, /* ap 6 */ | |
2320 | <0x0002c000 0x0002c000 0x001000>, /* ap 7 */ | |
2321 | <0x0002d000 0x0002d000 0x001000>, /* ap 8 */ | |
2322 | <0x00060000 0x00060000 0x002000>, /* ap 9 */ | |
2323 | <0x00062000 0x00062000 0x001000>, /* ap 10 */ | |
2324 | <0x00064000 0x00064000 0x002000>, /* ap 11 */ | |
2325 | <0x00066000 0x00066000 0x001000>, /* ap 12 */ | |
2326 | <0x00068000 0x00068000 0x002000>, /* ap 13 */ | |
2327 | <0x0006a000 0x0006a000 0x001000>, /* ap 14 */ | |
2328 | <0x0006c000 0x0006c000 0x002000>, /* ap 15 */ | |
2329 | <0x0006e000 0x0006e000 0x001000>, /* ap 16 */ | |
2330 | <0x00036000 0x00036000 0x001000>, /* ap 17 */ | |
2331 | <0x00037000 0x00037000 0x001000>, /* ap 18 */ | |
2332 | <0x00070000 0x00070000 0x002000>, /* ap 19 */ | |
2333 | <0x00072000 0x00072000 0x001000>, /* ap 20 */ | |
2334 | <0x0003a000 0x0003a000 0x001000>, /* ap 21 */ | |
2335 | <0x0003b000 0x0003b000 0x001000>, /* ap 22 */ | |
2336 | <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ | |
2337 | <0x0003d000 0x0003d000 0x001000>, /* ap 24 */ | |
2338 | <0x0003e000 0x0003e000 0x001000>, /* ap 25 */ | |
2339 | <0x0003f000 0x0003f000 0x001000>, /* ap 26 */ | |
2340 | <0x00040000 0x00040000 0x001000>, /* ap 27 */ | |
2341 | <0x00041000 0x00041000 0x001000>, /* ap 28 */ | |
2342 | <0x00042000 0x00042000 0x001000>, /* ap 29 */ | |
2343 | <0x00043000 0x00043000 0x001000>, /* ap 30 */ | |
2344 | <0x00080000 0x00080000 0x002000>, /* ap 31 */ | |
2345 | <0x00082000 0x00082000 0x001000>, /* ap 32 */ | |
2346 | <0x0004a000 0x0004a000 0x001000>, /* ap 33 */ | |
2347 | <0x0004b000 0x0004b000 0x001000>, /* ap 34 */ | |
2348 | <0x00074000 0x00074000 0x002000>, /* ap 35 */ | |
2349 | <0x00076000 0x00076000 0x001000>, /* ap 36 */ | |
2350 | <0x00050000 0x00050000 0x001000>, /* ap 37 */ | |
2351 | <0x00051000 0x00051000 0x001000>, /* ap 38 */ | |
2352 | <0x00078000 0x00078000 0x002000>, /* ap 39 */ | |
2353 | <0x0007a000 0x0007a000 0x001000>, /* ap 40 */ | |
2354 | <0x00054000 0x00054000 0x001000>, /* ap 41 */ | |
2355 | <0x00055000 0x00055000 0x001000>, /* ap 42 */ | |
2356 | <0x0007c000 0x0007c000 0x002000>, /* ap 43 */ | |
2357 | <0x0007e000 0x0007e000 0x001000>, /* ap 44 */ | |
2358 | <0x0004c000 0x0004c000 0x001000>, /* ap 45 */ | |
2359 | <0x0004d000 0x0004d000 0x001000>, /* ap 46 */ | |
2360 | <0x00020000 0x00020000 0x001000>, /* ap 47 */ | |
2361 | <0x00021000 0x00021000 0x001000>, /* ap 48 */ | |
2362 | <0x00022000 0x00022000 0x001000>, /* ap 49 */ | |
2363 | <0x00023000 0x00023000 0x001000>, /* ap 50 */ | |
2364 | <0x00024000 0x00024000 0x001000>, /* ap 51 */ | |
2365 | <0x00025000 0x00025000 0x001000>, /* ap 52 */ | |
2366 | <0x00046000 0x00046000 0x001000>, /* ap 53 */ | |
2367 | <0x00047000 0x00047000 0x001000>, /* ap 54 */ | |
2368 | <0x00048000 0x00048000 0x001000>, /* ap 55 */ | |
2369 | <0x00049000 0x00049000 0x001000>, /* ap 56 */ | |
2370 | <0x00058000 0x00058000 0x002000>, /* ap 57 */ | |
2371 | <0x0005a000 0x0005a000 0x001000>, /* ap 58 */ | |
2372 | <0x0005b000 0x0005b000 0x001000>, /* ap 59 */ | |
2373 | <0x0005c000 0x0005c000 0x001000>, /* ap 60 */ | |
2374 | <0x0005d000 0x0005d000 0x001000>, /* ap 61 */ | |
5241ccbf TL |
2375 | <0x0005e000 0x0005e000 0x001000>, /* ap 62 */ |
2376 | <0x45800000 0x45800000 0x400000>, /* L3 data port */ | |
2377 | <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ | |
2378 | <0x46000000 0x46000000 0x400000>, /* L3 data port */ | |
2379 | <0x48436000 0x48436000 0x400000>, /* L3 data port */ | |
2380 | <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ | |
2381 | <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ | |
2382 | <0x48450000 0x48450000 0x400000>, /* L3 data port */ | |
2383 | <0x48454000 0x48454000 0x400000>; /* L3 data port */ | |
549fce06 TL |
2384 | |
2385 | target-module@20000 { /* 0x48420000, ap 47 02.0 */ | |
2386 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
2387 | ti,hwmods = "uart7"; | |
2388 | reg = <0x20050 0x4>, | |
2389 | <0x20054 0x4>, | |
2390 | <0x20058 0x4>; | |
2391 | reg-names = "rev", "sysc", "syss"; | |
2392 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
2393 | SYSC_OMAP2_SOFTRESET | | |
2394 | SYSC_OMAP2_AUTOIDLE)>; | |
2395 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2396 | <SYSC_IDLE_NO>, | |
2397 | <SYSC_IDLE_SMART>, | |
2398 | <SYSC_IDLE_SMART_WKUP>; | |
2399 | ti,syss-mask = <1>; | |
2400 | /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ | |
2401 | clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>; | |
2402 | clock-names = "fck"; | |
2403 | #address-cells = <1>; | |
2404 | #size-cells = <1>; | |
2405 | ranges = <0x0 0x20000 0x1000>; | |
4ed0dfe3 TL |
2406 | |
2407 | uart7: serial@0 { | |
2408 | compatible = "ti,dra742-uart", "ti,omap4-uart"; | |
2409 | reg = <0x0 0x100>; | |
2410 | interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; | |
2411 | clock-frequency = <48000000>; | |
2412 | status = "disabled"; | |
2413 | }; | |
549fce06 TL |
2414 | }; |
2415 | ||
2416 | target-module@22000 { /* 0x48422000, ap 49 0a.0 */ | |
2417 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
2418 | ti,hwmods = "uart8"; | |
2419 | reg = <0x22050 0x4>, | |
2420 | <0x22054 0x4>, | |
2421 | <0x22058 0x4>; | |
2422 | reg-names = "rev", "sysc", "syss"; | |
2423 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
2424 | SYSC_OMAP2_SOFTRESET | | |
2425 | SYSC_OMAP2_AUTOIDLE)>; | |
2426 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2427 | <SYSC_IDLE_NO>, | |
2428 | <SYSC_IDLE_SMART>, | |
2429 | <SYSC_IDLE_SMART_WKUP>; | |
2430 | ti,syss-mask = <1>; | |
2431 | /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ | |
2432 | clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>; | |
2433 | clock-names = "fck"; | |
2434 | #address-cells = <1>; | |
2435 | #size-cells = <1>; | |
2436 | ranges = <0x0 0x22000 0x1000>; | |
4ed0dfe3 TL |
2437 | |
2438 | uart8: serial@0 { | |
2439 | compatible = "ti,dra742-uart", "ti,omap4-uart"; | |
2440 | reg = <0x0 0x100>; | |
2441 | interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; | |
2442 | clock-frequency = <48000000>; | |
2443 | status = "disabled"; | |
2444 | }; | |
549fce06 TL |
2445 | }; |
2446 | ||
2447 | target-module@24000 { /* 0x48424000, ap 51 12.0 */ | |
2448 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
2449 | ti,hwmods = "uart9"; | |
2450 | reg = <0x24050 0x4>, | |
2451 | <0x24054 0x4>, | |
2452 | <0x24058 0x4>; | |
2453 | reg-names = "rev", "sysc", "syss"; | |
2454 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
2455 | SYSC_OMAP2_SOFTRESET | | |
2456 | SYSC_OMAP2_AUTOIDLE)>; | |
2457 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2458 | <SYSC_IDLE_NO>, | |
2459 | <SYSC_IDLE_SMART>, | |
2460 | <SYSC_IDLE_SMART_WKUP>; | |
2461 | ti,syss-mask = <1>; | |
2462 | /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ | |
2463 | clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>; | |
2464 | clock-names = "fck"; | |
2465 | #address-cells = <1>; | |
2466 | #size-cells = <1>; | |
2467 | ranges = <0x0 0x24000 0x1000>; | |
4ed0dfe3 TL |
2468 | |
2469 | uart9: serial@0 { | |
2470 | compatible = "ti,dra742-uart", "ti,omap4-uart"; | |
2471 | reg = <0x0 0x100>; | |
2472 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; | |
2473 | clock-frequency = <48000000>; | |
2474 | status = "disabled"; | |
2475 | }; | |
549fce06 TL |
2476 | }; |
2477 | ||
2478 | target-module@2c000 { /* 0x4842c000, ap 7 18.0 */ | |
2479 | compatible = "ti,sysc"; | |
2480 | status = "disabled"; | |
2481 | #address-cells = <1>; | |
2482 | #size-cells = <1>; | |
2483 | ranges = <0x0 0x2c000 0x1000>; | |
2484 | }; | |
2485 | ||
2486 | target-module@36000 { /* 0x48436000, ap 17 06.0 */ | |
2487 | compatible = "ti,sysc"; | |
2488 | status = "disabled"; | |
2489 | #address-cells = <1>; | |
2490 | #size-cells = <1>; | |
2491 | ranges = <0x0 0x36000 0x1000>; | |
2492 | }; | |
2493 | ||
2494 | target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */ | |
2495 | compatible = "ti,sysc"; | |
2496 | status = "disabled"; | |
2497 | #address-cells = <1>; | |
2498 | #size-cells = <1>; | |
2499 | ranges = <0x0 0x3a000 0x1000>; | |
2500 | }; | |
2501 | ||
bcbb63b8 | 2502 | atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */ |
4ed0dfe3 TL |
2503 | compatible = "ti,sysc-omap4", "ti,sysc"; |
2504 | reg = <0x3c000 0x4>; | |
2505 | reg-names = "rev"; | |
2506 | clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>; | |
2507 | clock-names = "fck"; | |
549fce06 TL |
2508 | #address-cells = <1>; |
2509 | #size-cells = <1>; | |
2510 | ranges = <0x0 0x3c000 0x1000>; | |
4ed0dfe3 TL |
2511 | |
2512 | atl: atl@0 { | |
2513 | compatible = "ti,dra7-atl"; | |
2514 | reg = <0x0 0x3ff>; | |
2515 | ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, | |
2516 | <&atl_clkin2_ck>, <&atl_clkin3_ck>; | |
2517 | clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; | |
2518 | clock-names = "fck"; | |
2519 | status = "disabled"; | |
2520 | }; | |
549fce06 TL |
2521 | }; |
2522 | ||
2523 | target-module@3e000 { /* 0x4843e000, ap 25 30.0 */ | |
2524 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
2525 | ti,hwmods = "epwmss0"; | |
2526 | reg = <0x3e000 0x4>, | |
2527 | <0x3e004 0x4>; | |
2528 | reg-names = "rev", "sysc"; | |
2529 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
2530 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2531 | <SYSC_IDLE_NO>, | |
2532 | <SYSC_IDLE_SMART>; | |
2533 | /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ | |
2534 | clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>; | |
2535 | clock-names = "fck"; | |
2536 | #address-cells = <1>; | |
2537 | #size-cells = <1>; | |
2538 | ranges = <0x0 0x3e000 0x1000>; | |
4ed0dfe3 TL |
2539 | |
2540 | epwmss0: epwmss@0 { | |
2541 | compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; | |
2542 | reg = <0x0 0x30>; | |
2543 | #address-cells = <1>; | |
2544 | #size-cells = <1>; | |
2545 | status = "disabled"; | |
2546 | ranges = <0 0 0x1000>; | |
2547 | ||
2548 | ecap0: ecap@100 { | |
2549 | compatible = "ti,dra746-ecap", | |
2550 | "ti,am3352-ecap"; | |
2551 | #pwm-cells = <3>; | |
2552 | reg = <0x100 0x80>; | |
2553 | clocks = <&l4_root_clk_div>; | |
2554 | clock-names = "fck"; | |
2555 | status = "disabled"; | |
2556 | }; | |
2557 | ||
2558 | ehrpwm0: pwm@200 { | |
2559 | compatible = "ti,dra746-ehrpwm", | |
2560 | "ti,am3352-ehrpwm"; | |
2561 | #pwm-cells = <3>; | |
2562 | reg = <0x200 0x80>; | |
2563 | clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; | |
2564 | clock-names = "tbclk", "fck"; | |
2565 | status = "disabled"; | |
2566 | }; | |
2567 | }; | |
549fce06 TL |
2568 | }; |
2569 | ||
2570 | target-module@40000 { /* 0x48440000, ap 27 38.0 */ | |
2571 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
2572 | ti,hwmods = "epwmss1"; | |
2573 | reg = <0x40000 0x4>, | |
2574 | <0x40004 0x4>; | |
2575 | reg-names = "rev", "sysc"; | |
2576 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
2577 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2578 | <SYSC_IDLE_NO>, | |
2579 | <SYSC_IDLE_SMART>; | |
2580 | /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ | |
2581 | clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>; | |
2582 | clock-names = "fck"; | |
2583 | #address-cells = <1>; | |
2584 | #size-cells = <1>; | |
2585 | ranges = <0x0 0x40000 0x1000>; | |
4ed0dfe3 TL |
2586 | |
2587 | epwmss1: epwmss@0 { | |
2588 | compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; | |
2589 | reg = <0x0 0x30>; | |
2590 | #address-cells = <1>; | |
2591 | #size-cells = <1>; | |
2592 | status = "disabled"; | |
2593 | ranges = <0 0 0x1000>; | |
2594 | ||
2595 | ecap1: ecap@100 { | |
2596 | compatible = "ti,dra746-ecap", | |
2597 | "ti,am3352-ecap"; | |
2598 | #pwm-cells = <3>; | |
2599 | reg = <0x100 0x80>; | |
2600 | clocks = <&l4_root_clk_div>; | |
2601 | clock-names = "fck"; | |
2602 | status = "disabled"; | |
2603 | }; | |
2604 | ||
2605 | ehrpwm1: pwm@200 { | |
2606 | compatible = "ti,dra746-ehrpwm", | |
2607 | "ti,am3352-ehrpwm"; | |
2608 | #pwm-cells = <3>; | |
2609 | reg = <0x200 0x80>; | |
2610 | clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; | |
2611 | clock-names = "tbclk", "fck"; | |
2612 | status = "disabled"; | |
2613 | }; | |
2614 | }; | |
549fce06 TL |
2615 | }; |
2616 | ||
2617 | target-module@42000 { /* 0x48442000, ap 29 20.0 */ | |
2618 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
2619 | ti,hwmods = "epwmss2"; | |
2620 | reg = <0x42000 0x4>, | |
2621 | <0x42004 0x4>; | |
2622 | reg-names = "rev", "sysc"; | |
2623 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
2624 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2625 | <SYSC_IDLE_NO>, | |
2626 | <SYSC_IDLE_SMART>; | |
2627 | /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ | |
2628 | clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>; | |
2629 | clock-names = "fck"; | |
2630 | #address-cells = <1>; | |
2631 | #size-cells = <1>; | |
2632 | ranges = <0x0 0x42000 0x1000>; | |
4ed0dfe3 TL |
2633 | |
2634 | epwmss2: epwmss@0 { | |
2635 | compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; | |
2636 | reg = <0x0 0x30>; | |
2637 | #address-cells = <1>; | |
2638 | #size-cells = <1>; | |
2639 | status = "disabled"; | |
2640 | ranges = <0 0 0x1000>; | |
2641 | ||
2642 | ecap2: ecap@100 { | |
2643 | compatible = "ti,dra746-ecap", | |
2644 | "ti,am3352-ecap"; | |
2645 | #pwm-cells = <3>; | |
2646 | reg = <0x100 0x80>; | |
2647 | clocks = <&l4_root_clk_div>; | |
2648 | clock-names = "fck"; | |
2649 | status = "disabled"; | |
2650 | }; | |
2651 | ||
2652 | ehrpwm2: pwm@200 { | |
2653 | compatible = "ti,dra746-ehrpwm", | |
2654 | "ti,am3352-ehrpwm"; | |
2655 | #pwm-cells = <3>; | |
2656 | reg = <0x200 0x80>; | |
2657 | clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; | |
2658 | clock-names = "tbclk", "fck"; | |
2659 | status = "disabled"; | |
2660 | }; | |
2661 | }; | |
549fce06 TL |
2662 | }; |
2663 | ||
2664 | target-module@46000 { /* 0x48446000, ap 53 40.0 */ | |
2665 | compatible = "ti,sysc"; | |
2666 | status = "disabled"; | |
2667 | #address-cells = <1>; | |
2668 | #size-cells = <1>; | |
2669 | ranges = <0x0 0x46000 0x1000>; | |
2670 | }; | |
2671 | ||
2672 | target-module@48000 { /* 0x48448000, ap 55 48.0 */ | |
2673 | compatible = "ti,sysc"; | |
2674 | status = "disabled"; | |
2675 | #address-cells = <1>; | |
2676 | #size-cells = <1>; | |
2677 | ranges = <0x0 0x48000 0x1000>; | |
2678 | }; | |
2679 | ||
2680 | target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */ | |
2681 | compatible = "ti,sysc"; | |
2682 | status = "disabled"; | |
2683 | #address-cells = <1>; | |
2684 | #size-cells = <1>; | |
2685 | ranges = <0x0 0x4a000 0x1000>; | |
2686 | }; | |
2687 | ||
2688 | target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */ | |
2689 | compatible = "ti,sysc"; | |
2690 | status = "disabled"; | |
2691 | #address-cells = <1>; | |
2692 | #size-cells = <1>; | |
2693 | ranges = <0x0 0x4c000 0x1000>; | |
2694 | }; | |
2695 | ||
2696 | target-module@50000 { /* 0x48450000, ap 37 24.0 */ | |
2697 | compatible = "ti,sysc"; | |
2698 | status = "disabled"; | |
2699 | #address-cells = <1>; | |
2700 | #size-cells = <1>; | |
2701 | ranges = <0x0 0x50000 0x1000>; | |
2702 | }; | |
2703 | ||
2704 | target-module@54000 { /* 0x48454000, ap 41 2c.0 */ | |
2705 | compatible = "ti,sysc"; | |
2706 | status = "disabled"; | |
2707 | #address-cells = <1>; | |
2708 | #size-cells = <1>; | |
2709 | ranges = <0x0 0x54000 0x1000>; | |
2710 | }; | |
2711 | ||
2712 | target-module@58000 { /* 0x48458000, ap 57 28.0 */ | |
2713 | compatible = "ti,sysc"; | |
2714 | status = "disabled"; | |
2715 | #address-cells = <1>; | |
2716 | #size-cells = <1>; | |
2717 | ranges = <0x0 0x58000 0x2000>; | |
2718 | }; | |
2719 | ||
2720 | target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ | |
2721 | compatible = "ti,sysc"; | |
2722 | status = "disabled"; | |
2723 | #address-cells = <1>; | |
2724 | #size-cells = <1>; | |
2725 | ranges = <0x0 0x5b000 0x1000>; | |
2726 | }; | |
2727 | ||
2728 | target-module@5d000 { /* 0x4845d000, ap 61 22.0 */ | |
2729 | compatible = "ti,sysc"; | |
2730 | status = "disabled"; | |
2731 | #address-cells = <1>; | |
2732 | #size-cells = <1>; | |
2733 | ranges = <0x0 0x5d000 0x1000>; | |
2734 | }; | |
2735 | ||
2736 | target-module@60000 { /* 0x48460000, ap 9 0e.0 */ | |
10aee7ae | 2737 | compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; |
549fce06 TL |
2738 | ti,hwmods = "mcasp1"; |
2739 | reg = <0x60000 0x4>, | |
2740 | <0x60004 0x4>; | |
2741 | reg-names = "rev", "sysc"; | |
2742 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2743 | <SYSC_IDLE_NO>, | |
2744 | <SYSC_IDLE_SMART>; | |
2745 | /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ | |
5241ccbf TL |
2746 | clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, |
2747 | <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, | |
2748 | <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; | |
2749 | clock-names = "fck", "ahclkx", "ahclkr"; | |
549fce06 TL |
2750 | #address-cells = <1>; |
2751 | #size-cells = <1>; | |
5241ccbf TL |
2752 | ranges = <0x0 0x60000 0x2000>, |
2753 | <0x45800000 0x45800000 0x400000>; | |
4ed0dfe3 TL |
2754 | |
2755 | mcasp1: mcasp@0 { | |
2756 | compatible = "ti,dra7-mcasp-audio"; | |
2757 | reg = <0x0 0x2000>, | |
2758 | <0x45800000 0x1000>; /* L3 data port */ | |
2759 | reg-names = "mpu","dat"; | |
2760 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, | |
2761 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
2762 | interrupt-names = "tx", "rx"; | |
2763 | dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; | |
2764 | dma-names = "tx", "rx"; | |
09112bb3 | 2765 | clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, |
4ed0dfe3 TL |
2766 | <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, |
2767 | <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; | |
2768 | clock-names = "fck", "ahclkx", "ahclkr"; | |
2769 | status = "disabled"; | |
2770 | }; | |
549fce06 TL |
2771 | }; |
2772 | ||
2773 | target-module@64000 { /* 0x48464000, ap 11 1e.0 */ | |
10aee7ae | 2774 | compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; |
549fce06 TL |
2775 | ti,hwmods = "mcasp2"; |
2776 | reg = <0x64000 0x4>, | |
2777 | <0x64004 0x4>; | |
2778 | reg-names = "rev", "sysc"; | |
2779 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2780 | <SYSC_IDLE_NO>, | |
2781 | <SYSC_IDLE_SMART>; | |
2782 | /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ | |
5241ccbf TL |
2783 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, |
2784 | <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, | |
2785 | <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; | |
2786 | clock-names = "fck", "ahclkx", "ahclkr"; | |
549fce06 TL |
2787 | #address-cells = <1>; |
2788 | #size-cells = <1>; | |
5241ccbf TL |
2789 | ranges = <0x0 0x64000 0x2000>, |
2790 | <0x45c00000 0x45c00000 0x400000>; | |
4ed0dfe3 TL |
2791 | |
2792 | mcasp2: mcasp@0 { | |
2793 | compatible = "ti,dra7-mcasp-audio"; | |
2794 | reg = <0x0 0x2000>, | |
2795 | <0x45c00000 0x1000>; /* L3 data port */ | |
2796 | reg-names = "mpu","dat"; | |
2797 | interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
2798 | <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
2799 | interrupt-names = "tx", "rx"; | |
2800 | dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; | |
2801 | dma-names = "tx", "rx"; | |
09112bb3 TL |
2802 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, |
2803 | <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, | |
4ed0dfe3 TL |
2804 | <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; |
2805 | clock-names = "fck", "ahclkx", "ahclkr"; | |
2806 | status = "disabled"; | |
2807 | }; | |
549fce06 TL |
2808 | }; |
2809 | ||
2810 | target-module@68000 { /* 0x48468000, ap 13 26.0 */ | |
10aee7ae | 2811 | compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; |
549fce06 TL |
2812 | ti,hwmods = "mcasp3"; |
2813 | reg = <0x68000 0x4>, | |
2814 | <0x68004 0x4>; | |
2815 | reg-names = "rev", "sysc"; | |
2816 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2817 | <SYSC_IDLE_NO>, | |
2818 | <SYSC_IDLE_SMART>; | |
2819 | /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ | |
5241ccbf | 2820 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, |
09112bb3 TL |
2821 | <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; |
2822 | clock-names = "fck", "ahclkx"; | |
549fce06 TL |
2823 | #address-cells = <1>; |
2824 | #size-cells = <1>; | |
5241ccbf TL |
2825 | ranges = <0x0 0x68000 0x2000>, |
2826 | <0x46000000 0x46000000 0x400000>; | |
4ed0dfe3 TL |
2827 | |
2828 | mcasp3: mcasp@0 { | |
2829 | compatible = "ti,dra7-mcasp-audio"; | |
2830 | reg = <0x0 0x2000>, | |
2831 | <0x46000000 0x1000>; /* L3 data port */ | |
2832 | reg-names = "mpu","dat"; | |
2833 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, | |
2834 | <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; | |
2835 | interrupt-names = "tx", "rx"; | |
2836 | dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; | |
2837 | dma-names = "tx", "rx"; | |
09112bb3 | 2838 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, |
4ed0dfe3 TL |
2839 | <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; |
2840 | clock-names = "fck", "ahclkx"; | |
2841 | status = "disabled"; | |
2842 | }; | |
549fce06 TL |
2843 | }; |
2844 | ||
2845 | target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */ | |
10aee7ae | 2846 | compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; |
549fce06 TL |
2847 | ti,hwmods = "mcasp4"; |
2848 | reg = <0x6c000 0x4>, | |
2849 | <0x6c004 0x4>; | |
2850 | reg-names = "rev", "sysc"; | |
2851 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2852 | <SYSC_IDLE_NO>, | |
2853 | <SYSC_IDLE_SMART>; | |
2854 | /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ | |
5241ccbf | 2855 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, |
09112bb3 TL |
2856 | <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; |
2857 | clock-names = "fck", "ahclkx"; | |
549fce06 TL |
2858 | #address-cells = <1>; |
2859 | #size-cells = <1>; | |
5241ccbf TL |
2860 | ranges = <0x0 0x6c000 0x2000>, |
2861 | <0x48436000 0x48436000 0x400000>; | |
4ed0dfe3 TL |
2862 | |
2863 | mcasp4: mcasp@0 { | |
2864 | compatible = "ti,dra7-mcasp-audio"; | |
2865 | reg = <0x0 0x2000>, | |
2866 | <0x48436000 0x1000>; /* L3 data port */ | |
2867 | reg-names = "mpu","dat"; | |
2868 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, | |
2869 | <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
2870 | interrupt-names = "tx", "rx"; | |
2871 | dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; | |
2872 | dma-names = "tx", "rx"; | |
09112bb3 | 2873 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, |
4ed0dfe3 TL |
2874 | <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; |
2875 | clock-names = "fck", "ahclkx"; | |
2876 | status = "disabled"; | |
2877 | }; | |
549fce06 TL |
2878 | }; |
2879 | ||
2880 | target-module@70000 { /* 0x48470000, ap 19 36.0 */ | |
10aee7ae | 2881 | compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; |
549fce06 TL |
2882 | ti,hwmods = "mcasp5"; |
2883 | reg = <0x70000 0x4>, | |
2884 | <0x70004 0x4>; | |
2885 | reg-names = "rev", "sysc"; | |
2886 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2887 | <SYSC_IDLE_NO>, | |
2888 | <SYSC_IDLE_SMART>; | |
2889 | /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ | |
5241ccbf | 2890 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, |
09112bb3 TL |
2891 | <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; |
2892 | clock-names = "fck", "ahclkx"; | |
549fce06 TL |
2893 | #address-cells = <1>; |
2894 | #size-cells = <1>; | |
5241ccbf TL |
2895 | ranges = <0x0 0x70000 0x2000>, |
2896 | <0x4843a000 0x4843a000 0x400000>; | |
4ed0dfe3 TL |
2897 | |
2898 | mcasp5: mcasp@0 { | |
2899 | compatible = "ti,dra7-mcasp-audio"; | |
2900 | reg = <0x0 0x2000>, | |
2901 | <0x4843a000 0x1000>; /* L3 data port */ | |
2902 | reg-names = "mpu","dat"; | |
2903 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, | |
2904 | <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
2905 | interrupt-names = "tx", "rx"; | |
2906 | dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; | |
2907 | dma-names = "tx", "rx"; | |
09112bb3 | 2908 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, |
4ed0dfe3 TL |
2909 | <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; |
2910 | clock-names = "fck", "ahclkx"; | |
2911 | status = "disabled"; | |
2912 | }; | |
549fce06 TL |
2913 | }; |
2914 | ||
2915 | target-module@74000 { /* 0x48474000, ap 35 14.0 */ | |
10aee7ae | 2916 | compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; |
549fce06 TL |
2917 | ti,hwmods = "mcasp6"; |
2918 | reg = <0x74000 0x4>, | |
2919 | <0x74004 0x4>; | |
2920 | reg-names = "rev", "sysc"; | |
2921 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2922 | <SYSC_IDLE_NO>, | |
2923 | <SYSC_IDLE_SMART>; | |
2924 | /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ | |
5241ccbf | 2925 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, |
09112bb3 TL |
2926 | <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; |
2927 | clock-names = "fck", "ahclkx"; | |
549fce06 TL |
2928 | #address-cells = <1>; |
2929 | #size-cells = <1>; | |
5241ccbf TL |
2930 | ranges = <0x0 0x74000 0x2000>, |
2931 | <0x4844c000 0x4844c000 0x400000>; | |
4ed0dfe3 TL |
2932 | |
2933 | mcasp6: mcasp@0 { | |
2934 | compatible = "ti,dra7-mcasp-audio"; | |
2935 | reg = <0x0 0x2000>, | |
2936 | <0x4844c000 0x1000>; /* L3 data port */ | |
2937 | reg-names = "mpu","dat"; | |
2938 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, | |
2939 | <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; | |
2940 | interrupt-names = "tx", "rx"; | |
2941 | dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; | |
2942 | dma-names = "tx", "rx"; | |
09112bb3 | 2943 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, |
4ed0dfe3 TL |
2944 | <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; |
2945 | clock-names = "fck", "ahclkx"; | |
2946 | status = "disabled"; | |
2947 | }; | |
549fce06 TL |
2948 | }; |
2949 | ||
2950 | target-module@78000 { /* 0x48478000, ap 39 0c.0 */ | |
10aee7ae | 2951 | compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; |
549fce06 TL |
2952 | ti,hwmods = "mcasp7"; |
2953 | reg = <0x78000 0x4>, | |
2954 | <0x78004 0x4>; | |
2955 | reg-names = "rev", "sysc"; | |
2956 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2957 | <SYSC_IDLE_NO>, | |
2958 | <SYSC_IDLE_SMART>; | |
2959 | /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ | |
5241ccbf | 2960 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, |
09112bb3 TL |
2961 | <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; |
2962 | clock-names = "fck", "ahclkx"; | |
549fce06 TL |
2963 | #address-cells = <1>; |
2964 | #size-cells = <1>; | |
5241ccbf TL |
2965 | ranges = <0x0 0x78000 0x2000>, |
2966 | <0x48450000 0x48450000 0x400000>; | |
4ed0dfe3 TL |
2967 | |
2968 | mcasp7: mcasp@0 { | |
2969 | compatible = "ti,dra7-mcasp-audio"; | |
2970 | reg = <0x0 0x2000>, | |
2971 | <0x48450000 0x1000>; /* L3 data port */ | |
2972 | reg-names = "mpu","dat"; | |
2973 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, | |
2974 | <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
2975 | interrupt-names = "tx", "rx"; | |
2976 | dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; | |
2977 | dma-names = "tx", "rx"; | |
09112bb3 | 2978 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, |
4ed0dfe3 TL |
2979 | <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; |
2980 | clock-names = "fck", "ahclkx"; | |
2981 | status = "disabled"; | |
2982 | }; | |
549fce06 TL |
2983 | }; |
2984 | ||
2985 | target-module@7c000 { /* 0x4847c000, ap 43 04.0 */ | |
10aee7ae | 2986 | compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; |
549fce06 TL |
2987 | ti,hwmods = "mcasp8"; |
2988 | reg = <0x7c000 0x4>, | |
2989 | <0x7c004 0x4>; | |
2990 | reg-names = "rev", "sysc"; | |
2991 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
2992 | <SYSC_IDLE_NO>, | |
2993 | <SYSC_IDLE_SMART>; | |
2994 | /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ | |
5241ccbf | 2995 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, |
09112bb3 TL |
2996 | <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; |
2997 | clock-names = "fck", "ahclkx"; | |
549fce06 TL |
2998 | #address-cells = <1>; |
2999 | #size-cells = <1>; | |
5241ccbf TL |
3000 | ranges = <0x0 0x7c000 0x2000>, |
3001 | <0x48454000 0x48454000 0x400000>; | |
4ed0dfe3 TL |
3002 | |
3003 | mcasp8: mcasp@0 { | |
3004 | compatible = "ti,dra7-mcasp-audio"; | |
3005 | reg = <0x0 0x2000>, | |
3006 | <0x48454000 0x1000>; /* L3 data port */ | |
3007 | reg-names = "mpu","dat"; | |
3008 | interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, | |
3009 | <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; | |
3010 | interrupt-names = "tx", "rx"; | |
3011 | dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; | |
3012 | dma-names = "tx", "rx"; | |
09112bb3 | 3013 | clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, |
4ed0dfe3 TL |
3014 | <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; |
3015 | clock-names = "fck", "ahclkx"; | |
3016 | status = "disabled"; | |
3017 | }; | |
549fce06 TL |
3018 | }; |
3019 | ||
3020 | target-module@80000 { /* 0x48480000, ap 31 16.0 */ | |
4ed0dfe3 | 3021 | compatible = "ti,sysc-omap4", "ti,sysc"; |
89bbc6f1 | 3022 | reg = <0x80020 0x4>; |
4ed0dfe3 TL |
3023 | reg-names = "rev"; |
3024 | clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>; | |
3025 | clock-names = "fck"; | |
549fce06 TL |
3026 | #address-cells = <1>; |
3027 | #size-cells = <1>; | |
3028 | ranges = <0x0 0x80000 0x2000>; | |
4ed0dfe3 TL |
3029 | |
3030 | dcan2: can@0 { | |
3031 | compatible = "ti,dra7-d_can"; | |
3032 | reg = <0x0 0x2000>; | |
3033 | syscon-raminit = <&scm_conf 0x558 1>; | |
3034 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; | |
3035 | clocks = <&sys_clkin1>; | |
3036 | status = "disabled"; | |
3037 | }; | |
549fce06 TL |
3038 | }; |
3039 | ||
3040 | target-module@84000 { /* 0x48484000, ap 3 10.0 */ | |
4ed0dfe3 TL |
3041 | compatible = "ti,sysc-omap4-simple", "ti,sysc"; |
3042 | ti,hwmods = "gmac"; | |
3043 | reg = <0x85200 0x4>, | |
3044 | <0x85208 0x4>, | |
3045 | <0x85204 0x4>; | |
3046 | reg-names = "rev", "sysc", "syss"; | |
3047 | ti,sysc-mask = <0>; | |
3048 | ti,sysc-midle = <SYSC_IDLE_FORCE>, | |
3049 | <SYSC_IDLE_NO>; | |
3050 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3051 | <SYSC_IDLE_NO>; | |
3052 | ti,syss-mask = <1>; | |
3053 | clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; | |
3054 | clock-names = "fck"; | |
549fce06 TL |
3055 | #address-cells = <1>; |
3056 | #size-cells = <1>; | |
3057 | ranges = <0x0 0x84000 0x4000>; | |
b79e7b3b TK |
3058 | /* |
3059 | * Do not allow gating of cpsw clock as workaround | |
3060 | * for errata i877. Keeping internal clock disabled | |
3061 | * causes the device switching characteristics | |
3062 | * to degrade over time and eventually fail to meet | |
3063 | * the data manual delay time/skew specs. | |
3064 | */ | |
3065 | ti,no-idle; | |
4ed0dfe3 TL |
3066 | |
3067 | mac: ethernet@0 { | |
3068 | compatible = "ti,dra7-cpsw","ti,cpsw"; | |
3069 | clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; | |
3070 | clock-names = "fck", "cpts"; | |
3071 | cpdma_channels = <8>; | |
3072 | ale_entries = <1024>; | |
3073 | bd_ram_size = <0x2000>; | |
3074 | mac_control = <0x20>; | |
3075 | slaves = <2>; | |
3076 | active_slave = <0>; | |
3077 | cpts_clock_mult = <0x784CFE14>; | |
3078 | cpts_clock_shift = <29>; | |
3079 | reg = <0x0 0x1000 | |
3080 | 0x1200 0x2e00>; | |
3081 | #address-cells = <1>; | |
3082 | #size-cells = <1>; | |
3083 | ||
4ed0dfe3 TL |
3084 | /* |
3085 | * rx_thresh_pend | |
3086 | * rx_pend | |
3087 | * tx_pend | |
3088 | * misc_pend | |
3089 | */ | |
3090 | interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
3091 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, | |
3092 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
3093 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; | |
3094 | ranges = <0 0 0x4000>; | |
3095 | syscon = <&scm_conf>; | |
4ed0dfe3 TL |
3096 | status = "disabled"; |
3097 | ||
3098 | davinci_mdio: mdio@1000 { | |
3099 | compatible = "ti,cpsw-mdio","ti,davinci_mdio"; | |
3100 | #address-cells = <1>; | |
3101 | #size-cells = <0>; | |
3102 | ti,hwmods = "davinci_mdio"; | |
3103 | bus_freq = <1000000>; | |
3104 | reg = <0x1000 0x100>; | |
3105 | }; | |
3106 | ||
3107 | cpsw_emac0: slave@200 { | |
3108 | /* Filled in by U-Boot */ | |
3109 | mac-address = [ 00 00 00 00 00 00 ]; | |
e8acd856 | 3110 | phys = <&phy_gmii_sel 1>; |
4ed0dfe3 TL |
3111 | }; |
3112 | ||
3113 | cpsw_emac1: slave@300 { | |
3114 | /* Filled in by U-Boot */ | |
3115 | mac-address = [ 00 00 00 00 00 00 ]; | |
e8acd856 | 3116 | phys = <&phy_gmii_sel 2>; |
4ed0dfe3 TL |
3117 | }; |
3118 | }; | |
549fce06 TL |
3119 | }; |
3120 | }; | |
3121 | }; | |
3122 | ||
3123 | &l4_per3 { /* 0x48800000 */ | |
3124 | compatible = "ti,dra7-l4-per3", "simple-bus"; | |
3125 | reg = <0x48800000 0x800>, | |
3126 | <0x48800800 0x800>, | |
3127 | <0x48801000 0x400>, | |
3128 | <0x48801400 0x400>, | |
3129 | <0x48801800 0x400>; | |
3130 | reg-names = "ap", "la", "ia0", "ia1", "ia2"; | |
3131 | #address-cells = <1>; | |
3132 | #size-cells = <1>; | |
3133 | ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */ | |
3134 | ||
3135 | segment@0 { /* 0x48800000 */ | |
3136 | compatible = "simple-bus"; | |
3137 | #address-cells = <1>; | |
3138 | #size-cells = <1>; | |
3139 | ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ | |
3140 | <0x00000800 0x00000800 0x000800>, /* ap 1 */ | |
3141 | <0x00001000 0x00001000 0x000400>, /* ap 2 */ | |
3142 | <0x00001400 0x00001400 0x000400>, /* ap 3 */ | |
3143 | <0x00001800 0x00001800 0x000400>, /* ap 4 */ | |
3144 | <0x00020000 0x00020000 0x001000>, /* ap 5 */ | |
3145 | <0x00021000 0x00021000 0x001000>, /* ap 6 */ | |
3146 | <0x00022000 0x00022000 0x001000>, /* ap 7 */ | |
3147 | <0x00023000 0x00023000 0x001000>, /* ap 8 */ | |
3148 | <0x00024000 0x00024000 0x001000>, /* ap 9 */ | |
3149 | <0x00025000 0x00025000 0x001000>, /* ap 10 */ | |
3150 | <0x00026000 0x00026000 0x001000>, /* ap 11 */ | |
3151 | <0x00027000 0x00027000 0x001000>, /* ap 12 */ | |
3152 | <0x00028000 0x00028000 0x001000>, /* ap 13 */ | |
3153 | <0x00029000 0x00029000 0x001000>, /* ap 14 */ | |
3154 | <0x0002a000 0x0002a000 0x001000>, /* ap 15 */ | |
3155 | <0x0002b000 0x0002b000 0x001000>, /* ap 16 */ | |
3156 | <0x0002c000 0x0002c000 0x001000>, /* ap 17 */ | |
3157 | <0x0002d000 0x0002d000 0x001000>, /* ap 18 */ | |
3158 | <0x0002e000 0x0002e000 0x001000>, /* ap 19 */ | |
3159 | <0x0002f000 0x0002f000 0x001000>, /* ap 20 */ | |
3160 | <0x00170000 0x00170000 0x010000>, /* ap 21 */ | |
3161 | <0x00180000 0x00180000 0x001000>, /* ap 22 */ | |
3162 | <0x00190000 0x00190000 0x010000>, /* ap 23 */ | |
3163 | <0x001a0000 0x001a0000 0x001000>, /* ap 24 */ | |
3164 | <0x001b0000 0x001b0000 0x010000>, /* ap 25 */ | |
3165 | <0x001c0000 0x001c0000 0x001000>, /* ap 26 */ | |
3166 | <0x001d0000 0x001d0000 0x010000>, /* ap 27 */ | |
3167 | <0x001e0000 0x001e0000 0x001000>, /* ap 28 */ | |
3168 | <0x00038000 0x00038000 0x001000>, /* ap 29 */ | |
3169 | <0x00039000 0x00039000 0x001000>, /* ap 30 */ | |
3170 | <0x0005c000 0x0005c000 0x001000>, /* ap 31 */ | |
3171 | <0x0005d000 0x0005d000 0x001000>, /* ap 32 */ | |
3172 | <0x0003a000 0x0003a000 0x001000>, /* ap 33 */ | |
3173 | <0x0003b000 0x0003b000 0x001000>, /* ap 34 */ | |
3174 | <0x0003c000 0x0003c000 0x001000>, /* ap 35 */ | |
3175 | <0x0003d000 0x0003d000 0x001000>, /* ap 36 */ | |
3176 | <0x0003e000 0x0003e000 0x001000>, /* ap 37 */ | |
3177 | <0x0003f000 0x0003f000 0x001000>, /* ap 38 */ | |
3178 | <0x00040000 0x00040000 0x001000>, /* ap 39 */ | |
3179 | <0x00041000 0x00041000 0x001000>, /* ap 40 */ | |
3180 | <0x00042000 0x00042000 0x001000>, /* ap 41 */ | |
3181 | <0x00043000 0x00043000 0x001000>, /* ap 42 */ | |
3182 | <0x00044000 0x00044000 0x001000>, /* ap 43 */ | |
3183 | <0x00045000 0x00045000 0x001000>, /* ap 44 */ | |
3184 | <0x00046000 0x00046000 0x001000>, /* ap 45 */ | |
3185 | <0x00047000 0x00047000 0x001000>, /* ap 46 */ | |
3186 | <0x00048000 0x00048000 0x001000>, /* ap 47 */ | |
3187 | <0x00049000 0x00049000 0x001000>, /* ap 48 */ | |
3188 | <0x0004a000 0x0004a000 0x001000>, /* ap 49 */ | |
3189 | <0x0004b000 0x0004b000 0x001000>, /* ap 50 */ | |
3190 | <0x0004c000 0x0004c000 0x001000>, /* ap 51 */ | |
3191 | <0x0004d000 0x0004d000 0x001000>, /* ap 52 */ | |
3192 | <0x0004e000 0x0004e000 0x001000>, /* ap 53 */ | |
3193 | <0x0004f000 0x0004f000 0x001000>, /* ap 54 */ | |
3194 | <0x00050000 0x00050000 0x001000>, /* ap 55 */ | |
3195 | <0x00051000 0x00051000 0x001000>, /* ap 56 */ | |
3196 | <0x00052000 0x00052000 0x001000>, /* ap 57 */ | |
3197 | <0x00053000 0x00053000 0x001000>, /* ap 58 */ | |
3198 | <0x00054000 0x00054000 0x001000>, /* ap 59 */ | |
3199 | <0x00055000 0x00055000 0x001000>, /* ap 60 */ | |
3200 | <0x00056000 0x00056000 0x001000>, /* ap 61 */ | |
3201 | <0x00057000 0x00057000 0x001000>, /* ap 62 */ | |
3202 | <0x00058000 0x00058000 0x001000>, /* ap 63 */ | |
3203 | <0x00059000 0x00059000 0x001000>, /* ap 64 */ | |
3204 | <0x0005a000 0x0005a000 0x001000>, /* ap 65 */ | |
3205 | <0x0005b000 0x0005b000 0x001000>, /* ap 66 */ | |
3206 | <0x00064000 0x00064000 0x001000>, /* ap 67 */ | |
3207 | <0x00065000 0x00065000 0x001000>, /* ap 68 */ | |
3208 | <0x0005e000 0x0005e000 0x001000>, /* ap 69 */ | |
3209 | <0x0005f000 0x0005f000 0x001000>, /* ap 70 */ | |
3210 | <0x00060000 0x00060000 0x001000>, /* ap 71 */ | |
3211 | <0x00061000 0x00061000 0x001000>, /* ap 72 */ | |
3212 | <0x00062000 0x00062000 0x001000>, /* ap 73 */ | |
3213 | <0x00063000 0x00063000 0x001000>, /* ap 74 */ | |
3214 | <0x00140000 0x00140000 0x020000>, /* ap 75 */ | |
3215 | <0x00160000 0x00160000 0x001000>, /* ap 76 */ | |
3216 | <0x00016000 0x00016000 0x001000>, /* ap 77 */ | |
3217 | <0x00017000 0x00017000 0x001000>, /* ap 78 */ | |
3218 | <0x000c0000 0x000c0000 0x020000>, /* ap 79 */ | |
3219 | <0x000e0000 0x000e0000 0x001000>, /* ap 80 */ | |
3220 | <0x00004000 0x00004000 0x001000>, /* ap 81 */ | |
3221 | <0x00005000 0x00005000 0x001000>, /* ap 82 */ | |
3222 | <0x00080000 0x00080000 0x020000>, /* ap 83 */ | |
3223 | <0x000a0000 0x000a0000 0x001000>, /* ap 84 */ | |
3224 | <0x00100000 0x00100000 0x020000>, /* ap 85 */ | |
3225 | <0x00120000 0x00120000 0x001000>, /* ap 86 */ | |
3226 | <0x00010000 0x00010000 0x001000>, /* ap 87 */ | |
3227 | <0x00011000 0x00011000 0x001000>, /* ap 88 */ | |
3228 | <0x0000a000 0x0000a000 0x001000>, /* ap 89 */ | |
3229 | <0x0000b000 0x0000b000 0x001000>, /* ap 90 */ | |
3230 | <0x0001c000 0x0001c000 0x001000>, /* ap 91 */ | |
3231 | <0x0001d000 0x0001d000 0x001000>, /* ap 92 */ | |
3232 | <0x0001e000 0x0001e000 0x001000>, /* ap 93 */ | |
3233 | <0x0001f000 0x0001f000 0x001000>, /* ap 94 */ | |
3234 | <0x00002000 0x00002000 0x001000>, /* ap 95 */ | |
3235 | <0x00003000 0x00003000 0x001000>; /* ap 96 */ | |
3236 | ||
3237 | target-module@2000 { /* 0x48802000, ap 95 7c.0 */ | |
3238 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
3239 | ti,hwmods = "mailbox13"; | |
3240 | reg = <0x2000 0x4>, | |
3241 | <0x2010 0x4>; | |
3242 | reg-names = "rev", "sysc"; | |
3243 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
3244 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3245 | <SYSC_IDLE_NO>, | |
3246 | <SYSC_IDLE_SMART>; | |
3247 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
3248 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>; | |
3249 | clock-names = "fck"; | |
3250 | #address-cells = <1>; | |
3251 | #size-cells = <1>; | |
3252 | ranges = <0x0 0x2000 0x1000>; | |
4ed0dfe3 TL |
3253 | |
3254 | mailbox13: mailbox@0 { | |
3255 | compatible = "ti,omap4-mailbox"; | |
3256 | reg = <0x0 0x200>; | |
3257 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, | |
3258 | <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, | |
3259 | <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, | |
3260 | <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; | |
3261 | #mbox-cells = <1>; | |
3262 | ti,mbox-num-users = <4>; | |
3263 | ti,mbox-num-fifos = <12>; | |
3264 | status = "disabled"; | |
3265 | }; | |
549fce06 TL |
3266 | }; |
3267 | ||
3268 | target-module@4000 { /* 0x48804000, ap 81 20.0 */ | |
3269 | compatible = "ti,sysc"; | |
3270 | status = "disabled"; | |
3271 | #address-cells = <1>; | |
3272 | #size-cells = <1>; | |
3273 | ranges = <0x0 0x4000 0x1000>; | |
3274 | }; | |
3275 | ||
3276 | target-module@a000 { /* 0x4880a000, ap 89 18.0 */ | |
3277 | compatible = "ti,sysc"; | |
3278 | status = "disabled"; | |
3279 | #address-cells = <1>; | |
3280 | #size-cells = <1>; | |
3281 | ranges = <0x0 0xa000 0x1000>; | |
3282 | }; | |
3283 | ||
3284 | target-module@10000 { /* 0x48810000, ap 87 28.0 */ | |
3285 | compatible = "ti,sysc"; | |
3286 | status = "disabled"; | |
3287 | #address-cells = <1>; | |
3288 | #size-cells = <1>; | |
3289 | ranges = <0x0 0x10000 0x1000>; | |
3290 | }; | |
3291 | ||
3292 | target-module@16000 { /* 0x48816000, ap 77 1e.0 */ | |
3293 | compatible = "ti,sysc"; | |
3294 | status = "disabled"; | |
3295 | #address-cells = <1>; | |
3296 | #size-cells = <1>; | |
3297 | ranges = <0x0 0x16000 0x1000>; | |
3298 | }; | |
3299 | ||
3300 | target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */ | |
3301 | compatible = "ti,sysc"; | |
3302 | status = "disabled"; | |
3303 | #address-cells = <1>; | |
3304 | #size-cells = <1>; | |
3305 | ranges = <0x0 0x1c000 0x1000>; | |
3306 | }; | |
3307 | ||
3308 | target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */ | |
3309 | compatible = "ti,sysc"; | |
3310 | status = "disabled"; | |
3311 | #address-cells = <1>; | |
3312 | #size-cells = <1>; | |
3313 | ranges = <0x0 0x1e000 0x1000>; | |
3314 | }; | |
3315 | ||
3316 | target-module@20000 { /* 0x48820000, ap 5 08.0 */ | |
3317 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
3318 | ti,hwmods = "timer5"; | |
3319 | reg = <0x20000 0x4>, | |
3320 | <0x20010 0x4>; | |
3321 | reg-names = "rev", "sysc"; | |
3322 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
3323 | SYSC_OMAP4_SOFTRESET)>; | |
3324 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3325 | <SYSC_IDLE_NO>, | |
3326 | <SYSC_IDLE_SMART>, | |
3327 | <SYSC_IDLE_SMART_WKUP>; | |
3328 | /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ | |
3329 | clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>; | |
3330 | clock-names = "fck"; | |
3331 | #address-cells = <1>; | |
3332 | #size-cells = <1>; | |
3333 | ranges = <0x0 0x20000 0x1000>; | |
4ed0dfe3 TL |
3334 | |
3335 | timer5: timer@0 { | |
3336 | compatible = "ti,omap5430-timer"; | |
3337 | reg = <0x0 0x80>; | |
3338 | clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>; | |
3339 | clock-names = "fck"; | |
3340 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
3341 | }; | |
549fce06 TL |
3342 | }; |
3343 | ||
3344 | target-module@22000 { /* 0x48822000, ap 7 24.0 */ | |
3345 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
3346 | ti,hwmods = "timer6"; | |
3347 | reg = <0x22000 0x4>, | |
3348 | <0x22010 0x4>; | |
3349 | reg-names = "rev", "sysc"; | |
3350 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
3351 | SYSC_OMAP4_SOFTRESET)>; | |
3352 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3353 | <SYSC_IDLE_NO>, | |
3354 | <SYSC_IDLE_SMART>, | |
3355 | <SYSC_IDLE_SMART_WKUP>; | |
3356 | /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ | |
3357 | clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>; | |
3358 | clock-names = "fck"; | |
3359 | #address-cells = <1>; | |
3360 | #size-cells = <1>; | |
3361 | ranges = <0x0 0x22000 0x1000>; | |
4ed0dfe3 TL |
3362 | |
3363 | timer6: timer@0 { | |
3364 | compatible = "ti,omap5430-timer"; | |
3365 | reg = <0x0 0x80>; | |
3366 | clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>; | |
3367 | clock-names = "fck"; | |
3368 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
3369 | }; | |
549fce06 TL |
3370 | }; |
3371 | ||
3372 | target-module@24000 { /* 0x48824000, ap 9 26.0 */ | |
3373 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
3374 | ti,hwmods = "timer7"; | |
3375 | reg = <0x24000 0x4>, | |
3376 | <0x24010 0x4>; | |
3377 | reg-names = "rev", "sysc"; | |
3378 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
3379 | SYSC_OMAP4_SOFTRESET)>; | |
3380 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3381 | <SYSC_IDLE_NO>, | |
3382 | <SYSC_IDLE_SMART>, | |
3383 | <SYSC_IDLE_SMART_WKUP>; | |
3384 | /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ | |
3385 | clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>; | |
3386 | clock-names = "fck"; | |
3387 | #address-cells = <1>; | |
3388 | #size-cells = <1>; | |
3389 | ranges = <0x0 0x24000 0x1000>; | |
4ed0dfe3 TL |
3390 | |
3391 | timer7: timer@0 { | |
3392 | compatible = "ti,omap5430-timer"; | |
3393 | reg = <0x0 0x80>; | |
3394 | clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>; | |
3395 | clock-names = "fck"; | |
3396 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
3397 | }; | |
549fce06 TL |
3398 | }; |
3399 | ||
3400 | target-module@26000 { /* 0x48826000, ap 11 0c.0 */ | |
3401 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
3402 | ti,hwmods = "timer8"; | |
3403 | reg = <0x26000 0x4>, | |
3404 | <0x26010 0x4>; | |
3405 | reg-names = "rev", "sysc"; | |
3406 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
3407 | SYSC_OMAP4_SOFTRESET)>; | |
3408 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3409 | <SYSC_IDLE_NO>, | |
3410 | <SYSC_IDLE_SMART>, | |
3411 | <SYSC_IDLE_SMART_WKUP>; | |
3412 | /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ | |
3413 | clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>; | |
3414 | clock-names = "fck"; | |
3415 | #address-cells = <1>; | |
3416 | #size-cells = <1>; | |
3417 | ranges = <0x0 0x26000 0x1000>; | |
4ed0dfe3 TL |
3418 | |
3419 | timer8: timer@0 { | |
3420 | compatible = "ti,omap5430-timer"; | |
3421 | reg = <0x0 0x80>; | |
3422 | clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>; | |
3423 | clock-names = "fck"; | |
3424 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
3425 | }; | |
549fce06 TL |
3426 | }; |
3427 | ||
3428 | target-module@28000 { /* 0x48828000, ap 13 16.0 */ | |
3429 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
3430 | ti,hwmods = "timer13"; | |
3431 | reg = <0x28000 0x4>, | |
3432 | <0x28010 0x4>; | |
3433 | reg-names = "rev", "sysc"; | |
3434 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
3435 | SYSC_OMAP4_SOFTRESET)>; | |
3436 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3437 | <SYSC_IDLE_NO>, | |
3438 | <SYSC_IDLE_SMART>, | |
3439 | <SYSC_IDLE_SMART_WKUP>; | |
3440 | /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ | |
3441 | clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>; | |
3442 | clock-names = "fck"; | |
3443 | #address-cells = <1>; | |
3444 | #size-cells = <1>; | |
3445 | ranges = <0x0 0x28000 0x1000>; | |
4ed0dfe3 TL |
3446 | |
3447 | timer13: timer@0 { | |
3448 | compatible = "ti,omap5430-timer"; | |
3449 | reg = <0x0 0x80>; | |
3450 | clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>; | |
3451 | clock-names = "fck"; | |
3452 | interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; | |
3453 | }; | |
549fce06 TL |
3454 | }; |
3455 | ||
3456 | target-module@2a000 { /* 0x4882a000, ap 15 10.0 */ | |
3457 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
3458 | ti,hwmods = "timer14"; | |
3459 | reg = <0x2a000 0x4>, | |
3460 | <0x2a010 0x4>; | |
3461 | reg-names = "rev", "sysc"; | |
3462 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
3463 | SYSC_OMAP4_SOFTRESET)>; | |
3464 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3465 | <SYSC_IDLE_NO>, | |
3466 | <SYSC_IDLE_SMART>, | |
3467 | <SYSC_IDLE_SMART_WKUP>; | |
3468 | /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ | |
3469 | clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>; | |
3470 | clock-names = "fck"; | |
3471 | #address-cells = <1>; | |
3472 | #size-cells = <1>; | |
3473 | ranges = <0x0 0x2a000 0x1000>; | |
4ed0dfe3 TL |
3474 | |
3475 | timer14: timer@0 { | |
3476 | compatible = "ti,omap5430-timer"; | |
3477 | reg = <0x0 0x80>; | |
3478 | clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>; | |
3479 | clock-names = "fck"; | |
3480 | interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; | |
3481 | }; | |
549fce06 TL |
3482 | }; |
3483 | ||
3484 | target-module@2c000 { /* 0x4882c000, ap 17 02.0 */ | |
3485 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
3486 | ti,hwmods = "timer15"; | |
3487 | reg = <0x2c000 0x4>, | |
3488 | <0x2c010 0x4>; | |
3489 | reg-names = "rev", "sysc"; | |
3490 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
3491 | SYSC_OMAP4_SOFTRESET)>; | |
3492 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3493 | <SYSC_IDLE_NO>, | |
3494 | <SYSC_IDLE_SMART>, | |
3495 | <SYSC_IDLE_SMART_WKUP>; | |
3496 | /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ | |
3497 | clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>; | |
3498 | clock-names = "fck"; | |
3499 | #address-cells = <1>; | |
3500 | #size-cells = <1>; | |
3501 | ranges = <0x0 0x2c000 0x1000>; | |
4ed0dfe3 TL |
3502 | |
3503 | timer15: timer@0 { | |
3504 | compatible = "ti,omap5430-timer"; | |
3505 | reg = <0x0 0x80>; | |
3506 | clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; | |
3507 | clock-names = "fck"; | |
3508 | interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; | |
3509 | }; | |
549fce06 TL |
3510 | }; |
3511 | ||
3512 | target-module@2e000 { /* 0x4882e000, ap 19 14.0 */ | |
3513 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
3514 | ti,hwmods = "timer16"; | |
3515 | reg = <0x2e000 0x4>, | |
3516 | <0x2e010 0x4>; | |
3517 | reg-names = "rev", "sysc"; | |
3518 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
3519 | SYSC_OMAP4_SOFTRESET)>; | |
3520 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3521 | <SYSC_IDLE_NO>, | |
3522 | <SYSC_IDLE_SMART>, | |
3523 | <SYSC_IDLE_SMART_WKUP>; | |
3524 | /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ | |
3525 | clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>; | |
3526 | clock-names = "fck"; | |
3527 | #address-cells = <1>; | |
3528 | #size-cells = <1>; | |
3529 | ranges = <0x0 0x2e000 0x1000>; | |
4ed0dfe3 TL |
3530 | |
3531 | timer16: timer@0 { | |
3532 | compatible = "ti,omap5430-timer"; | |
3533 | reg = <0x0 0x80>; | |
3534 | clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; | |
3535 | clock-names = "fck"; | |
3536 | interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; | |
3537 | }; | |
549fce06 TL |
3538 | }; |
3539 | ||
f7b9cb94 | 3540 | rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */ |
549fce06 TL |
3541 | compatible = "ti,sysc-omap4-simple", "ti,sysc"; |
3542 | ti,hwmods = "rtcss"; | |
3543 | reg = <0x38074 0x4>, | |
3544 | <0x38078 0x4>; | |
3545 | reg-names = "rev", "sysc"; | |
3546 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3547 | <SYSC_IDLE_NO>, | |
3548 | <SYSC_IDLE_SMART>, | |
3549 | <SYSC_IDLE_SMART_WKUP>; | |
3550 | /* Domains (P, C): rtc_pwrdm, rtc_clkdm */ | |
3551 | clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>; | |
3552 | clock-names = "fck"; | |
3553 | #address-cells = <1>; | |
3554 | #size-cells = <1>; | |
3555 | ranges = <0x0 0x38000 0x1000>; | |
4ed0dfe3 TL |
3556 | |
3557 | rtc: rtc@0 { | |
3558 | compatible = "ti,am3352-rtc"; | |
3559 | reg = <0x0 0x100>; | |
3560 | interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, | |
3561 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; | |
3562 | clocks = <&sys_32k_ck>; | |
3563 | }; | |
549fce06 TL |
3564 | }; |
3565 | ||
3566 | target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */ | |
3567 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
3568 | ti,hwmods = "mailbox2"; | |
3569 | reg = <0x3a000 0x4>, | |
3570 | <0x3a010 0x4>; | |
3571 | reg-names = "rev", "sysc"; | |
3572 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
3573 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3574 | <SYSC_IDLE_NO>, | |
3575 | <SYSC_IDLE_SMART>; | |
3576 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
3577 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>; | |
3578 | clock-names = "fck"; | |
3579 | #address-cells = <1>; | |
3580 | #size-cells = <1>; | |
3581 | ranges = <0x0 0x3a000 0x1000>; | |
4ed0dfe3 TL |
3582 | |
3583 | mailbox2: mailbox@0 { | |
3584 | compatible = "ti,omap4-mailbox"; | |
3585 | reg = <0x0 0x200>; | |
3586 | interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, | |
3587 | <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, | |
3588 | <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, | |
3589 | <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; | |
3590 | #mbox-cells = <1>; | |
3591 | ti,mbox-num-users = <4>; | |
3592 | ti,mbox-num-fifos = <12>; | |
3593 | status = "disabled"; | |
3594 | }; | |
549fce06 TL |
3595 | }; |
3596 | ||
3597 | target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */ | |
3598 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
3599 | ti,hwmods = "mailbox3"; | |
3600 | reg = <0x3c000 0x4>, | |
3601 | <0x3c010 0x4>; | |
3602 | reg-names = "rev", "sysc"; | |
3603 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
3604 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3605 | <SYSC_IDLE_NO>, | |
3606 | <SYSC_IDLE_SMART>; | |
3607 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
3608 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>; | |
3609 | clock-names = "fck"; | |
3610 | #address-cells = <1>; | |
3611 | #size-cells = <1>; | |
3612 | ranges = <0x0 0x3c000 0x1000>; | |
4ed0dfe3 TL |
3613 | |
3614 | mailbox3: mailbox@0 { | |
3615 | compatible = "ti,omap4-mailbox"; | |
3616 | reg = <0x0 0x200>; | |
3617 | interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, | |
3618 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, | |
3619 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, | |
3620 | <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; | |
3621 | #mbox-cells = <1>; | |
3622 | ti,mbox-num-users = <4>; | |
3623 | ti,mbox-num-fifos = <12>; | |
3624 | status = "disabled"; | |
3625 | }; | |
549fce06 TL |
3626 | }; |
3627 | ||
3628 | target-module@3e000 { /* 0x4883e000, ap 37 46.0 */ | |
3629 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
3630 | ti,hwmods = "mailbox4"; | |
3631 | reg = <0x3e000 0x4>, | |
3632 | <0x3e010 0x4>; | |
3633 | reg-names = "rev", "sysc"; | |
3634 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
3635 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3636 | <SYSC_IDLE_NO>, | |
3637 | <SYSC_IDLE_SMART>; | |
3638 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
3639 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>; | |
3640 | clock-names = "fck"; | |
3641 | #address-cells = <1>; | |
3642 | #size-cells = <1>; | |
3643 | ranges = <0x0 0x3e000 0x1000>; | |
4ed0dfe3 TL |
3644 | |
3645 | mailbox4: mailbox@0 { | |
3646 | compatible = "ti,omap4-mailbox"; | |
3647 | reg = <0x0 0x200>; | |
3648 | interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, | |
3649 | <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, | |
3650 | <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, | |
3651 | <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; | |
3652 | #mbox-cells = <1>; | |
3653 | ti,mbox-num-users = <4>; | |
3654 | ti,mbox-num-fifos = <12>; | |
3655 | status = "disabled"; | |
3656 | }; | |
549fce06 TL |
3657 | }; |
3658 | ||
3659 | target-module@40000 { /* 0x48840000, ap 39 64.0 */ | |
3660 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
3661 | ti,hwmods = "mailbox5"; | |
3662 | reg = <0x40000 0x4>, | |
3663 | <0x40010 0x4>; | |
3664 | reg-names = "rev", "sysc"; | |
3665 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
3666 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3667 | <SYSC_IDLE_NO>, | |
3668 | <SYSC_IDLE_SMART>; | |
3669 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
3670 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>; | |
3671 | clock-names = "fck"; | |
3672 | #address-cells = <1>; | |
3673 | #size-cells = <1>; | |
3674 | ranges = <0x0 0x40000 0x1000>; | |
4ed0dfe3 TL |
3675 | |
3676 | mailbox5: mailbox@0 { | |
3677 | compatible = "ti,omap4-mailbox"; | |
3678 | reg = <0x0 0x200>; | |
3679 | interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, | |
3680 | <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, | |
3681 | <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, | |
3682 | <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; | |
3683 | #mbox-cells = <1>; | |
3684 | ti,mbox-num-users = <4>; | |
3685 | ti,mbox-num-fifos = <12>; | |
3686 | status = "disabled"; | |
3687 | }; | |
549fce06 TL |
3688 | }; |
3689 | ||
3690 | target-module@42000 { /* 0x48842000, ap 41 4e.0 */ | |
3691 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
3692 | ti,hwmods = "mailbox6"; | |
3693 | reg = <0x42000 0x4>, | |
3694 | <0x42010 0x4>; | |
3695 | reg-names = "rev", "sysc"; | |
3696 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
3697 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3698 | <SYSC_IDLE_NO>, | |
3699 | <SYSC_IDLE_SMART>; | |
3700 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
3701 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>; | |
3702 | clock-names = "fck"; | |
3703 | #address-cells = <1>; | |
3704 | #size-cells = <1>; | |
3705 | ranges = <0x0 0x42000 0x1000>; | |
4ed0dfe3 TL |
3706 | |
3707 | mailbox6: mailbox@0 { | |
3708 | compatible = "ti,omap4-mailbox"; | |
3709 | reg = <0x0 0x200>; | |
3710 | interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, | |
3711 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, | |
3712 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, | |
3713 | <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; | |
3714 | #mbox-cells = <1>; | |
3715 | ti,mbox-num-users = <4>; | |
3716 | ti,mbox-num-fifos = <12>; | |
3717 | status = "disabled"; | |
3718 | }; | |
549fce06 TL |
3719 | }; |
3720 | ||
3721 | target-module@44000 { /* 0x48844000, ap 43 42.0 */ | |
3722 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
3723 | ti,hwmods = "mailbox7"; | |
3724 | reg = <0x44000 0x4>, | |
3725 | <0x44010 0x4>; | |
3726 | reg-names = "rev", "sysc"; | |
3727 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
3728 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3729 | <SYSC_IDLE_NO>, | |
3730 | <SYSC_IDLE_SMART>; | |
3731 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
3732 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>; | |
3733 | clock-names = "fck"; | |
3734 | #address-cells = <1>; | |
3735 | #size-cells = <1>; | |
3736 | ranges = <0x0 0x44000 0x1000>; | |
4ed0dfe3 TL |
3737 | |
3738 | mailbox7: mailbox@0 { | |
3739 | compatible = "ti,omap4-mailbox"; | |
3740 | reg = <0x0 0x200>; | |
3741 | interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, | |
3742 | <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, | |
3743 | <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, | |
3744 | <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; | |
3745 | #mbox-cells = <1>; | |
3746 | ti,mbox-num-users = <4>; | |
3747 | ti,mbox-num-fifos = <12>; | |
3748 | status = "disabled"; | |
3749 | }; | |
549fce06 TL |
3750 | }; |
3751 | ||
3752 | target-module@46000 { /* 0x48846000, ap 45 48.0 */ | |
3753 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
3754 | ti,hwmods = "mailbox8"; | |
3755 | reg = <0x46000 0x4>, | |
3756 | <0x46010 0x4>; | |
3757 | reg-names = "rev", "sysc"; | |
3758 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
3759 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3760 | <SYSC_IDLE_NO>, | |
3761 | <SYSC_IDLE_SMART>; | |
3762 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
3763 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>; | |
3764 | clock-names = "fck"; | |
3765 | #address-cells = <1>; | |
3766 | #size-cells = <1>; | |
3767 | ranges = <0x0 0x46000 0x1000>; | |
4ed0dfe3 TL |
3768 | |
3769 | mailbox8: mailbox@0 { | |
3770 | compatible = "ti,omap4-mailbox"; | |
3771 | reg = <0x0 0x200>; | |
3772 | interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, | |
3773 | <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, | |
3774 | <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, | |
3775 | <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; | |
3776 | #mbox-cells = <1>; | |
3777 | ti,mbox-num-users = <4>; | |
3778 | ti,mbox-num-fifos = <12>; | |
3779 | status = "disabled"; | |
3780 | }; | |
549fce06 TL |
3781 | }; |
3782 | ||
3783 | target-module@48000 { /* 0x48848000, ap 47 36.0 */ | |
3784 | compatible = "ti,sysc"; | |
3785 | status = "disabled"; | |
3786 | #address-cells = <1>; | |
3787 | #size-cells = <1>; | |
3788 | ranges = <0x0 0x48000 0x1000>; | |
3789 | }; | |
3790 | ||
3791 | target-module@4a000 { /* 0x4884a000, ap 49 38.0 */ | |
3792 | compatible = "ti,sysc"; | |
3793 | status = "disabled"; | |
3794 | #address-cells = <1>; | |
3795 | #size-cells = <1>; | |
3796 | ranges = <0x0 0x4a000 0x1000>; | |
3797 | }; | |
3798 | ||
3799 | target-module@4c000 { /* 0x4884c000, ap 51 44.0 */ | |
3800 | compatible = "ti,sysc"; | |
3801 | status = "disabled"; | |
3802 | #address-cells = <1>; | |
3803 | #size-cells = <1>; | |
3804 | ranges = <0x0 0x4c000 0x1000>; | |
3805 | }; | |
3806 | ||
3807 | target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */ | |
3808 | compatible = "ti,sysc"; | |
3809 | status = "disabled"; | |
3810 | #address-cells = <1>; | |
3811 | #size-cells = <1>; | |
3812 | ranges = <0x0 0x4e000 0x1000>; | |
3813 | }; | |
3814 | ||
3815 | target-module@50000 { /* 0x48850000, ap 55 40.0 */ | |
3816 | compatible = "ti,sysc"; | |
3817 | status = "disabled"; | |
3818 | #address-cells = <1>; | |
3819 | #size-cells = <1>; | |
3820 | ranges = <0x0 0x50000 0x1000>; | |
3821 | }; | |
3822 | ||
3823 | target-module@52000 { /* 0x48852000, ap 57 54.0 */ | |
3824 | compatible = "ti,sysc"; | |
3825 | status = "disabled"; | |
3826 | #address-cells = <1>; | |
3827 | #size-cells = <1>; | |
3828 | ranges = <0x0 0x52000 0x1000>; | |
3829 | }; | |
3830 | ||
3831 | target-module@54000 { /* 0x48854000, ap 59 1a.0 */ | |
3832 | compatible = "ti,sysc"; | |
3833 | status = "disabled"; | |
3834 | #address-cells = <1>; | |
3835 | #size-cells = <1>; | |
3836 | ranges = <0x0 0x54000 0x1000>; | |
3837 | }; | |
3838 | ||
3839 | target-module@56000 { /* 0x48856000, ap 61 22.0 */ | |
3840 | compatible = "ti,sysc"; | |
3841 | status = "disabled"; | |
3842 | #address-cells = <1>; | |
3843 | #size-cells = <1>; | |
3844 | ranges = <0x0 0x56000 0x1000>; | |
3845 | }; | |
3846 | ||
3847 | target-module@58000 { /* 0x48858000, ap 63 2a.0 */ | |
3848 | compatible = "ti,sysc"; | |
3849 | status = "disabled"; | |
3850 | #address-cells = <1>; | |
3851 | #size-cells = <1>; | |
3852 | ranges = <0x0 0x58000 0x1000>; | |
3853 | }; | |
3854 | ||
3855 | target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */ | |
3856 | compatible = "ti,sysc"; | |
3857 | status = "disabled"; | |
3858 | #address-cells = <1>; | |
3859 | #size-cells = <1>; | |
3860 | ranges = <0x0 0x5a000 0x1000>; | |
3861 | }; | |
3862 | ||
3863 | target-module@5c000 { /* 0x4885c000, ap 31 32.0 */ | |
3864 | compatible = "ti,sysc"; | |
3865 | status = "disabled"; | |
3866 | #address-cells = <1>; | |
3867 | #size-cells = <1>; | |
3868 | ranges = <0x0 0x5c000 0x1000>; | |
3869 | }; | |
3870 | ||
3871 | target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */ | |
3872 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
3873 | ti,hwmods = "mailbox9"; | |
3874 | reg = <0x5e000 0x4>, | |
3875 | <0x5e010 0x4>; | |
3876 | reg-names = "rev", "sysc"; | |
3877 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
3878 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3879 | <SYSC_IDLE_NO>, | |
3880 | <SYSC_IDLE_SMART>; | |
3881 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
3882 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>; | |
3883 | clock-names = "fck"; | |
3884 | #address-cells = <1>; | |
3885 | #size-cells = <1>; | |
3886 | ranges = <0x0 0x5e000 0x1000>; | |
4ed0dfe3 TL |
3887 | |
3888 | mailbox9: mailbox@0 { | |
3889 | compatible = "ti,omap4-mailbox"; | |
3890 | reg = <0x0 0x200>; | |
3891 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, | |
3892 | <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, | |
3893 | <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, | |
3894 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; | |
3895 | #mbox-cells = <1>; | |
3896 | ti,mbox-num-users = <4>; | |
3897 | ti,mbox-num-fifos = <12>; | |
3898 | status = "disabled"; | |
3899 | }; | |
549fce06 TL |
3900 | }; |
3901 | ||
3902 | target-module@60000 { /* 0x48860000, ap 71 4a.0 */ | |
3903 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
3904 | ti,hwmods = "mailbox10"; | |
3905 | reg = <0x60000 0x4>, | |
3906 | <0x60010 0x4>; | |
3907 | reg-names = "rev", "sysc"; | |
3908 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
3909 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3910 | <SYSC_IDLE_NO>, | |
3911 | <SYSC_IDLE_SMART>; | |
3912 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
3913 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>; | |
3914 | clock-names = "fck"; | |
3915 | #address-cells = <1>; | |
3916 | #size-cells = <1>; | |
3917 | ranges = <0x0 0x60000 0x1000>; | |
4ed0dfe3 TL |
3918 | |
3919 | mailbox10: mailbox@0 { | |
3920 | compatible = "ti,omap4-mailbox"; | |
3921 | reg = <0x0 0x200>; | |
3922 | interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, | |
3923 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, | |
3924 | <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, | |
3925 | <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; | |
3926 | #mbox-cells = <1>; | |
3927 | ti,mbox-num-users = <4>; | |
3928 | ti,mbox-num-fifos = <12>; | |
3929 | status = "disabled"; | |
3930 | }; | |
549fce06 TL |
3931 | }; |
3932 | ||
3933 | target-module@62000 { /* 0x48862000, ap 73 74.0 */ | |
3934 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
3935 | ti,hwmods = "mailbox11"; | |
3936 | reg = <0x62000 0x4>, | |
3937 | <0x62010 0x4>; | |
3938 | reg-names = "rev", "sysc"; | |
3939 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
3940 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3941 | <SYSC_IDLE_NO>, | |
3942 | <SYSC_IDLE_SMART>; | |
3943 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
3944 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>; | |
3945 | clock-names = "fck"; | |
3946 | #address-cells = <1>; | |
3947 | #size-cells = <1>; | |
3948 | ranges = <0x0 0x62000 0x1000>; | |
4ed0dfe3 TL |
3949 | |
3950 | mailbox11: mailbox@0 { | |
3951 | compatible = "ti,omap4-mailbox"; | |
3952 | reg = <0x0 0x200>; | |
3953 | interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, | |
3954 | <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, | |
3955 | <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, | |
3956 | <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; | |
3957 | #mbox-cells = <1>; | |
3958 | ti,mbox-num-users = <4>; | |
3959 | ti,mbox-num-fifos = <12>; | |
3960 | status = "disabled"; | |
3961 | }; | |
549fce06 TL |
3962 | }; |
3963 | ||
3964 | target-module@64000 { /* 0x48864000, ap 67 52.0 */ | |
3965 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
3966 | ti,hwmods = "mailbox12"; | |
3967 | reg = <0x64000 0x4>, | |
3968 | <0x64010 0x4>; | |
3969 | reg-names = "rev", "sysc"; | |
3970 | ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; | |
3971 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
3972 | <SYSC_IDLE_NO>, | |
3973 | <SYSC_IDLE_SMART>; | |
3974 | /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ | |
3975 | clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>; | |
3976 | clock-names = "fck"; | |
3977 | #address-cells = <1>; | |
3978 | #size-cells = <1>; | |
3979 | ranges = <0x0 0x64000 0x1000>; | |
4ed0dfe3 TL |
3980 | |
3981 | mailbox12: mailbox@0 { | |
3982 | compatible = "ti,omap4-mailbox"; | |
3983 | reg = <0x0 0x200>; | |
3984 | interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, | |
3985 | <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, | |
3986 | <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, | |
3987 | <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; | |
3988 | #mbox-cells = <1>; | |
3989 | ti,mbox-num-users = <4>; | |
3990 | ti,mbox-num-fifos = <12>; | |
3991 | status = "disabled"; | |
3992 | }; | |
549fce06 TL |
3993 | }; |
3994 | ||
3995 | target-module@80000 { /* 0x48880000, ap 83 0e.1 */ | |
3996 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
3997 | ti,hwmods = "usb_otg_ss1"; | |
3998 | reg = <0x80000 0x4>, | |
3999 | <0x80010 0x4>; | |
4000 | reg-names = "rev", "sysc"; | |
4001 | ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; | |
4002 | ti,sysc-midle = <SYSC_IDLE_FORCE>, | |
4003 | <SYSC_IDLE_NO>, | |
4004 | <SYSC_IDLE_SMART>, | |
4005 | <SYSC_IDLE_SMART_WKUP>; | |
4006 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
4007 | <SYSC_IDLE_NO>, | |
4008 | <SYSC_IDLE_SMART>, | |
4009 | <SYSC_IDLE_SMART_WKUP>; | |
4010 | /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ | |
4011 | clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>; | |
4012 | clock-names = "fck"; | |
4013 | #address-cells = <1>; | |
4014 | #size-cells = <1>; | |
4015 | ranges = <0x0 0x80000 0x20000>; | |
4ed0dfe3 TL |
4016 | |
4017 | omap_dwc3_1: omap_dwc3_1@0 { | |
4018 | compatible = "ti,dwc3"; | |
4019 | reg = <0x0 0x10000>; | |
4020 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
4021 | #address-cells = <1>; | |
4022 | #size-cells = <1>; | |
4023 | utmi-mode = <2>; | |
4024 | ranges = <0 0 0x20000>; | |
4025 | ||
4026 | usb1: usb@10000 { | |
4027 | compatible = "snps,dwc3"; | |
4028 | reg = <0x10000 0x17000>; | |
4029 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, | |
4030 | <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, | |
4031 | <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | |
4032 | interrupt-names = "peripheral", | |
4033 | "host", | |
4034 | "otg"; | |
4035 | phys = <&usb2_phy1>, <&usb3_phy1>; | |
4036 | phy-names = "usb2-phy", "usb3-phy"; | |
4037 | maximum-speed = "super-speed"; | |
4038 | dr_mode = "otg"; | |
4039 | snps,dis_u3_susphy_quirk; | |
4040 | snps,dis_u2_susphy_quirk; | |
4041 | }; | |
4042 | }; | |
549fce06 TL |
4043 | }; |
4044 | ||
4045 | target-module@c0000 { /* 0x488c0000, ap 79 06.0 */ | |
4046 | compatible = "ti,sysc-omap4", "ti,sysc"; | |
4047 | ti,hwmods = "usb_otg_ss2"; | |
4048 | reg = <0xc0000 0x4>, | |
4049 | <0xc0010 0x4>; | |
4050 | reg-names = "rev", "sysc"; | |
4051 | ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; | |
4052 | ti,sysc-midle = <SYSC_IDLE_FORCE>, | |
4053 | <SYSC_IDLE_NO>, | |
4054 | <SYSC_IDLE_SMART>, | |
4055 | <SYSC_IDLE_SMART_WKUP>; | |
4056 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
4057 | <SYSC_IDLE_NO>, | |
4058 | <SYSC_IDLE_SMART>, | |
4059 | <SYSC_IDLE_SMART_WKUP>; | |
4060 | /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ | |
4061 | clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>; | |
4062 | clock-names = "fck"; | |
4063 | #address-cells = <1>; | |
4064 | #size-cells = <1>; | |
4065 | ranges = <0x0 0xc0000 0x20000>; | |
4ed0dfe3 TL |
4066 | |
4067 | omap_dwc3_2: omap_dwc3_2@0 { | |
4068 | compatible = "ti,dwc3"; | |
4069 | reg = <0x0 0x10000>; | |
4070 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
4071 | #address-cells = <1>; | |
4072 | #size-cells = <1>; | |
4073 | utmi-mode = <2>; | |
4074 | ranges = <0 0 0x20000>; | |
4075 | ||
4076 | usb2: usb@10000 { | |
4077 | compatible = "snps,dwc3"; | |
4078 | reg = <0x10000 0x17000>; | |
4079 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, | |
4080 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, | |
4081 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
4082 | interrupt-names = "peripheral", | |
4083 | "host", | |
4084 | "otg"; | |
4085 | phys = <&usb2_phy2>; | |
4086 | phy-names = "usb2-phy"; | |
4087 | maximum-speed = "high-speed"; | |
4088 | dr_mode = "otg"; | |
4089 | snps,dis_u3_susphy_quirk; | |
4090 | snps,dis_u2_susphy_quirk; | |
4091 | snps,dis_metastability_quirk; | |
4092 | }; | |
4093 | }; | |
549fce06 TL |
4094 | }; |
4095 | ||
bcbb63b8 | 4096 | usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */ |
549fce06 TL |
4097 | compatible = "ti,sysc-omap4", "ti,sysc"; |
4098 | ti,hwmods = "usb_otg_ss3"; | |
4099 | reg = <0x100000 0x4>, | |
4100 | <0x100010 0x4>; | |
4101 | reg-names = "rev", "sysc"; | |
4102 | ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; | |
4103 | ti,sysc-midle = <SYSC_IDLE_FORCE>, | |
4104 | <SYSC_IDLE_NO>, | |
4105 | <SYSC_IDLE_SMART>, | |
4106 | <SYSC_IDLE_SMART_WKUP>; | |
4107 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
4108 | <SYSC_IDLE_NO>, | |
4109 | <SYSC_IDLE_SMART>, | |
4110 | <SYSC_IDLE_SMART_WKUP>; | |
4111 | /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ | |
4112 | clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>; | |
4113 | clock-names = "fck"; | |
4114 | #address-cells = <1>; | |
4115 | #size-cells = <1>; | |
4116 | ranges = <0x0 0x100000 0x20000>; | |
4ed0dfe3 TL |
4117 | |
4118 | omap_dwc3_3: omap_dwc3_3@0 { | |
4119 | compatible = "ti,dwc3"; | |
4120 | reg = <0x0 0x10000>; | |
4121 | interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; | |
4122 | #address-cells = <1>; | |
4123 | #size-cells = <1>; | |
4124 | utmi-mode = <2>; | |
4125 | ranges = <0 0 0x20000>; | |
4126 | status = "disabled"; | |
4127 | ||
4128 | usb3: usb@10000 { | |
4129 | compatible = "snps,dwc3"; | |
4130 | reg = <0x10000 0x17000>; | |
4131 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, | |
4132 | <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, | |
4133 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; | |
4134 | interrupt-names = "peripheral", | |
4135 | "host", | |
4136 | "otg"; | |
4137 | maximum-speed = "high-speed"; | |
4138 | dr_mode = "otg"; | |
4139 | snps,dis_u3_susphy_quirk; | |
4140 | snps,dis_u2_susphy_quirk; | |
4141 | }; | |
4142 | }; | |
549fce06 TL |
4143 | }; |
4144 | ||
bcbb63b8 | 4145 | usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */ |
549fce06 TL |
4146 | compatible = "ti,sysc-omap4", "ti,sysc"; |
4147 | ti,hwmods = "usb_otg_ss4"; | |
4148 | reg = <0x140000 0x4>, | |
4149 | <0x140010 0x4>; | |
4150 | reg-names = "rev", "sysc"; | |
4151 | ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; | |
4152 | ti,sysc-midle = <SYSC_IDLE_FORCE>, | |
4153 | <SYSC_IDLE_NO>, | |
4154 | <SYSC_IDLE_SMART>, | |
4155 | <SYSC_IDLE_SMART_WKUP>; | |
4156 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
4157 | <SYSC_IDLE_NO>, | |
4158 | <SYSC_IDLE_SMART>, | |
4159 | <SYSC_IDLE_SMART_WKUP>; | |
4160 | /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ | |
4161 | clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>; | |
4162 | clock-names = "fck"; | |
4163 | #address-cells = <1>; | |
4164 | #size-cells = <1>; | |
4165 | ranges = <0x0 0x140000 0x20000>; | |
4166 | }; | |
4167 | ||
4168 | target-module@170000 { /* 0x48970000, ap 21 0a.0 */ | |
4169 | compatible = "ti,sysc"; | |
4170 | status = "disabled"; | |
4171 | #address-cells = <1>; | |
4172 | #size-cells = <1>; | |
4173 | ranges = <0x0 0x170000 0x10000>; | |
4174 | }; | |
4175 | ||
4176 | target-module@190000 { /* 0x48990000, ap 23 2e.0 */ | |
4177 | compatible = "ti,sysc"; | |
4178 | status = "disabled"; | |
4179 | #address-cells = <1>; | |
4180 | #size-cells = <1>; | |
4181 | ranges = <0x0 0x190000 0x10000>; | |
4182 | }; | |
4183 | ||
4184 | target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ | |
4185 | compatible = "ti,sysc"; | |
4186 | status = "disabled"; | |
4187 | #address-cells = <1>; | |
4188 | #size-cells = <1>; | |
4189 | ranges = <0x0 0x1b0000 0x10000>; | |
4190 | }; | |
4191 | ||
4192 | target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */ | |
4193 | compatible = "ti,sysc"; | |
4194 | status = "disabled"; | |
4195 | #address-cells = <1>; | |
4196 | #size-cells = <1>; | |
4197 | ranges = <0x0 0x1d0000 0x10000>; | |
4198 | }; | |
4199 | }; | |
4200 | }; | |
4201 | ||
4202 | &l4_wkup { /* 0x4ae00000 */ | |
4203 | compatible = "ti,dra7-l4-wkup", "simple-bus"; | |
4204 | reg = <0x4ae00000 0x800>, | |
4205 | <0x4ae00800 0x800>, | |
4206 | <0x4ae01000 0x1000>; | |
4207 | reg-names = "ap", "la", "ia0"; | |
4208 | #address-cells = <1>; | |
4209 | #size-cells = <1>; | |
4210 | ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ | |
4211 | <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ | |
4212 | <0x00020000 0x4ae20000 0x010000>, /* segment 2 */ | |
4213 | <0x00030000 0x4ae30000 0x010000>; /* segment 3 */ | |
4214 | ||
4215 | segment@0 { /* 0x4ae00000 */ | |
4216 | compatible = "simple-bus"; | |
4217 | #address-cells = <1>; | |
4218 | #size-cells = <1>; | |
4219 | ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ | |
4220 | <0x00001000 0x00001000 0x001000>, /* ap 1 */ | |
4221 | <0x00000800 0x00000800 0x000800>, /* ap 2 */ | |
4222 | <0x00006000 0x00006000 0x002000>, /* ap 3 */ | |
4223 | <0x00008000 0x00008000 0x001000>, /* ap 4 */ | |
4224 | <0x00004000 0x00004000 0x001000>, /* ap 15 */ | |
4225 | <0x00005000 0x00005000 0x001000>, /* ap 16 */ | |
4226 | <0x0000c000 0x0000c000 0x001000>, /* ap 17 */ | |
4227 | <0x0000d000 0x0000d000 0x001000>; /* ap 18 */ | |
4228 | ||
4229 | target-module@4000 { /* 0x4ae04000, ap 15 40.0 */ | |
4230 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
4231 | ti,hwmods = "counter_32k"; | |
4232 | reg = <0x4000 0x4>, | |
4233 | <0x4010 0x4>; | |
4234 | reg-names = "rev", "sysc"; | |
4235 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
4236 | <SYSC_IDLE_NO>, | |
4237 | <SYSC_IDLE_SMART>, | |
4238 | <SYSC_IDLE_SMART_WKUP>; | |
4239 | /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ | |
4240 | clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>; | |
4241 | clock-names = "fck"; | |
4242 | #address-cells = <1>; | |
4243 | #size-cells = <1>; | |
4244 | ranges = <0x0 0x4000 0x1000>; | |
4ed0dfe3 TL |
4245 | |
4246 | counter32k: counter@0 { | |
4247 | compatible = "ti,omap-counter32k"; | |
4248 | reg = <0x0 0x40>; | |
4249 | }; | |
549fce06 TL |
4250 | }; |
4251 | ||
4252 | target-module@6000 { /* 0x4ae06000, ap 3 10.0 */ | |
4ed0dfe3 TL |
4253 | compatible = "ti,sysc-omap4", "ti,sysc"; |
4254 | reg = <0x6000 0x4>; | |
4255 | reg-names = "rev"; | |
549fce06 TL |
4256 | #address-cells = <1>; |
4257 | #size-cells = <1>; | |
4258 | ranges = <0x0 0x6000 0x2000>; | |
4ed0dfe3 TL |
4259 | |
4260 | prm: prm@0 { | |
4261 | compatible = "ti,dra7-prm", "simple-bus"; | |
4262 | reg = <0 0x3000>; | |
4263 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
4264 | #address-cells = <1>; | |
4265 | #size-cells = <1>; | |
4266 | ranges = <0 0 0x3000>; | |
4267 | ||
4268 | prm_clocks: clocks { | |
4269 | #address-cells = <1>; | |
4270 | #size-cells = <0>; | |
4271 | }; | |
4272 | ||
4273 | prm_clockdomains: clockdomains { | |
4274 | }; | |
4275 | }; | |
549fce06 TL |
4276 | }; |
4277 | ||
4278 | target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */ | |
4ed0dfe3 TL |
4279 | compatible = "ti,sysc-omap4", "ti,sysc"; |
4280 | reg = <0xc000 0x4>; | |
4281 | reg-names = "rev"; | |
549fce06 TL |
4282 | #address-cells = <1>; |
4283 | #size-cells = <1>; | |
4284 | ranges = <0x0 0xc000 0x1000>; | |
4ed0dfe3 TL |
4285 | |
4286 | scm_wkup: scm_conf@0 { | |
4287 | compatible = "syscon"; | |
4288 | reg = <0 0x1000>; | |
4289 | }; | |
549fce06 TL |
4290 | }; |
4291 | }; | |
4292 | ||
4293 | segment@10000 { /* 0x4ae10000 */ | |
4294 | compatible = "simple-bus"; | |
4295 | #address-cells = <1>; | |
4296 | #size-cells = <1>; | |
4297 | ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ | |
4298 | <0x00001000 0x00011000 0x001000>, /* ap 6 */ | |
4299 | <0x00004000 0x00014000 0x001000>, /* ap 7 */ | |
4300 | <0x00005000 0x00015000 0x001000>, /* ap 8 */ | |
4301 | <0x00008000 0x00018000 0x001000>, /* ap 9 */ | |
4302 | <0x00009000 0x00019000 0x001000>, /* ap 10 */ | |
4303 | <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ | |
4304 | <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ | |
4305 | ||
4306 | target-module@0 { /* 0x4ae10000, ap 5 20.0 */ | |
4307 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
4308 | ti,hwmods = "gpio1"; | |
4309 | reg = <0x0 0x4>, | |
4310 | <0x10 0x4>, | |
4311 | <0x114 0x4>; | |
4312 | reg-names = "rev", "sysc", "syss"; | |
4313 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
4314 | SYSC_OMAP2_SOFTRESET | | |
4315 | SYSC_OMAP2_AUTOIDLE)>; | |
4316 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
4317 | <SYSC_IDLE_NO>, | |
4318 | <SYSC_IDLE_SMART>, | |
4319 | <SYSC_IDLE_SMART_WKUP>; | |
4320 | ti,syss-mask = <1>; | |
4321 | /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ | |
4322 | clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>, | |
4323 | <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>; | |
4324 | clock-names = "fck", "dbclk"; | |
4325 | #address-cells = <1>; | |
4326 | #size-cells = <1>; | |
4327 | ranges = <0x0 0x0 0x1000>; | |
4ed0dfe3 TL |
4328 | |
4329 | gpio1: gpio@0 { | |
4330 | compatible = "ti,omap4-gpio"; | |
4331 | reg = <0x0 0x200>; | |
4332 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
4333 | gpio-controller; | |
4334 | #gpio-cells = <2>; | |
4335 | interrupt-controller; | |
4336 | #interrupt-cells = <2>; | |
4337 | }; | |
549fce06 TL |
4338 | }; |
4339 | ||
4340 | target-module@4000 { /* 0x4ae14000, ap 7 28.0 */ | |
4341 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
4342 | ti,hwmods = "wd_timer2"; | |
4343 | reg = <0x4000 0x4>, | |
4344 | <0x4010 0x4>, | |
4345 | <0x4014 0x4>; | |
4346 | reg-names = "rev", "sysc", "syss"; | |
4347 | ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | | |
4348 | SYSC_OMAP2_SOFTRESET)>; | |
4349 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
4350 | <SYSC_IDLE_NO>, | |
4351 | <SYSC_IDLE_SMART>, | |
4352 | <SYSC_IDLE_SMART_WKUP>; | |
4353 | ti,syss-mask = <1>; | |
4354 | /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ | |
4355 | clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>; | |
4356 | clock-names = "fck"; | |
4357 | #address-cells = <1>; | |
4358 | #size-cells = <1>; | |
4359 | ranges = <0x0 0x4000 0x1000>; | |
4ed0dfe3 TL |
4360 | |
4361 | wdt2: wdt@0 { | |
4362 | compatible = "ti,omap3-wdt"; | |
4363 | reg = <0x0 0x80>; | |
4364 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
4365 | }; | |
549fce06 TL |
4366 | }; |
4367 | ||
4368 | target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ | |
4369 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
4370 | ti,hwmods = "timer1"; | |
4371 | reg = <0x8000 0x4>, | |
4372 | <0x8010 0x4>; | |
4373 | reg-names = "rev", "sysc"; | |
4374 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
4375 | SYSC_OMAP4_SOFTRESET)>; | |
4376 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
4377 | <SYSC_IDLE_NO>, | |
4378 | <SYSC_IDLE_SMART>, | |
4379 | <SYSC_IDLE_SMART_WKUP>; | |
4380 | /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ | |
4381 | clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>; | |
4382 | clock-names = "fck"; | |
4383 | #address-cells = <1>; | |
4384 | #size-cells = <1>; | |
4385 | ranges = <0x0 0x8000 0x1000>; | |
4ed0dfe3 TL |
4386 | |
4387 | timer1: timer@0 { | |
4388 | compatible = "ti,omap5430-timer"; | |
4389 | reg = <0x0 0x80>; | |
4390 | clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; | |
4391 | clock-names = "fck"; | |
4392 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
4393 | ti,timer-alwon; | |
4394 | }; | |
549fce06 TL |
4395 | }; |
4396 | ||
4397 | target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */ | |
4398 | compatible = "ti,sysc"; | |
4399 | status = "disabled"; | |
4400 | #address-cells = <1>; | |
4401 | #size-cells = <1>; | |
4402 | ranges = <0x0 0xc000 0x1000>; | |
4403 | }; | |
4404 | }; | |
4405 | ||
4406 | segment@20000 { /* 0x4ae20000 */ | |
4407 | compatible = "simple-bus"; | |
4408 | #address-cells = <1>; | |
4409 | #size-cells = <1>; | |
4410 | ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ | |
4411 | <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ | |
4412 | <0x00000000 0x00020000 0x001000>, /* ap 19 */ | |
4413 | <0x00001000 0x00021000 0x001000>, /* ap 20 */ | |
4414 | <0x00002000 0x00022000 0x001000>, /* ap 21 */ | |
4415 | <0x00003000 0x00023000 0x001000>, /* ap 22 */ | |
4416 | <0x00007000 0x00027000 0x000400>, /* ap 23 */ | |
4417 | <0x00008000 0x00028000 0x000800>, /* ap 24 */ | |
4418 | <0x00009000 0x00029000 0x000100>, /* ap 25 */ | |
4419 | <0x00008800 0x00028800 0x000200>, /* ap 26 */ | |
4420 | <0x00008a00 0x00028a00 0x000100>, /* ap 27 */ | |
4421 | <0x0000b000 0x0002b000 0x001000>, /* ap 28 */ | |
4422 | <0x0000c000 0x0002c000 0x001000>, /* ap 29 */ | |
4423 | <0x0000f000 0x0002f000 0x001000>; /* ap 32 */ | |
4424 | ||
4425 | target-module@0 { /* 0x4ae20000, ap 19 08.0 */ | |
4426 | compatible = "ti,sysc-omap4-timer", "ti,sysc"; | |
4427 | ti,hwmods = "timer12"; | |
4428 | reg = <0x0 0x4>, | |
4429 | <0x10 0x4>; | |
4430 | reg-names = "rev", "sysc"; | |
4431 | ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | | |
4432 | SYSC_OMAP4_SOFTRESET)>; | |
4433 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
4434 | <SYSC_IDLE_NO>, | |
4435 | <SYSC_IDLE_SMART>, | |
4436 | <SYSC_IDLE_SMART_WKUP>; | |
4437 | /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ | |
4438 | clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>; | |
4439 | clock-names = "fck"; | |
4440 | #address-cells = <1>; | |
4441 | #size-cells = <1>; | |
4442 | ranges = <0x0 0x0 0x1000>; | |
4ed0dfe3 TL |
4443 | |
4444 | timer12: timer@0 { | |
4445 | compatible = "ti,omap5430-timer"; | |
4446 | reg = <0x0 0x80>; | |
4ed0dfe3 TL |
4447 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
4448 | ti,timer-alwon; | |
4449 | ti,timer-secure; | |
4450 | }; | |
549fce06 TL |
4451 | }; |
4452 | ||
4453 | target-module@2000 { /* 0x4ae22000, ap 21 18.0 */ | |
4454 | compatible = "ti,sysc"; | |
4455 | status = "disabled"; | |
4456 | #address-cells = <1>; | |
4457 | #size-cells = <1>; | |
4458 | ranges = <0x0 0x2000 0x1000>; | |
4459 | }; | |
4460 | ||
4461 | target-module@6000 { /* 0x4ae26000, ap 13 48.0 */ | |
4462 | compatible = "ti,sysc"; | |
4463 | status = "disabled"; | |
4464 | #address-cells = <1>; | |
4465 | #size-cells = <1>; | |
4466 | ranges = <0x00000000 0x00006000 0x00001000>, | |
4467 | <0x00001000 0x00007000 0x00000400>, | |
4468 | <0x00002000 0x00008000 0x00000800>, | |
4469 | <0x00002800 0x00008800 0x00000200>, | |
4470 | <0x00002a00 0x00008a00 0x00000100>, | |
4471 | <0x00003000 0x00009000 0x00000100>; | |
4472 | }; | |
4473 | ||
4474 | target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */ | |
4475 | compatible = "ti,sysc-omap2", "ti,sysc"; | |
4476 | ti,hwmods = "uart10"; | |
4477 | reg = <0xb050 0x4>, | |
4478 | <0xb054 0x4>, | |
4479 | <0xb058 0x4>; | |
4480 | reg-names = "rev", "sysc", "syss"; | |
4481 | ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | | |
4482 | SYSC_OMAP2_SOFTRESET | | |
4483 | SYSC_OMAP2_AUTOIDLE)>; | |
4484 | ti,sysc-sidle = <SYSC_IDLE_FORCE>, | |
4485 | <SYSC_IDLE_NO>, | |
4486 | <SYSC_IDLE_SMART>, | |
4487 | <SYSC_IDLE_SMART_WKUP>; | |
4488 | ti,syss-mask = <1>; | |
4489 | /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ | |
4490 | clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>; | |
4491 | clock-names = "fck"; | |
4492 | #address-cells = <1>; | |
4493 | #size-cells = <1>; | |
4494 | ranges = <0x0 0xb000 0x1000>; | |
4ed0dfe3 TL |
4495 | |
4496 | uart10: serial@0 { | |
4497 | compatible = "ti,dra742-uart", "ti,omap4-uart"; | |
4498 | reg = <0x0 0x100>; | |
4499 | interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; | |
4500 | clock-frequency = <48000000>; | |
4501 | status = "disabled"; | |
4502 | }; | |
549fce06 TL |
4503 | }; |
4504 | ||
4505 | target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */ | |
4506 | compatible = "ti,sysc"; | |
4507 | status = "disabled"; | |
4508 | #address-cells = <1>; | |
4509 | #size-cells = <1>; | |
4510 | ranges = <0x0 0xf000 0x1000>; | |
4511 | }; | |
4512 | }; | |
4513 | ||
4514 | segment@30000 { /* 0x4ae30000 */ | |
4515 | compatible = "simple-bus"; | |
4516 | #address-cells = <1>; | |
4517 | #size-cells = <1>; | |
4518 | ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */ | |
4519 | <0x0000e000 0x0003e000 0x001000>, /* ap 31 */ | |
4520 | <0x00000000 0x00030000 0x001000>, /* ap 33 */ | |
4521 | <0x00001000 0x00031000 0x001000>, /* ap 34 */ | |
4522 | <0x00002000 0x00032000 0x001000>, /* ap 35 */ | |
4523 | <0x00003000 0x00033000 0x001000>, /* ap 36 */ | |
4524 | <0x00004000 0x00034000 0x001000>, /* ap 37 */ | |
4525 | <0x00005000 0x00035000 0x001000>, /* ap 38 */ | |
4526 | <0x00006000 0x00036000 0x001000>, /* ap 39 */ | |
4527 | <0x00007000 0x00037000 0x001000>, /* ap 40 */ | |
4528 | <0x00008000 0x00038000 0x001000>, /* ap 41 */ | |
4529 | <0x00009000 0x00039000 0x001000>, /* ap 42 */ | |
4530 | <0x0000a000 0x0003a000 0x001000>; /* ap 43 */ | |
4531 | ||
4532 | target-module@1000 { /* 0x4ae31000, ap 34 60.0 */ | |
4533 | compatible = "ti,sysc"; | |
4534 | status = "disabled"; | |
4535 | #address-cells = <1>; | |
4536 | #size-cells = <1>; | |
4537 | ranges = <0x0 0x1000 0x1000>; | |
4538 | }; | |
4539 | ||
4540 | target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */ | |
4541 | compatible = "ti,sysc"; | |
4542 | status = "disabled"; | |
4543 | #address-cells = <1>; | |
4544 | #size-cells = <1>; | |
4545 | ranges = <0x0 0x3000 0x1000>; | |
4546 | }; | |
4547 | ||
4548 | target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */ | |
4549 | compatible = "ti,sysc"; | |
4550 | status = "disabled"; | |
4551 | #address-cells = <1>; | |
4552 | #size-cells = <1>; | |
4553 | ranges = <0x0 0x5000 0x1000>; | |
4554 | }; | |
4555 | ||
4556 | target-module@7000 { /* 0x4ae37000, ap 40 68.0 */ | |
4557 | compatible = "ti,sysc"; | |
4558 | status = "disabled"; | |
4559 | #address-cells = <1>; | |
4560 | #size-cells = <1>; | |
4561 | ranges = <0x0 0x7000 0x1000>; | |
4562 | }; | |
4563 | ||
4564 | target-module@9000 { /* 0x4ae39000, ap 42 70.0 */ | |
4565 | compatible = "ti,sysc"; | |
4566 | status = "disabled"; | |
4567 | #address-cells = <1>; | |
4568 | #size-cells = <1>; | |
4569 | ranges = <0x0 0x9000 0x1000>; | |
4570 | }; | |
4571 | ||
4572 | target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */ | |
4ed0dfe3 | 4573 | compatible = "ti,sysc-omap4", "ti,sysc"; |
89bbc6f1 | 4574 | reg = <0xc020 0x4>; |
4ed0dfe3 TL |
4575 | reg-names = "rev"; |
4576 | clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>; | |
4577 | clock-names = "fck"; | |
549fce06 TL |
4578 | #address-cells = <1>; |
4579 | #size-cells = <1>; | |
4580 | ranges = <0x0 0xc000 0x2000>; | |
4ed0dfe3 TL |
4581 | |
4582 | dcan1: can@0 { | |
4583 | compatible = "ti,dra7-d_can"; | |
4584 | reg = <0x0 0x2000>; | |
4585 | syscon-raminit = <&scm_conf 0x558 0>; | |
4586 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; | |
4587 | clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>; | |
4588 | status = "disabled"; | |
4589 | }; | |
549fce06 TL |
4590 | }; |
4591 | }; | |
4592 | }; | |
4593 |