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d2a37b3d DGC |
1 | /* |
2 | * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
d2a37b3d | 12 | / { |
7f107887 FE |
13 | #address-cells = <1>; |
14 | #size-cells = <1>; | |
a971c554 FE |
15 | /* |
16 | * The decompressor and also some bootloaders rely on a | |
17 | * pre-existing /chosen node to be available to insert the | |
18 | * command line and merge other ATAGS info. | |
19 | * Also for U-Boot there must be a pre-existing /memory node. | |
20 | */ | |
21 | chosen {}; | |
22 | memory { device_type = "memory"; reg = <0 0>; }; | |
7f107887 | 23 | |
d2a37b3d DGC |
24 | aliases { |
25 | serial0 = &uart1; | |
26 | serial1 = &uart2; | |
27 | serial2 = &uart3; | |
28 | serial3 = &uart4; | |
29 | serial4 = &uart5; | |
30 | }; | |
31 | ||
070bd7e4 FE |
32 | cpus { |
33 | #address-cells = <0>; | |
34 | #size-cells = <0>; | |
35 | ||
36 | cpu { | |
bc6cde35 | 37 | compatible = "arm,arm1136jf-s"; |
070bd7e4 FE |
38 | device_type = "cpu"; |
39 | }; | |
40 | }; | |
41 | ||
af92305e | 42 | avic: interrupt-controller@68000000 { |
d2a37b3d DGC |
43 | compatible = "fsl,imx31-avic", "fsl,avic"; |
44 | interrupt-controller; | |
45 | #interrupt-cells = <1>; | |
af92305e | 46 | reg = <0x68000000 0x100000>; |
d2a37b3d DGC |
47 | }; |
48 | ||
49 | soc { | |
50 | #address-cells = <1>; | |
51 | #size-cells = <1>; | |
52 | compatible = "simple-bus"; | |
53 | interrupt-parent = <&avic>; | |
54 | ranges; | |
55 | ||
56 | aips@43f00000 { /* AIPS1 */ | |
57 | compatible = "fsl,aips-bus", "simple-bus"; | |
58 | #address-cells = <1>; | |
59 | #size-cells = <1>; | |
60 | reg = <0x43f00000 0x100000>; | |
61 | ranges; | |
62 | ||
63 | uart1: serial@43f90000 { | |
64 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
65 | reg = <0x43f90000 0x4000>; | |
66 | interrupts = <45>; | |
ef0e4a60 FE |
67 | clocks = <&clks 10>, <&clks 30>; |
68 | clock-names = "ipg", "per"; | |
d2a37b3d DGC |
69 | status = "disabled"; |
70 | }; | |
71 | ||
72 | uart2: serial@43f94000 { | |
73 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
74 | reg = <0x43f94000 0x4000>; | |
75 | interrupts = <32>; | |
ef0e4a60 FE |
76 | clocks = <&clks 10>, <&clks 31>; |
77 | clock-names = "ipg", "per"; | |
d2a37b3d DGC |
78 | status = "disabled"; |
79 | }; | |
80 | ||
d8c8c70c AK |
81 | kpp: kpp@43fa8000 { |
82 | compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; | |
83 | reg = <0x43fa8000 0x4000>; | |
84 | interrupts = <24>; | |
85 | clocks = <&clks 46>; | |
86 | status = "disabled"; | |
87 | }; | |
88 | ||
d2a37b3d DGC |
89 | uart4: serial@43fb0000 { |
90 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
91 | reg = <0x43fb0000 0x4000>; | |
ef0e4a60 FE |
92 | clocks = <&clks 10>, <&clks 49>; |
93 | clock-names = "ipg", "per"; | |
d2a37b3d DGC |
94 | interrupts = <46>; |
95 | status = "disabled"; | |
96 | }; | |
97 | ||
98 | uart5: serial@43fb4000 { | |
99 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
100 | reg = <0x43fb4000 0x4000>; | |
101 | interrupts = <47>; | |
ef0e4a60 FE |
102 | clocks = <&clks 10>, <&clks 50>; |
103 | clock-names = "ipg", "per"; | |
d2a37b3d DGC |
104 | status = "disabled"; |
105 | }; | |
106 | }; | |
107 | ||
108 | spba@50000000 { | |
109 | compatible = "fsl,spba-bus", "simple-bus"; | |
110 | #address-cells = <1>; | |
111 | #size-cells = <1>; | |
112 | reg = <0x50000000 0x100000>; | |
113 | ranges; | |
114 | ||
115 | uart3: serial@5000c000 { | |
116 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | |
117 | reg = <0x5000c000 0x4000>; | |
118 | interrupts = <18>; | |
ef0e4a60 FE |
119 | clocks = <&clks 10>, <&clks 48>; |
120 | clock-names = "ipg", "per"; | |
d2a37b3d DGC |
121 | status = "disabled"; |
122 | }; | |
ef0e4a60 | 123 | |
9c5d5909 SH |
124 | iim: iim@5001c000 { |
125 | compatible = "fsl,imx31-iim", "fsl,imx27-iim"; | |
126 | reg = <0x5001c000 0x1000>; | |
127 | interrupts = <19>; | |
128 | clocks = <&clks 25>; | |
129 | }; | |
d2a37b3d | 130 | }; |
a44eed9a SH |
131 | |
132 | aips@53f00000 { /* AIPS2 */ | |
133 | compatible = "fsl,aips-bus", "simple-bus"; | |
134 | #address-cells = <1>; | |
135 | #size-cells = <1>; | |
136 | reg = <0x53f00000 0x100000>; | |
137 | ranges; | |
138 | ||
1f87aee6 VZ |
139 | clks: ccm@53f80000{ |
140 | compatible = "fsl,imx31-ccm"; | |
141 | reg = <0x53f80000 0x4000>; | |
142 | interrupts = <31>, <53>; | |
143 | #clock-cells = <1>; | |
144 | }; | |
145 | ||
a44eed9a SH |
146 | gpt: timer@53f90000 { |
147 | compatible = "fsl,imx31-gpt"; | |
148 | reg = <0x53f90000 0x4000>; | |
149 | interrupts = <29>; | |
150 | clocks = <&clks 10>, <&clks 22>; | |
151 | clock-names = "ipg", "per"; | |
152 | }; | |
153 | }; | |
d2a37b3d DGC |
154 | }; |
155 | }; |