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UBUNTU: Ubuntu-5.3.0-29.31
[mirror_ubuntu-eoan-kernel.git] / arch / arm / boot / dts / r8a7778.dtsi
CommitLineData
cdbfaf64 1// SPDX-License-Identifier: GPL-2.0
ccb7cc74 2/*
af69e340 3 * Device Tree Source for the R-Car M1A (R8A77781) SoC
ccb7cc74
KM		 4 *
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 *
8 * based on r8a7779
9 *
10 * Copyright (C) 2013 Renesas Solutions Corp.
11 * Copyright (C) 2013 Simon Horman
ccb7cc74
KM		 12 */
13
93aa970d 14#include <dt-bindings/clock/r8a7778-clock.h>
0c34bd1e 15#include <dt-bindings/interrupt-controller/arm-gic.h>
5f75e73c
LP		 16#include <dt-bindings/interrupt-controller/irq.h>
17
ccb7cc74
KM		 18/ {
19 compatible = "renesas,r8a7778";
9ff254ad 20 interrupt-parent = <&gic>;
3bc31302
GU		 21 #address-cells = <1>;
22 #size-cells = <1>;
ccb7cc74
KM		 23
24 cpus {
869f92ae
MD		 25 #address-cells = <1>;
26 #size-cells = <0>;
27
ccb7cc74 28 cpu@0 {
869f92ae 29 device_type = "cpu";
ccb7cc74 30 compatible = "arm,cortex-a9";
869f92ae
MD		 31 reg = <0>;
32 clock-frequency = <800000000>;
d3e865a3 33 clocks = <&z_clk>;
ccb7cc74
KM		 34 };
35 };
36
a50da085
KM		 37 aliases {
38 spi0 = &hspi0;
39 spi1 = &hspi1;
40 spi2 = &hspi2;
41 };
42
d4578204
UH		 43 bsc: bus@1c000000 {
44 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges = <0 0 0x1c000000>;
48 };
49
05cabb83 50 ether: ethernet@fde00000 {
1bfd9444
SH		 51 compatible = "renesas,ether-r8a7778",
52 "renesas,rcar-gen1-ether";
05cabb83 53 reg = <0xfde00000 0x400>;
0c34bd1e 54 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
05cabb83 55 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
a670f366 56 power-domains = <&cpg_clocks>;
05cabb83
UH		 57 phy-mode = "rmii";
58 #address-cells = <1>;
59 #size-cells = <0>;
60 status = "disabled";
61 };
62
ccb7cc74 63 gic: interrupt-controller@fe438000 {
26828d9e 64 compatible = "arm,pl390";
ccb7cc74
KM		 65 #interrupt-cells = <3>;
66 interrupt-controller;
67 reg = <0xfe438000 0x1000>,
68 <0xfe430000 0x100>;
69 };
0697ccc0 70
87f1ba80 71 /* irqpin: IRQ0 - IRQ3 */
b38150fa 72 irqpin: interrupt-controller@fe78001c {
d79af224 73 compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
87f1ba80
KM		 74 #interrupt-cells = <2>;
75 interrupt-controller;
76 status = "disabled"; /* default off */
77 reg = <0xfe78001c 4>,
78 <0xfe780010 4>,
79 <0xfe780024 4>,
80 <0xfe780044 4>,
81 <0xfe780064 4>;
0c34bd1e
SH		 82 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
83 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
84 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
85 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
87f1ba80
KM		 86 sense-bitfield-width = <2>;
87 };
88
aaf7eda8 89 gpio0: gpio@ffc40000 {
9b43ba66 90 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
aaf7eda8 91 reg = <0xffc40000 0x2c>;
0c34bd1e 92 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
aaf7eda8
LP		 93 #gpio-cells = <2>;
94 gpio-controller;
95 gpio-ranges = <&pfc 0 0 32>;
96 #interrupt-cells = <2>;
97 interrupt-controller;
98 };
99
100 gpio1: gpio@ffc41000 {
9b43ba66 101 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
aaf7eda8 102 reg = <0xffc41000 0x2c>;
0c34bd1e 103 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
aaf7eda8
LP		 104 #gpio-cells = <2>;
105 gpio-controller;
106 gpio-ranges = <&pfc 0 32 32>;
107 #interrupt-cells = <2>;
108 interrupt-controller;
109 };
110
111 gpio2: gpio@ffc42000 {
9b43ba66 112 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
aaf7eda8 113 reg = <0xffc42000 0x2c>;
0c34bd1e 114 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
aaf7eda8
LP		 115 #gpio-cells = <2>;
116 gpio-controller;
117 gpio-ranges = <&pfc 0 64 32>;
118 #interrupt-cells = <2>;
119 interrupt-controller;
120 };
121
122 gpio3: gpio@ffc43000 {
9b43ba66 123 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
aaf7eda8 124 reg = <0xffc43000 0x2c>;
0c34bd1e 125 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
aaf7eda8
LP		 126 #gpio-cells = <2>;
127 gpio-controller;
128 gpio-ranges = <&pfc 0 96 32>;
129 #interrupt-cells = <2>;
130 interrupt-controller;
131 };
132
133 gpio4: gpio@ffc44000 {
9b43ba66 134 compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
aaf7eda8 135 reg = <0xffc44000 0x2c>;
0c34bd1e 136 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
aaf7eda8
LP		 137 #gpio-cells = <2>;
138 gpio-controller;
139 gpio-ranges = <&pfc 0 128 27>;
140 #interrupt-cells = <2>;
141 interrupt-controller;
142 };
143
b3ed0498 144 pfc: pin-controller@fffc0000 {
0697ccc0 145 compatible = "renesas,pfc-r8a7778";
80d01fee 146 reg = <0xfffc0000 0x118>;
0697ccc0 147 };
3acb51b9
KM		 148
149 i2c0: i2c@ffc70000 {
150 #address-cells = <1>;
151 #size-cells = <0>;
eb6f2adf 152 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
3acb51b9 153 reg = <0xffc70000 0x1000>;
0c34bd1e 154 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
66462be7 155 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
a670f366 156 power-domains = <&cpg_clocks>;
3acb51b9
KM		 157 status = "disabled";
158 };
159
160 i2c1: i2c@ffc71000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
eb6f2adf 163 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
3acb51b9 164 reg = <0xffc71000 0x1000>;
0c34bd1e 165 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
66462be7 166 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
a670f366 167 power-domains = <&cpg_clocks>;
3acb51b9
KM		 168 status = "disabled";
169 };
170
171 i2c2: i2c@ffc72000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
eb6f2adf 174 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
3acb51b9 175 reg = <0xffc72000 0x1000>;
0c34bd1e 176 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
66462be7 177 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
a670f366 178 power-domains = <&cpg_clocks>;
3acb51b9
KM		 179 status = "disabled";
180 };
181
182 i2c3: i2c@ffc73000 {
183 #address-cells = <1>;
184 #size-cells = <0>;
eb6f2adf 185 compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
3acb51b9 186 reg = <0xffc73000 0x1000>;
0c34bd1e 187 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
66462be7 188 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
a670f366 189 power-domains = <&cpg_clocks>;
3acb51b9
KM		 190 status = "disabled";
191 };
f7b90175 192
2109b5a2 193 tmu0: timer@ffd80000 {
45b439c1 194 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
2109b5a2 195 reg = <0xffd80000 0x30>;
0c34bd1e
SH		 196 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
66462be7
UH		 199 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
200 clock-names = "fck";
a670f366 201 power-domains = <&cpg_clocks>;
2109b5a2
SH		 202
203 #renesas,channels = <3>;
204
205 status = "disabled";
206 };
207
208 tmu1: timer@ffd81000 {
45b439c1 209 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
2109b5a2 210 reg = <0xffd81000 0x30>;
0c34bd1e
SH		 211 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
66462be7
UH		 214 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
215 clock-names = "fck";
a670f366 216 power-domains = <&cpg_clocks>;
2109b5a2
SH		 217
218 #renesas,channels = <3>;
219
220 status = "disabled";
221 };
222
223 tmu2: timer@ffd82000 {
45b439c1 224 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
2109b5a2 225 reg = <0xffd82000 0x30>;
0c34bd1e
SH		 226 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
66462be7
UH		 229 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
230 clock-names = "fck";
a670f366 231 power-domains = <&cpg_clocks>;
2109b5a2
SH		 232
233 #renesas,channels = <3>;
234
235 status = "disabled";
236 };
237
39a96792 238 rcar_sound: sound@ffd90000 {
2020dddd
KM		 239 /*
240 * #sound-dai-cells is required
241 *
242 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
243 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
244 */
39a96792
UH		 245 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
246 reg = <0xffd90000 0x1000>, /* SRU */
23640ff2 247 <0xffd91000 0x240>, /* SSI */
39a96792
UH		 248 <0xfffe0000 0x24>; /* ADG */
249 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
250 <&mstp3_clks R8A7778_CLK_SSI7>,
251 <&mstp3_clks R8A7778_CLK_SSI6>,
252 <&mstp3_clks R8A7778_CLK_SSI5>,
253 <&mstp3_clks R8A7778_CLK_SSI4>,
254 <&mstp0_clks R8A7778_CLK_SSI3>,
255 <&mstp0_clks R8A7778_CLK_SSI2>,
256 <&mstp0_clks R8A7778_CLK_SSI1>,
257 <&mstp0_clks R8A7778_CLK_SSI0>,
258 <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
259 <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
260 <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
261 <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
262 <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
263 <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
264 <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
265 <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
266 <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
267 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
268 <&cpg_clocks R8A7778_CLK_S1>;
269 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
270 "ssi.3", "ssi.2", "ssi.1", "ssi.0",
271 "src.8", "src.7", "src.6", "src.5", "src.4",
272 "src.3", "src.2", "src.1", "src.0",
273 "clk_a", "clk_b", "clk_c", "clk_i";
274
275 status = "disabled";
276
277 rcar_sound,src {
51f20c93
GU		 278 src3: src-3 { };
279 src4: src-4 { };
280 src5: src-5 { };
281 src6: src-6 { };
282 src7: src-7 { };
283 src8: src-8 { };
284 src9: src-9 { };
39a96792
UH		 285 };
286
287 rcar_sound,ssi {
51f20c93
GU		 288 ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
289 ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
290 ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
291 ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
292 ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
293 ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
294 ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
39a96792
UH		 295 };
296 };
297
9930dc8e 298 scif0: serial@ffe40000 {
720e9096
GU		 299 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
300 "renesas,scif";
9930dc8e 301 reg = <0xffe40000 0x100>;
0c34bd1e 302 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
5fb544da
GU		 303 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
304 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
305 clock-names = "fck", "brg_int", "scif_clk";
a670f366 306 power-domains = <&cpg_clocks>;
9930dc8e
SH		 307 status = "disabled";
308 };
309
310 scif1: serial@ffe41000 {
720e9096
GU		 311 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
312 "renesas,scif";
9930dc8e 313 reg = <0xffe41000 0x100>;
0c34bd1e 314 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
5fb544da
GU		 315 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
316 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
317 clock-names = "fck", "brg_int", "scif_clk";
a670f366 318 power-domains = <&cpg_clocks>;
9930dc8e
SH		 319 status = "disabled";
320 };
321
322 scif2: serial@ffe42000 {
720e9096
GU		 323 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
324 "renesas,scif";
9930dc8e 325 reg = <0xffe42000 0x100>;
0c34bd1e 326 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
5fb544da
GU		 327 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
328 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
329 clock-names = "fck", "brg_int", "scif_clk";
a670f366 330 power-domains = <&cpg_clocks>;
9930dc8e
SH		 331 status = "disabled";
332 };
333
334 scif3: serial@ffe43000 {
720e9096
GU		 335 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
336 "renesas,scif";
9930dc8e 337 reg = <0xffe43000 0x100>;
0c34bd1e 338 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
5fb544da
GU		 339 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
340 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
341 clock-names = "fck", "brg_int", "scif_clk";
a670f366 342 power-domains = <&cpg_clocks>;
9930dc8e
SH		 343 status = "disabled";
344 };
345
346 scif4: serial@ffe44000 {
720e9096
GU		 347 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
348 "renesas,scif";
9930dc8e 349 reg = <0xffe44000 0x100>;
0c34bd1e 350 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
5fb544da
GU		 351 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
352 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
353 clock-names = "fck", "brg_int", "scif_clk";
a670f366 354 power-domains = <&cpg_clocks>;
9930dc8e
SH		 355 status = "disabled";
356 };
357
358 scif5: serial@ffe45000 {
720e9096
GU		 359 compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
360 "renesas,scif";
9930dc8e 361 reg = <0xffe45000 0x100>;
0c34bd1e 362 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
5fb544da
GU		 363 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
364 <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
365 clock-names = "fck", "brg_int", "scif_clk";
a670f366 366 power-domains = <&cpg_clocks>;
9930dc8e
SH		 367 status = "disabled";
368 };
369
adbb78e1
UH		 370 hscif0: serial@ffe48000 {
371 compatible = "renesas,hscif-r8a7778",
372 "renesas,rcar-gen1-hscif", "renesas,hscif";
373 reg = <0xffe48000 96>;
374 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,
376 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
377 clock-names = "fck", "brg_int", "scif_clk";
378 power-domains = <&cpg_clocks>;
379 status = "disabled";
380 };
381
382 hscif1: serial@ffe49000 {
383 compatible = "renesas,hscif-r8a7778",
384 "renesas,rcar-gen1-hscif", "renesas,hscif";
385 reg = <0xffe49000 96>;
386 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,
388 <&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
389 clock-names = "fck", "brg_int", "scif_clk";
390 power-domains = <&cpg_clocks>;
391 status = "disabled";
392 };
393
14e1d914 394 mmcif: mmc@ffe4e000 {
f9be04fe 395 compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
f7b90175 396 reg = <0xffe4e000 0x100>;
0c34bd1e 397 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
66462be7 398 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
a670f366 399 power-domains = <&cpg_clocks>;
f7b90175
KM		 400 status = "disabled";
401 };
04cbd889 402
14e1d914 403 sdhi0: sd@ffe4c000 {
bce90b30
SH		 404 compatible = "renesas,sdhi-r8a7778",
405 "renesas,rcar-gen1-sdhi";
04cbd889 406 reg = <0xffe4c000 0x100>;
0c34bd1e 407 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
66462be7 408 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
a670f366 409 power-domains = <&cpg_clocks>;
04cbd889
KM		 410 status = "disabled";
411 };
412
14e1d914 413 sdhi1: sd@ffe4d000 {
bce90b30
SH		 414 compatible = "renesas,sdhi-r8a7778",
415 "renesas,rcar-gen1-sdhi";
04cbd889 416 reg = <0xffe4d000 0x100>;
0c34bd1e 417 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
66462be7 418 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
a670f366 419 power-domains = <&cpg_clocks>;
04cbd889
KM		 420 status = "disabled";
421 };
422
14e1d914 423 sdhi2: sd@ffe4f000 {
bce90b30
SH		 424 compatible = "renesas,sdhi-r8a7778",
425 "renesas,rcar-gen1-sdhi";
04cbd889 426 reg = <0xffe4f000 0x100>;
0c34bd1e 427 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
66462be7 428 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
a670f366 429 power-domains = <&cpg_clocks>;
04cbd889
KM		 430 status = "disabled";
431 };
ae4273ec 432
a50da085 433 hspi0: spi@fffc7000 {
a34c50d5 434 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
a50da085 435 reg = <0xfffc7000 0x18>;
0c34bd1e 436 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
66462be7 437 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
a670f366 438 power-domains = <&cpg_clocks>;
a34c50d5
GU		 439 #address-cells = <1>;
440 #size-cells = <0>;
a50da085
KM		 441 status = "disabled";
442 };
443
444 hspi1: spi@fffc8000 {
a34c50d5 445 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
a50da085 446 reg = <0xfffc8000 0x18>;
0c34bd1e 447 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
66462be7 448 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
a670f366 449 power-domains = <&cpg_clocks>;
a34c50d5
GU		 450 #address-cells = <1>;
451 #size-cells = <0>;
a50da085
KM		 452 status = "disabled";
453 };
454
455 hspi2: spi@fffc6000 {
a34c50d5 456 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
a50da085 457 reg = <0xfffc6000 0x18>;
0c34bd1e 458 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
66462be7 459 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
a670f366 460 power-domains = <&cpg_clocks>;
a34c50d5
GU		 461 #address-cells = <1>;
462 #size-cells = <0>;
a50da085
KM		 463 status = "disabled";
464 };
93aa970d
UH		 465
466 clocks {
467 #address-cells = <1>;
468 #size-cells = <1>;
469 ranges;
470
471 /* External input clock */
452fc899 472 extal_clk: extal {
93aa970d
UH		 473 compatible = "fixed-clock";
474 #clock-cells = <0>;
475 clock-frequency = <0>;
93aa970d
UH		 476 };
477
5fb544da
GU		 478 /* External SCIF clock */
479 scif_clk: scif {
480 compatible = "fixed-clock";
481 #clock-cells = <0>;
482 /* This value must be overridden by the board. */
483 clock-frequency = <0>;
5fb544da
GU		 484 };
485
93aa970d
UH		 486 /* Special CPG clocks */
487 cpg_clocks: cpg_clocks@ffc80000 {
488 compatible = "renesas,r8a7778-cpg-clocks";
489 reg = <0xffc80000 0x80>;
490 #clock-cells = <1>;
491 clocks = <&extal_clk>;
492 clock-output-names = "plla", "pllb", "b",
493 "out", "p", "s", "s1";
a670f366 494 #power-domain-cells = <0>;
93aa970d
UH		 495 };
496
497 /* Audio clocks; frequencies are set by boards if applicable. */
498 audio_clk_a: audio_clk_a {
499 compatible = "fixed-clock";
500 #clock-cells = <0>;
93aa970d
UH		 501 };
502 audio_clk_b: audio_clk_b {
503 compatible = "fixed-clock";
504 #clock-cells = <0>;
93aa970d
UH		 505 };
506 audio_clk_c: audio_clk_c {
507 compatible = "fixed-clock";
508 #clock-cells = <0>;
93aa970d
UH		 509 };
510
511 /* Fixed ratio clocks */
452fc899 512 g_clk: g {
93aa970d
UH		 513 compatible = "fixed-factor-clock";
514 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
515 #clock-cells = <0>;
516 clock-div = <12>;
517 clock-mult = <1>;
93aa970d 518 };
452fc899 519 i_clk: i {
93aa970d
UH		 520 compatible = "fixed-factor-clock";
521 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
522 #clock-cells = <0>;
523 clock-div = <1>;
524 clock-mult = <1>;
93aa970d 525 };
452fc899 526 s3_clk: s3 {
93aa970d
UH		 527 compatible = "fixed-factor-clock";
528 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
529 #clock-cells = <0>;
530 clock-div = <4>;
531 clock-mult = <1>;
93aa970d 532 };
452fc899 533 s4_clk: s4 {
93aa970d
UH		 534 compatible = "fixed-factor-clock";
535 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
536 #clock-cells = <0>;
537 clock-div = <8>;
538 clock-mult = <1>;
93aa970d 539 };
452fc899 540 z_clk: z {
93aa970d
UH		 541 compatible = "fixed-factor-clock";
542 clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
543 #clock-cells = <0>;
544 clock-div = <1>;
545 clock-mult = <1>;
93aa970d
UH		 546 };
547
548 /* Gate clocks */
549 mstp0_clks: mstp0_clks@ffc80030 {
550 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
551 reg = <0xffc80030 4>;
552 clocks = <&cpg_clocks R8A7778_CLK_P>,
553 <&cpg_clocks R8A7778_CLK_P>,
554 <&cpg_clocks R8A7778_CLK_P>,
555 <&cpg_clocks R8A7778_CLK_P>,
556 <&cpg_clocks R8A7778_CLK_P>,
557 <&cpg_clocks R8A7778_CLK_P>,
558 <&cpg_clocks R8A7778_CLK_P>,
559 <&cpg_clocks R8A7778_CLK_P>,
560 <&cpg_clocks R8A7778_CLK_P>,
561 <&cpg_clocks R8A7778_CLK_P>,
adbb78e1
UH		 562 <&cpg_clocks R8A7778_CLK_S>,
563 <&cpg_clocks R8A7778_CLK_S>,
93aa970d
UH		 564 <&cpg_clocks R8A7778_CLK_P>,
565 <&cpg_clocks R8A7778_CLK_P>,
566 <&cpg_clocks R8A7778_CLK_P>,
567 <&cpg_clocks R8A7778_CLK_P>,
568 <&cpg_clocks R8A7778_CLK_P>,
569 <&cpg_clocks R8A7778_CLK_P>,
570 <&cpg_clocks R8A7778_CLK_P>,
571 <&cpg_clocks R8A7778_CLK_P>,
572 <&cpg_clocks R8A7778_CLK_S>;
573 #clock-cells = <1>;
574 clock-indices = <
575 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
576 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
577 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
578 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
579 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
adbb78e1 580 R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1
93aa970d
UH		 581 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
582 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
583 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
584 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
585 R8A7778_CLK_HSPI
586 >;
587 clock-output-names =
588 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
589 "scif1", "scif2", "scif3", "scif4", "scif5",
adbb78e1 590 "hscif0", "hscif1",
93aa970d
UH		 591 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
592 "ssi2", "ssi3", "sru", "hspi";
593 };
594 mstp1_clks: mstp1_clks@ffc80034 {
595 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
596 reg = <0xffc80034 4>, <0xffc80044 4>;
597 clocks = <&cpg_clocks R8A7778_CLK_P>,
598 <&cpg_clocks R8A7778_CLK_S>,
599 <&cpg_clocks R8A7778_CLK_S>,
600 <&cpg_clocks R8A7778_CLK_P>;
601 #clock-cells = <1>;
602 clock-indices = <
603 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
604 R8A7778_CLK_VIN1 R8A7778_CLK_USB
605 >;
606 clock-output-names =
607 "ether", "vin0", "vin1", "usb";
608 };
609 mstp3_clks: mstp3_clks@ffc8003c {
610 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
611 reg = <0xffc8003c 4>;
612 clocks = <&s4_clk>,
613 <&cpg_clocks R8A7778_CLK_P>,
614 <&cpg_clocks R8A7778_CLK_P>,
615 <&cpg_clocks R8A7778_CLK_P>,
616 <&cpg_clocks R8A7778_CLK_P>,
617 <&cpg_clocks R8A7778_CLK_P>,
618 <&cpg_clocks R8A7778_CLK_P>,
619 <&cpg_clocks R8A7778_CLK_P>,
620 <&cpg_clocks R8A7778_CLK_P>;
621 #clock-cells = <1>;
622 clock-indices = <
623 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
624 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
625 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
626 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
627 R8A7778_CLK_SSI8
628 >;
629 clock-output-names =
630 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
631 "ssi5", "ssi6", "ssi7", "ssi8";
632 };
633 mstp5_clks: mstp5_clks@ffc80054 {
634 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
635 reg = <0xffc80054 4>;
636 clocks = <&cpg_clocks R8A7778_CLK_P>,
637 <&cpg_clocks R8A7778_CLK_P>,
638 <&cpg_clocks R8A7778_CLK_P>,
639 <&cpg_clocks R8A7778_CLK_P>,
640 <&cpg_clocks R8A7778_CLK_P>,
641 <&cpg_clocks R8A7778_CLK_P>,
642 <&cpg_clocks R8A7778_CLK_P>,
643 <&cpg_clocks R8A7778_CLK_P>,
644 <&cpg_clocks R8A7778_CLK_P>;
645 #clock-cells = <1>;
646 clock-indices = <
647 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
648 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
649 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
650 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
651 R8A7778_CLK_SRU_SRC8
652 >;
653 clock-output-names =
654 "sru-src0", "sru-src1", "sru-src2",
655 "sru-src3", "sru-src4", "sru-src5",
656 "sru-src6", "sru-src7", "sru-src8";
657 };
658 };
e2eb35e0
GU		 659
660 rst: reset-controller@ffcc0000 {
661 compatible = "renesas,r8a7778-reset-wdt";
662 reg = <0xffcc0000 0x40>;
663 };
ccb7cc74 664};
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