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Commit | Line | Data |
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66314223 DN |
1 | /* |
2 | * Copyright (C) 2012 Altera <www.altera.com> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
16fb4f8b | 18 | #include <dt-bindings/reset/altr,rst-mgr.h> |
66314223 DN |
19 | |
20 | / { | |
21 | #address-cells = <1>; | |
22 | #size-cells = <1>; | |
23 | ||
24 | aliases { | |
25 | ethernet0 = &gmac0; | |
3d954cf1 | 26 | ethernet1 = &gmac1; |
66314223 DN |
27 | serial0 = &uart0; |
28 | serial1 = &uart1; | |
c2ad2844 DN |
29 | timer0 = &timer0; |
30 | timer1 = &timer1; | |
31 | timer2 = &timer2; | |
32 | timer3 = &timer3; | |
66314223 DN |
33 | }; |
34 | ||
35 | cpus { | |
36 | #address-cells = <1>; | |
37 | #size-cells = <0>; | |
ebbce1bb | 38 | enable-method = "altr,socfpga-smp"; |
66314223 | 39 | |
e3e6dba1 | 40 | cpu0: cpu@0 { |
66314223 DN |
41 | compatible = "arm,cortex-a9"; |
42 | device_type = "cpu"; | |
43 | reg = <0>; | |
44 | next-level-cache = <&L2>; | |
45 | }; | |
e3e6dba1 | 46 | cpu1: cpu@1 { |
66314223 DN |
47 | compatible = "arm,cortex-a9"; |
48 | device_type = "cpu"; | |
49 | reg = <1>; | |
50 | next-level-cache = <&L2>; | |
51 | }; | |
52 | }; | |
53 | ||
34869353 FV |
54 | pmu: pmu@ff111000 { |
55 | compatible = "arm,cortex-a9-pmu"; | |
56 | interrupt-parent = <&intc>; | |
57 | interrupts = <0 176 4>, <0 177 4>; | |
58 | interrupt-affinity = <&cpu0>, <&cpu1>; | |
59 | reg = <0xff111000 0x1000>, | |
60 | <0xff113000 0x1000>; | |
61 | }; | |
62 | ||
66314223 DN |
63 | intc: intc@fffed000 { |
64 | compatible = "arm,cortex-a9-gic"; | |
65 | #interrupt-cells = <3>; | |
66 | interrupt-controller; | |
67 | reg = <0xfffed000 0x1000>, | |
68 | <0xfffec100 0x100>; | |
69 | }; | |
70 | ||
71 | soc { | |
72 | #address-cells = <1>; | |
73 | #size-cells = <1>; | |
74 | compatible = "simple-bus"; | |
75 | device_type = "soc"; | |
76 | interrupt-parent = <&intc>; | |
77 | ranges; | |
78 | ||
79 | amba { | |
2ef7d5f3 | 80 | compatible = "simple-bus"; |
66314223 DN |
81 | #address-cells = <1>; |
82 | #size-cells = <1>; | |
83 | ranges; | |
84 | ||
85 | pdma: pdma@ffe01000 { | |
86 | compatible = "arm,pl330", "arm,primecell"; | |
87 | reg = <0xffe01000 0x1000>; | |
18d56199 ST |
88 | interrupts = <0 104 4>, |
89 | <0 105 4>, | |
90 | <0 106 4>, | |
91 | <0 107 4>, | |
92 | <0 108 4>, | |
93 | <0 109 4>, | |
94 | <0 110 4>, | |
95 | <0 111 4>; | |
0d8abbfd PV |
96 | #dma-cells = <1>; |
97 | #dma-channels = <8>; | |
98 | #dma-requests = <32>; | |
672ef909 ST |
99 | clocks = <&l4_main_clk>; |
100 | clock-names = "apb_pclk"; | |
66314223 DN |
101 | }; |
102 | }; | |
103 | ||
7c8e5afd AT |
104 | base_fpga_region { |
105 | compatible = "fpga-region"; | |
106 | fpga-mgr = <&fpgamgr0>; | |
107 | ||
108 | #address-cells = <0x1>; | |
109 | #size-cells = <0x1>; | |
110 | }; | |
111 | ||
36fe3f54 ST |
112 | can0: can@ffc00000 { |
113 | compatible = "bosch,d_can"; | |
114 | reg = <0xffc00000 0x1000>; | |
115 | interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; | |
116 | clocks = <&can0_clk>; | |
117 | status = "disabled"; | |
118 | }; | |
119 | ||
120 | can1: can@ffc01000 { | |
121 | compatible = "bosch,d_can"; | |
122 | reg = <0xffc01000 0x1000>; | |
123 | interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; | |
124 | clocks = <&can1_clk>; | |
125 | status = "disabled"; | |
126 | }; | |
127 | ||
042000b0 DN |
128 | clkmgr@ffd04000 { |
129 | compatible = "altr,clk-mgr"; | |
130 | reg = <0xffd04000 0x1000>; | |
131 | ||
132 | clocks { | |
133 | #address-cells = <1>; | |
134 | #size-cells = <0>; | |
135 | ||
f1ce1a99 DN |
136 | osc1: osc1 { |
137 | #clock-cells = <0>; | |
138 | compatible = "fixed-clock"; | |
139 | }; | |
140 | ||
141 | osc2: osc2 { | |
042000b0 DN |
142 | #clock-cells = <0>; |
143 | compatible = "fixed-clock"; | |
144 | }; | |
145 | ||
a92b83af DN |
146 | f2s_periph_ref_clk: f2s_periph_ref_clk { |
147 | #clock-cells = <0>; | |
148 | compatible = "fixed-clock"; | |
f1ce1a99 DN |
149 | }; |
150 | ||
151 | f2s_sdram_ref_clk: f2s_sdram_ref_clk { | |
152 | #clock-cells = <0>; | |
153 | compatible = "fixed-clock"; | |
a92b83af DN |
154 | }; |
155 | ||
9f24e816 | 156 | main_pll: main_pll@40 { |
042000b0 DN |
157 | #address-cells = <1>; |
158 | #size-cells = <0>; | |
159 | #clock-cells = <0>; | |
160 | compatible = "altr,socfpga-pll-clock"; | |
f1ce1a99 | 161 | clocks = <&osc1>; |
042000b0 DN |
162 | reg = <0x40>; |
163 | ||
9f24e816 | 164 | mpuclk: mpuclk@48 { |
042000b0 DN |
165 | #clock-cells = <0>; |
166 | compatible = "altr,socfpga-perip-clk"; | |
167 | clocks = <&main_pll>; | |
8cb289ed | 168 | div-reg = <0xe0 0 9>; |
042000b0 DN |
169 | reg = <0x48>; |
170 | }; | |
171 | ||
9f24e816 | 172 | mainclk: mainclk@4c { |
042000b0 DN |
173 | #clock-cells = <0>; |
174 | compatible = "altr,socfpga-perip-clk"; | |
175 | clocks = <&main_pll>; | |
8cb289ed | 176 | div-reg = <0xe4 0 9>; |
042000b0 DN |
177 | reg = <0x4C>; |
178 | }; | |
179 | ||
9f24e816 | 180 | dbg_base_clk: dbg_base_clk@50 { |
042000b0 DN |
181 | #clock-cells = <0>; |
182 | compatible = "altr,socfpga-perip-clk"; | |
2e4c7588 | 183 | clocks = <&main_pll>, <&osc1>; |
8cb289ed | 184 | div-reg = <0xe8 0 9>; |
042000b0 DN |
185 | reg = <0x50>; |
186 | }; | |
187 | ||
9f24e816 | 188 | main_qspi_clk: main_qspi_clk@54 { |
042000b0 DN |
189 | #clock-cells = <0>; |
190 | compatible = "altr,socfpga-perip-clk"; | |
191 | clocks = <&main_pll>; | |
192 | reg = <0x54>; | |
193 | }; | |
194 | ||
9f24e816 | 195 | main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 { |
042000b0 DN |
196 | #clock-cells = <0>; |
197 | compatible = "altr,socfpga-perip-clk"; | |
198 | clocks = <&main_pll>; | |
199 | reg = <0x58>; | |
200 | }; | |
201 | ||
9f24e816 | 202 | cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c { |
042000b0 DN |
203 | #clock-cells = <0>; |
204 | compatible = "altr,socfpga-perip-clk"; | |
205 | clocks = <&main_pll>; | |
206 | reg = <0x5C>; | |
207 | }; | |
208 | }; | |
209 | ||
9f24e816 | 210 | periph_pll: periph_pll@80 { |
042000b0 DN |
211 | #address-cells = <1>; |
212 | #size-cells = <0>; | |
213 | #clock-cells = <0>; | |
214 | compatible = "altr,socfpga-pll-clock"; | |
f1ce1a99 | 215 | clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; |
042000b0 DN |
216 | reg = <0x80>; |
217 | ||
9f24e816 | 218 | emac0_clk: emac0_clk@88 { |
042000b0 DN |
219 | #clock-cells = <0>; |
220 | compatible = "altr,socfpga-perip-clk"; | |
221 | clocks = <&periph_pll>; | |
222 | reg = <0x88>; | |
223 | }; | |
224 | ||
9f24e816 | 225 | emac1_clk: emac1_clk@8c { |
042000b0 DN |
226 | #clock-cells = <0>; |
227 | compatible = "altr,socfpga-perip-clk"; | |
228 | clocks = <&periph_pll>; | |
229 | reg = <0x8C>; | |
230 | }; | |
231 | ||
9f24e816 | 232 | per_qspi_clk: per_qsi_clk@90 { |
042000b0 DN |
233 | #clock-cells = <0>; |
234 | compatible = "altr,socfpga-perip-clk"; | |
235 | clocks = <&periph_pll>; | |
236 | reg = <0x90>; | |
237 | }; | |
238 | ||
9f24e816 | 239 | per_nand_mmc_clk: per_nand_mmc_clk@94 { |
042000b0 DN |
240 | #clock-cells = <0>; |
241 | compatible = "altr,socfpga-perip-clk"; | |
242 | clocks = <&periph_pll>; | |
243 | reg = <0x94>; | |
244 | }; | |
245 | ||
9f24e816 | 246 | per_base_clk: per_base_clk@98 { |
042000b0 DN |
247 | #clock-cells = <0>; |
248 | compatible = "altr,socfpga-perip-clk"; | |
249 | clocks = <&periph_pll>; | |
250 | reg = <0x98>; | |
251 | }; | |
252 | ||
9f24e816 | 253 | h2f_usr1_clk: h2f_usr1_clk@9c { |
042000b0 DN |
254 | #clock-cells = <0>; |
255 | compatible = "altr,socfpga-perip-clk"; | |
256 | clocks = <&periph_pll>; | |
257 | reg = <0x9C>; | |
258 | }; | |
259 | }; | |
260 | ||
9f24e816 | 261 | sdram_pll: sdram_pll@c0 { |
042000b0 DN |
262 | #address-cells = <1>; |
263 | #size-cells = <0>; | |
264 | #clock-cells = <0>; | |
265 | compatible = "altr,socfpga-pll-clock"; | |
f1ce1a99 | 266 | clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; |
042000b0 DN |
267 | reg = <0xC0>; |
268 | ||
9f24e816 | 269 | ddr_dqs_clk: ddr_dqs_clk@c8 { |
042000b0 DN |
270 | #clock-cells = <0>; |
271 | compatible = "altr,socfpga-perip-clk"; | |
272 | clocks = <&sdram_pll>; | |
273 | reg = <0xC8>; | |
274 | }; | |
275 | ||
9f24e816 | 276 | ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc { |
042000b0 DN |
277 | #clock-cells = <0>; |
278 | compatible = "altr,socfpga-perip-clk"; | |
279 | clocks = <&sdram_pll>; | |
280 | reg = <0xCC>; | |
281 | }; | |
282 | ||
9f24e816 | 283 | ddr_dq_clk: ddr_dq_clk@d0 { |
042000b0 DN |
284 | #clock-cells = <0>; |
285 | compatible = "altr,socfpga-perip-clk"; | |
286 | clocks = <&sdram_pll>; | |
287 | reg = <0xD0>; | |
288 | }; | |
289 | ||
9f24e816 | 290 | h2f_usr2_clk: h2f_usr2_clk@d4 { |
042000b0 DN |
291 | #clock-cells = <0>; |
292 | compatible = "altr,socfpga-perip-clk"; | |
293 | clocks = <&sdram_pll>; | |
294 | reg = <0xD4>; | |
295 | }; | |
296 | }; | |
a92b83af | 297 | |
7857d560 ST |
298 | mpu_periph_clk: mpu_periph_clk { |
299 | #clock-cells = <0>; | |
a5c6e87a | 300 | compatible = "altr,socfpga-perip-clk"; |
7857d560 ST |
301 | clocks = <&mpuclk>; |
302 | fixed-divider = <4>; | |
a92b83af DN |
303 | }; |
304 | ||
7857d560 ST |
305 | mpu_l2_ram_clk: mpu_l2_ram_clk { |
306 | #clock-cells = <0>; | |
a5c6e87a | 307 | compatible = "altr,socfpga-perip-clk"; |
7857d560 ST |
308 | clocks = <&mpuclk>; |
309 | fixed-divider = <2>; | |
a92b83af DN |
310 | }; |
311 | ||
7857d560 ST |
312 | l4_main_clk: l4_main_clk { |
313 | #clock-cells = <0>; | |
314 | compatible = "altr,socfpga-gate-clk"; | |
315 | clocks = <&mainclk>; | |
316 | clk-gate = <0x60 0>; | |
a92b83af DN |
317 | }; |
318 | ||
7857d560 ST |
319 | l3_main_clk: l3_main_clk { |
320 | #clock-cells = <0>; | |
a5c6e87a | 321 | compatible = "altr,socfpga-perip-clk"; |
7857d560 | 322 | clocks = <&mainclk>; |
a5c6e87a | 323 | fixed-divider = <1>; |
a92b83af DN |
324 | }; |
325 | ||
7857d560 ST |
326 | l3_mp_clk: l3_mp_clk { |
327 | #clock-cells = <0>; | |
328 | compatible = "altr,socfpga-gate-clk"; | |
329 | clocks = <&mainclk>; | |
330 | div-reg = <0x64 0 2>; | |
331 | clk-gate = <0x60 1>; | |
a92b83af DN |
332 | }; |
333 | ||
7857d560 ST |
334 | l3_sp_clk: l3_sp_clk { |
335 | #clock-cells = <0>; | |
336 | compatible = "altr,socfpga-gate-clk"; | |
c5dab6e2 | 337 | clocks = <&l3_mp_clk>; |
7857d560 ST |
338 | div-reg = <0x64 2 2>; |
339 | }; | |
a92b83af | 340 | |
7857d560 ST |
341 | l4_mp_clk: l4_mp_clk { |
342 | #clock-cells = <0>; | |
343 | compatible = "altr,socfpga-gate-clk"; | |
344 | clocks = <&mainclk>, <&per_base_clk>; | |
345 | div-reg = <0x64 4 3>; | |
346 | clk-gate = <0x60 2>; | |
a92b83af DN |
347 | }; |
348 | ||
7857d560 ST |
349 | l4_sp_clk: l4_sp_clk { |
350 | #clock-cells = <0>; | |
351 | compatible = "altr,socfpga-gate-clk"; | |
352 | clocks = <&mainclk>, <&per_base_clk>; | |
353 | div-reg = <0x64 7 3>; | |
354 | clk-gate = <0x60 3>; | |
a92b83af DN |
355 | }; |
356 | ||
7857d560 ST |
357 | dbg_at_clk: dbg_at_clk { |
358 | #clock-cells = <0>; | |
359 | compatible = "altr,socfpga-gate-clk"; | |
360 | clocks = <&dbg_base_clk>; | |
361 | div-reg = <0x68 0 2>; | |
362 | clk-gate = <0x60 4>; | |
a92b83af DN |
363 | }; |
364 | ||
7857d560 ST |
365 | dbg_clk: dbg_clk { |
366 | #clock-cells = <0>; | |
367 | compatible = "altr,socfpga-gate-clk"; | |
c5dab6e2 | 368 | clocks = <&dbg_at_clk>; |
7857d560 ST |
369 | div-reg = <0x68 2 2>; |
370 | clk-gate = <0x60 5>; | |
a92b83af DN |
371 | }; |
372 | ||
7857d560 ST |
373 | dbg_trace_clk: dbg_trace_clk { |
374 | #clock-cells = <0>; | |
375 | compatible = "altr,socfpga-gate-clk"; | |
376 | clocks = <&dbg_base_clk>; | |
377 | div-reg = <0x6C 0 3>; | |
378 | clk-gate = <0x60 6>; | |
a92b83af DN |
379 | }; |
380 | ||
7857d560 ST |
381 | dbg_timer_clk: dbg_timer_clk { |
382 | #clock-cells = <0>; | |
383 | compatible = "altr,socfpga-gate-clk"; | |
384 | clocks = <&dbg_base_clk>; | |
385 | clk-gate = <0x60 7>; | |
a92b83af DN |
386 | }; |
387 | ||
7857d560 ST |
388 | cfg_clk: cfg_clk { |
389 | #clock-cells = <0>; | |
390 | compatible = "altr,socfpga-gate-clk"; | |
01ed80b0 | 391 | clocks = <&cfg_h2f_usr0_clk>; |
7857d560 | 392 | clk-gate = <0x60 8>; |
a92b83af DN |
393 | }; |
394 | ||
01ed80b0 | 395 | h2f_user0_clk: h2f_user0_clk { |
7857d560 ST |
396 | #clock-cells = <0>; |
397 | compatible = "altr,socfpga-gate-clk"; | |
01ed80b0 | 398 | clocks = <&cfg_h2f_usr0_clk>; |
7857d560 | 399 | clk-gate = <0x60 9>; |
a92b83af DN |
400 | }; |
401 | ||
7857d560 ST |
402 | emac_0_clk: emac_0_clk { |
403 | #clock-cells = <0>; | |
404 | compatible = "altr,socfpga-gate-clk"; | |
405 | clocks = <&emac0_clk>; | |
406 | clk-gate = <0xa0 0>; | |
a92b83af DN |
407 | }; |
408 | ||
7857d560 ST |
409 | emac_1_clk: emac_1_clk { |
410 | #clock-cells = <0>; | |
411 | compatible = "altr,socfpga-gate-clk"; | |
412 | clocks = <&emac1_clk>; | |
413 | clk-gate = <0xa0 1>; | |
a92b83af DN |
414 | }; |
415 | ||
7857d560 ST |
416 | usb_mp_clk: usb_mp_clk { |
417 | #clock-cells = <0>; | |
418 | compatible = "altr,socfpga-gate-clk"; | |
419 | clocks = <&per_base_clk>; | |
420 | clk-gate = <0xa0 2>; | |
421 | div-reg = <0xa4 0 3>; | |
a92b83af DN |
422 | }; |
423 | ||
7857d560 ST |
424 | spi_m_clk: spi_m_clk { |
425 | #clock-cells = <0>; | |
426 | compatible = "altr,socfpga-gate-clk"; | |
427 | clocks = <&per_base_clk>; | |
428 | clk-gate = <0xa0 3>; | |
429 | div-reg = <0xa4 3 3>; | |
a92b83af DN |
430 | }; |
431 | ||
7857d560 ST |
432 | can0_clk: can0_clk { |
433 | #clock-cells = <0>; | |
434 | compatible = "altr,socfpga-gate-clk"; | |
435 | clocks = <&per_base_clk>; | |
436 | clk-gate = <0xa0 4>; | |
437 | div-reg = <0xa4 6 3>; | |
a92b83af DN |
438 | }; |
439 | ||
7857d560 ST |
440 | can1_clk: can1_clk { |
441 | #clock-cells = <0>; | |
442 | compatible = "altr,socfpga-gate-clk"; | |
443 | clocks = <&per_base_clk>; | |
444 | clk-gate = <0xa0 5>; | |
445 | div-reg = <0xa4 9 3>; | |
a92b83af DN |
446 | }; |
447 | ||
7857d560 ST |
448 | gpio_db_clk: gpio_db_clk { |
449 | #clock-cells = <0>; | |
450 | compatible = "altr,socfpga-gate-clk"; | |
451 | clocks = <&per_base_clk>; | |
452 | clk-gate = <0xa0 6>; | |
453 | div-reg = <0xa8 0 24>; | |
a92b83af DN |
454 | }; |
455 | ||
01ed80b0 | 456 | h2f_user1_clk: h2f_user1_clk { |
7857d560 ST |
457 | #clock-cells = <0>; |
458 | compatible = "altr,socfpga-gate-clk"; | |
01ed80b0 | 459 | clocks = <&h2f_usr1_clk>; |
7857d560 | 460 | clk-gate = <0xa0 7>; |
a92b83af DN |
461 | }; |
462 | ||
7857d560 ST |
463 | sdmmc_clk: sdmmc_clk { |
464 | #clock-cells = <0>; | |
465 | compatible = "altr,socfpga-gate-clk"; | |
466 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | |
467 | clk-gate = <0xa0 8>; | |
044abbde | 468 | clk-phase = <0 135>; |
a92b83af DN |
469 | }; |
470 | ||
5459f9ab DN |
471 | sdmmc_clk_divided: sdmmc_clk_divided { |
472 | #clock-cells = <0>; | |
473 | compatible = "altr,socfpga-gate-clk"; | |
474 | clocks = <&sdmmc_clk>; | |
475 | clk-gate = <0xa0 8>; | |
476 | fixed-divider = <4>; | |
477 | }; | |
478 | ||
7857d560 ST |
479 | nand_x_clk: nand_x_clk { |
480 | #clock-cells = <0>; | |
481 | compatible = "altr,socfpga-gate-clk"; | |
482 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | |
483 | clk-gate = <0xa0 9>; | |
a92b83af DN |
484 | }; |
485 | ||
7857d560 ST |
486 | nand_clk: nand_clk { |
487 | #clock-cells = <0>; | |
488 | compatible = "altr,socfpga-gate-clk"; | |
489 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | |
490 | clk-gate = <0xa0 10>; | |
491 | fixed-divider = <4>; | |
a92b83af DN |
492 | }; |
493 | ||
7857d560 ST |
494 | qspi_clk: qspi_clk { |
495 | #clock-cells = <0>; | |
496 | compatible = "altr,socfpga-gate-clk"; | |
497 | clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; | |
498 | clk-gate = <0xa0 11>; | |
a92b83af | 499 | }; |
7db85dd0 MG |
500 | |
501 | ddr_dqs_clk_gate: ddr_dqs_clk_gate { | |
502 | #clock-cells = <0>; | |
503 | compatible = "altr,socfpga-gate-clk"; | |
504 | clocks = <&ddr_dqs_clk>; | |
505 | clk-gate = <0xd8 0>; | |
506 | }; | |
507 | ||
508 | ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate { | |
509 | #clock-cells = <0>; | |
510 | compatible = "altr,socfpga-gate-clk"; | |
511 | clocks = <&ddr_2x_dqs_clk>; | |
512 | clk-gate = <0xd8 1>; | |
513 | }; | |
514 | ||
515 | ddr_dq_clk_gate: ddr_dq_clk_gate { | |
516 | #clock-cells = <0>; | |
517 | compatible = "altr,socfpga-gate-clk"; | |
518 | clocks = <&ddr_dq_clk>; | |
519 | clk-gate = <0xd8 2>; | |
520 | }; | |
521 | ||
522 | h2f_user2_clk: h2f_user2_clk { | |
523 | #clock-cells = <0>; | |
524 | compatible = "altr,socfpga-gate-clk"; | |
525 | clocks = <&h2f_usr2_clk>; | |
526 | clk-gate = <0xd8 3>; | |
527 | }; | |
528 | ||
042000b0 | 529 | }; |
7db85dd0 | 530 | }; |
042000b0 | 531 | |
7c8e5afd AT |
532 | fpga_bridge0: fpga_bridge@ff400000 { |
533 | compatible = "altr,socfpga-lwhps2fpga-bridge"; | |
534 | reg = <0xff400000 0x100000>; | |
535 | resets = <&rst LWHPS2FPGA_RESET>; | |
536 | clocks = <&l4_main_clk>; | |
537 | }; | |
538 | ||
539 | fpga_bridge1: fpga_bridge@ff500000 { | |
540 | compatible = "altr,socfpga-hps2fpga-bridge"; | |
541 | reg = <0xff500000 0x10000>; | |
542 | resets = <&rst HPS2FPGA_RESET>; | |
543 | clocks = <&l4_main_clk>; | |
544 | }; | |
545 | ||
ebb25103 AT |
546 | fpgamgr0: fpgamgr@ff706000 { |
547 | compatible = "altr,socfpga-fpga-mgr"; | |
548 | reg = <0xff706000 0x1000 | |
6ed6bf47 | 549 | 0xffb90000 0x4>; |
ebb25103 AT |
550 | interrupts = <0 175 4>; |
551 | }; | |
552 | ||
3d954cf1 | 553 | gmac0: ethernet@ff700000 { |
66314223 | 554 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; |
2755e187 | 555 | altr,sysmgr-syscon = <&sysmgr 0x60 0>; |
66314223 DN |
556 | reg = <0xff700000 0x2000>; |
557 | interrupts = <0 115 4>; | |
558 | interrupt-names = "macirq"; | |
559 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | |
b8d9b3e4 | 560 | clocks = <&emac_0_clk>; |
3d954cf1 | 561 | clock-names = "stmmaceth"; |
16fb4f8b ST |
562 | resets = <&rst EMAC0_RESET>; |
563 | reset-names = "stmmaceth"; | |
ea6856e3 VB |
564 | snps,multicast-filter-bins = <256>; |
565 | snps,perfect-filter-entries = <128>; | |
c01e8cdb VB |
566 | tx-fifo-depth = <4096>; |
567 | rx-fifo-depth = <4096>; | |
3d954cf1 DN |
568 | status = "disabled"; |
569 | }; | |
570 | ||
571 | gmac1: ethernet@ff702000 { | |
572 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | |
2755e187 | 573 | altr,sysmgr-syscon = <&sysmgr 0x60 2>; |
3d954cf1 DN |
574 | reg = <0xff702000 0x2000>; |
575 | interrupts = <0 120 4>; | |
576 | interrupt-names = "macirq"; | |
577 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | |
b8d9b3e4 | 578 | clocks = <&emac_1_clk>; |
3d954cf1 | 579 | clock-names = "stmmaceth"; |
16fb4f8b ST |
580 | resets = <&rst EMAC1_RESET>; |
581 | reset-names = "stmmaceth"; | |
ea6856e3 VB |
582 | snps,multicast-filter-bins = <256>; |
583 | snps,perfect-filter-entries = <128>; | |
c01e8cdb VB |
584 | tx-fifo-depth = <4096>; |
585 | rx-fifo-depth = <4096>; | |
3d954cf1 | 586 | status = "disabled"; |
66314223 DN |
587 | }; |
588 | ||
d11ac1d2 | 589 | gpio0: gpio@ff708000 { |
6ec08c71 SAS |
590 | #address-cells = <1>; |
591 | #size-cells = <0>; | |
592 | compatible = "snps,dw-apb-gpio"; | |
593 | reg = <0xff708000 0x1000>; | |
e9f9fe35 | 594 | clocks = <&l4_mp_clk>; |
6ec08c71 SAS |
595 | status = "disabled"; |
596 | ||
d11ac1d2 | 597 | porta: gpio-controller@0 { |
6ec08c71 SAS |
598 | compatible = "snps,dw-apb-gpio-port"; |
599 | gpio-controller; | |
600 | #gpio-cells = <2>; | |
601 | snps,nr-gpios = <29>; | |
602 | reg = <0>; | |
603 | interrupt-controller; | |
604 | #interrupt-cells = <2>; | |
605 | interrupts = <0 164 4>; | |
606 | }; | |
607 | }; | |
608 | ||
d11ac1d2 | 609 | gpio1: gpio@ff709000 { |
6ec08c71 SAS |
610 | #address-cells = <1>; |
611 | #size-cells = <0>; | |
612 | compatible = "snps,dw-apb-gpio"; | |
613 | reg = <0xff709000 0x1000>; | |
e9f9fe35 | 614 | clocks = <&l4_mp_clk>; |
6ec08c71 SAS |
615 | status = "disabled"; |
616 | ||
d11ac1d2 | 617 | portb: gpio-controller@0 { |
6ec08c71 SAS |
618 | compatible = "snps,dw-apb-gpio-port"; |
619 | gpio-controller; | |
620 | #gpio-cells = <2>; | |
621 | snps,nr-gpios = <29>; | |
622 | reg = <0>; | |
623 | interrupt-controller; | |
624 | #interrupt-cells = <2>; | |
625 | interrupts = <0 165 4>; | |
626 | }; | |
627 | }; | |
628 | ||
d11ac1d2 | 629 | gpio2: gpio@ff70a000 { |
6ec08c71 SAS |
630 | #address-cells = <1>; |
631 | #size-cells = <0>; | |
632 | compatible = "snps,dw-apb-gpio"; | |
633 | reg = <0xff70a000 0x1000>; | |
e9f9fe35 | 634 | clocks = <&l4_mp_clk>; |
6ec08c71 SAS |
635 | status = "disabled"; |
636 | ||
d11ac1d2 | 637 | portc: gpio-controller@0 { |
6ec08c71 SAS |
638 | compatible = "snps,dw-apb-gpio-port"; |
639 | gpio-controller; | |
640 | #gpio-cells = <2>; | |
641 | snps,nr-gpios = <27>; | |
642 | reg = <0>; | |
643 | interrupt-controller; | |
644 | #interrupt-cells = <2>; | |
645 | interrupts = <0 166 4>; | |
646 | }; | |
647 | }; | |
648 | ||
0cdbec62 ST |
649 | i2c0: i2c@ffc04000 { |
650 | #address-cells = <1>; | |
651 | #size-cells = <0>; | |
652 | compatible = "snps,designware-i2c"; | |
653 | reg = <0xffc04000 0x1000>; | |
654 | clocks = <&l4_sp_clk>; | |
655 | interrupts = <0 158 0x4>; | |
656 | status = "disabled"; | |
75a41826 TT |
657 | }; |
658 | ||
0cdbec62 ST |
659 | i2c1: i2c@ffc05000 { |
660 | #address-cells = <1>; | |
661 | #size-cells = <0>; | |
662 | compatible = "snps,designware-i2c"; | |
663 | reg = <0xffc05000 0x1000>; | |
664 | clocks = <&l4_sp_clk>; | |
665 | interrupts = <0 159 0x4>; | |
666 | status = "disabled"; | |
667 | }; | |
668 | ||
669 | i2c2: i2c@ffc06000 { | |
670 | #address-cells = <1>; | |
671 | #size-cells = <0>; | |
672 | compatible = "snps,designware-i2c"; | |
673 | reg = <0xffc06000 0x1000>; | |
674 | clocks = <&l4_sp_clk>; | |
675 | interrupts = <0 160 0x4>; | |
676 | status = "disabled"; | |
677 | }; | |
678 | ||
679 | i2c3: i2c@ffc07000 { | |
680 | #address-cells = <1>; | |
681 | #size-cells = <0>; | |
682 | compatible = "snps,designware-i2c"; | |
683 | reg = <0xffc07000 0x1000>; | |
684 | clocks = <&l4_sp_clk>; | |
685 | interrupts = <0 161 0x4>; | |
686 | status = "disabled"; | |
75a41826 TT |
687 | }; |
688 | ||
0c9ff615 | 689 | eccmgr: eccmgr { |
d31e2e84 TT |
690 | compatible = "altr,socfpga-ecc-manager"; |
691 | #address-cells = <1>; | |
692 | #size-cells = <1>; | |
693 | ranges; | |
694 | ||
695 | l2-ecc@ffd08140 { | |
696 | compatible = "altr,socfpga-l2-ecc"; | |
697 | reg = <0xffd08140 0x4>; | |
698 | interrupts = <0 36 1>, <0 37 1>; | |
699 | }; | |
700 | ||
701 | ocram-ecc@ffd08144 { | |
702 | compatible = "altr,socfpga-ocram-ecc"; | |
703 | reg = <0xffd08144 0x4>; | |
704 | iram = <&ocram>; | |
705 | interrupts = <0 178 1>, <0 179 1>; | |
706 | }; | |
707 | }; | |
708 | ||
66314223 DN |
709 | L2: l2-cache@fffef000 { |
710 | compatible = "arm,pl310-cache"; | |
711 | reg = <0xfffef000 0x1000>; | |
712 | interrupts = <0 38 0x04>; | |
713 | cache-unified; | |
714 | cache-level = <2>; | |
9a21e55d DN |
715 | arm,tag-latency = <1 1 1>; |
716 | arm,data-latency = <2 1 1>; | |
2211a658 DN |
717 | prefetch-data = <1>; |
718 | prefetch-instr = <1>; | |
ecba2390 | 719 | arm,shared-override; |
7c38dc62 MV |
720 | arm,double-linefill = <1>; |
721 | arm,double-linefill-incr = <0>; | |
722 | arm,double-linefill-wrap = <1>; | |
723 | arm,prefetch-drop = <0>; | |
724 | arm,prefetch-offset = <7>; | |
66314223 DN |
725 | }; |
726 | ||
7c8e5afd AT |
727 | l3regs@0xff800000 { |
728 | compatible = "altr,l3regs", "syscon"; | |
729 | reg = <0xff800000 0x1000>; | |
730 | }; | |
731 | ||
9b931361 DN |
732 | mmc: dwmmc0@ff704000 { |
733 | compatible = "altr,socfpga-dw-mshc"; | |
734 | reg = <0xff704000 0x1000>; | |
735 | interrupts = <0 139 4>; | |
736 | fifo-depth = <0x400>; | |
737 | #address-cells = <1>; | |
738 | #size-cells = <0>; | |
5459f9ab | 739 | clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; |
9b931361 | 740 | clock-names = "biu", "ciu"; |
91f69147 | 741 | status = "disabled"; |
9b931361 DN |
742 | }; |
743 | ||
d837a80d ST |
744 | nand0: nand@ff900000 { |
745 | #address-cells = <0x1>; | |
746 | #size-cells = <0x1>; | |
747 | compatible = "denali,denali-nand-dt"; | |
748 | reg = <0xff900000 0x100000>, | |
749 | <0xffb80000 0x10000>; | |
750 | reg-names = "nand_data", "denali_reg"; | |
751 | interrupts = <0x0 0x90 0x4>; | |
752 | dma-mask = <0xffffffff>; | |
753 | clocks = <&nand_clk>; | |
754 | status = "disabled"; | |
755 | }; | |
756 | ||
8b907c8b DN |
757 | ocram: sram@ffff0000 { |
758 | compatible = "mmio-sram"; | |
759 | reg = <0xffff0000 0x10000>; | |
760 | }; | |
761 | ||
c6deff00 ST |
762 | qspi: spi@ff705000 { |
763 | compatible = "cdns,qspi-nor"; | |
764 | #address-cells = <1>; | |
765 | #size-cells = <0>; | |
766 | reg = <0xff705000 0x1000>, | |
767 | <0xffa00000 0x1000>; | |
768 | interrupts = <0 151 4>; | |
769 | cdns,fifo-depth = <128>; | |
770 | cdns,fifo-width = <4>; | |
771 | cdns,trigger-address = <0x00000000>; | |
772 | clocks = <&qspi_clk>; | |
773 | status = "disabled"; | |
774 | }; | |
775 | ||
0cdbec62 ST |
776 | rst: rstmgr@ffd05000 { |
777 | #reset-cells = <1>; | |
778 | compatible = "altr,rst-mgr"; | |
779 | reg = <0xffd05000 0x1000>; | |
780 | altr,modrst-offset = <0x10>; | |
781 | }; | |
782 | ||
783 | scu: snoop-control-unit@fffec000 { | |
784 | compatible = "arm,cortex-a9-scu"; | |
785 | reg = <0xfffec000 0x100>; | |
786 | }; | |
787 | ||
788 | sdr: sdr@ffc25000 { | |
7f0f5460 | 789 | compatible = "altr,sdr-ctl", "syscon"; |
0cdbec62 ST |
790 | reg = <0xffc25000 0x1000>; |
791 | }; | |
792 | ||
793 | sdramedac { | |
794 | compatible = "altr,sdram-edac"; | |
795 | altr,sdr-syscon = <&sdr>; | |
796 | interrupts = <0 39 4>; | |
797 | }; | |
798 | ||
ba6b96b3 TT |
799 | spi0: spi@fff00000 { |
800 | compatible = "snps,dw-apb-ssi"; | |
801 | #address-cells = <1>; | |
802 | #size-cells = <0>; | |
803 | reg = <0xfff00000 0x1000>; | |
804 | interrupts = <0 154 4>; | |
805 | num-cs = <4>; | |
806 | clocks = <&spi_m_clk>; | |
807 | status = "disabled"; | |
808 | }; | |
809 | ||
810 | spi1: spi@fff01000 { | |
811 | compatible = "snps,dw-apb-ssi"; | |
812 | #address-cells = <1>; | |
813 | #size-cells = <0>; | |
814 | reg = <0xfff01000 0x1000>; | |
1ac31de7 | 815 | interrupts = <0 155 4>; |
ba6b96b3 TT |
816 | num-cs = <4>; |
817 | clocks = <&spi_m_clk>; | |
818 | status = "disabled"; | |
819 | }; | |
820 | ||
0cdbec62 ST |
821 | sysmgr: sysmgr@ffd08000 { |
822 | compatible = "altr,sys-mgr", "syscon"; | |
823 | reg = <0xffd08000 0x4000>; | |
824 | }; | |
825 | ||
66314223 DN |
826 | /* Local timer */ |
827 | timer@fffec600 { | |
828 | compatible = "arm,cortex-a9-twd-timer"; | |
829 | reg = <0xfffec600 0x100>; | |
830 | interrupts = <1 13 0xf04>; | |
159c7f89 | 831 | clocks = <&mpu_periph_clk>; |
66314223 DN |
832 | }; |
833 | ||
c2ad2844 | 834 | timer0: timer0@ffc08000 { |
620f5e1c | 835 | compatible = "snps,dw-apb-timer"; |
66314223 | 836 | interrupts = <0 167 4>; |
66314223 | 837 | reg = <0xffc08000 0x1000>; |
bd785efd DN |
838 | clocks = <&l4_sp_clk>; |
839 | clock-names = "timer"; | |
66314223 DN |
840 | }; |
841 | ||
c2ad2844 | 842 | timer1: timer1@ffc09000 { |
620f5e1c | 843 | compatible = "snps,dw-apb-timer"; |
66314223 | 844 | interrupts = <0 168 4>; |
66314223 | 845 | reg = <0xffc09000 0x1000>; |
bd785efd DN |
846 | clocks = <&l4_sp_clk>; |
847 | clock-names = "timer"; | |
66314223 DN |
848 | }; |
849 | ||
c2ad2844 | 850 | timer2: timer2@ffd00000 { |
620f5e1c | 851 | compatible = "snps,dw-apb-timer"; |
66314223 | 852 | interrupts = <0 169 4>; |
66314223 | 853 | reg = <0xffd00000 0x1000>; |
bd785efd DN |
854 | clocks = <&osc1>; |
855 | clock-names = "timer"; | |
66314223 DN |
856 | }; |
857 | ||
c2ad2844 | 858 | timer3: timer3@ffd01000 { |
620f5e1c | 859 | compatible = "snps,dw-apb-timer"; |
66314223 | 860 | interrupts = <0 170 4>; |
66314223 | 861 | reg = <0xffd01000 0x1000>; |
bd785efd DN |
862 | clocks = <&osc1>; |
863 | clock-names = "timer"; | |
66314223 DN |
864 | }; |
865 | ||
c2ad2844 | 866 | uart0: serial0@ffc02000 { |
66314223 DN |
867 | compatible = "snps,dw-apb-uart"; |
868 | reg = <0xffc02000 0x1000>; | |
66314223 DN |
869 | interrupts = <0 162 4>; |
870 | reg-shift = <2>; | |
871 | reg-io-width = <4>; | |
bd785efd | 872 | clocks = <&l4_sp_clk>; |
78c03c7a ST |
873 | dmas = <&pdma 28>, |
874 | <&pdma 29>; | |
875 | dma-names = "tx", "rx"; | |
66314223 DN |
876 | }; |
877 | ||
c2ad2844 | 878 | uart1: serial1@ffc03000 { |
66314223 DN |
879 | compatible = "snps,dw-apb-uart"; |
880 | reg = <0xffc03000 0x1000>; | |
66314223 DN |
881 | interrupts = <0 163 4>; |
882 | reg-shift = <2>; | |
883 | reg-io-width = <4>; | |
bd785efd | 884 | clocks = <&l4_sp_clk>; |
78c03c7a ST |
885 | dmas = <&pdma 30>, |
886 | <&pdma 31>; | |
887 | dma-names = "tx", "rx"; | |
66314223 | 888 | }; |
9c4566a1 | 889 | |
0c9ff615 | 890 | usbphy0: usbphy { |
1403250b DN |
891 | #phy-cells = <0>; |
892 | compatible = "usb-nop-xceiv"; | |
893 | status = "okay"; | |
894 | }; | |
895 | ||
896 | usb0: usb@ffb00000 { | |
897 | compatible = "snps,dwc2"; | |
898 | reg = <0xffb00000 0xffff>; | |
899 | interrupts = <0 125 4>; | |
900 | clocks = <&usb_mp_clk>; | |
901 | clock-names = "otg"; | |
249ff32e DN |
902 | resets = <&rst USB0_RESET>; |
903 | reset-names = "dwc2"; | |
1403250b DN |
904 | phys = <&usbphy0>; |
905 | phy-names = "usb2-phy"; | |
906 | status = "disabled"; | |
907 | }; | |
908 | ||
909 | usb1: usb@ffb40000 { | |
910 | compatible = "snps,dwc2"; | |
911 | reg = <0xffb40000 0xffff>; | |
912 | interrupts = <0 128 4>; | |
913 | clocks = <&usb_mp_clk>; | |
914 | clock-names = "otg"; | |
249ff32e DN |
915 | resets = <&rst USB1_RESET>; |
916 | reset-names = "dwc2"; | |
1403250b DN |
917 | phys = <&usbphy0>; |
918 | phy-names = "usb2-phy"; | |
919 | status = "disabled"; | |
920 | }; | |
921 | ||
a98b6057 ST |
922 | watchdog0: watchdog@ffd02000 { |
923 | compatible = "snps,dw-wdt"; | |
924 | reg = <0xffd02000 0x1000>; | |
925 | interrupts = <0 171 4>; | |
926 | clocks = <&osc1>; | |
927 | status = "disabled"; | |
928 | }; | |
929 | ||
930 | watchdog1: watchdog@ffd03000 { | |
931 | compatible = "snps,dw-wdt"; | |
932 | reg = <0xffd03000 0x1000>; | |
933 | interrupts = <0 172 4>; | |
934 | clocks = <&osc1>; | |
935 | status = "disabled"; | |
936 | }; | |
66314223 DN |
937 | }; |
938 | }; |