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f563a571 MC |
1 | /* |
2 | * Copyright (C) 2014 STMicroelectronics Limited. | |
3 | * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * publishhed by the Free Software Foundation. | |
8 | */ | |
f563a571 | 9 | #include "stih407-pinctrl.dtsi" |
358764f3 | 10 | #include <dt-bindings/mfd/st-lpc.h> |
b3d37f92 | 11 | #include <dt-bindings/phy/phy.h> |
efdf5aa8 | 12 | #include <dt-bindings/reset/stih407-resets.h> |
107dea0c | 13 | #include <dt-bindings/interrupt-controller/irq-st.h> |
f563a571 MC |
14 | / { |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | ||
18 | cpus { | |
19 | #address-cells = <1>; | |
20 | #size-cells = <0>; | |
21 | cpu@0 { | |
22 | device_type = "cpu"; | |
23 | compatible = "arm,cortex-a9"; | |
24 | reg = <0>; | |
6fef7953 | 25 | |
c1dc02da PG |
26 | /* u-boot puts hpen in SBC dmem at 0xa4 offset */ |
27 | cpu-release-addr = <0x94100A4>; | |
6fef7953 LJ |
28 | |
29 | /* kHz uV */ | |
30 | operating-points = <1500000 0 | |
31 | 1200000 0 | |
32 | 800000 0 | |
33 | 500000 0>; | |
4ad8f3ac LJ |
34 | |
35 | clocks = <&clk_m_a9>; | |
36 | clock-names = "cpu"; | |
37 | clock-latency = <100000>; | |
f563a571 MC |
38 | }; |
39 | cpu@1 { | |
40 | device_type = "cpu"; | |
41 | compatible = "arm,cortex-a9"; | |
42 | reg = <1>; | |
6fef7953 | 43 | |
c1dc02da PG |
44 | /* u-boot puts hpen in SBC dmem at 0xa4 offset */ |
45 | cpu-release-addr = <0x94100A4>; | |
6fef7953 LJ |
46 | |
47 | /* kHz uV */ | |
48 | operating-points = <1500000 0 | |
49 | 1200000 0 | |
50 | 800000 0 | |
51 | 500000 0>; | |
f563a571 MC |
52 | }; |
53 | }; | |
54 | ||
55 | intc: interrupt-controller@08761000 { | |
56 | compatible = "arm,cortex-a9-gic"; | |
57 | #interrupt-cells = <3>; | |
58 | interrupt-controller; | |
59 | reg = <0x08761000 0x1000>, <0x08760100 0x100>; | |
60 | }; | |
61 | ||
62 | scu@08760000 { | |
63 | compatible = "arm,cortex-a9-scu"; | |
64 | reg = <0x08760000 0x1000>; | |
65 | }; | |
66 | ||
67 | timer@08760200 { | |
68 | interrupt-parent = <&intc>; | |
69 | compatible = "arm,cortex-a9-global-timer"; | |
70 | reg = <0x08760200 0x100>; | |
71 | interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
72 | clocks = <&arm_periph_clk>; | |
73 | }; | |
74 | ||
75 | l2: cache-controller { | |
76 | compatible = "arm,pl310-cache"; | |
77 | reg = <0x08762000 0x1000>; | |
78 | arm,data-latency = <3 3 3>; | |
79 | arm,tag-latency = <2 2 2>; | |
80 | cache-unified; | |
81 | cache-level = <2>; | |
82 | }; | |
83 | ||
00133b91 LJ |
84 | arm-pmu { |
85 | interrupt-parent = <&intc>; | |
86 | compatible = "arm,cortex-a9-pmu"; | |
87 | interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
88 | }; | |
89 | ||
23155ffc LJ |
90 | pwm_regulator: pwm-regulator { |
91 | compatible = "pwm-regulator"; | |
92 | pwms = <&pwm1 3 8448>; | |
93 | regulator-name = "CPU_1V0_AVS"; | |
94 | regulator-min-microvolt = <784000>; | |
95 | regulator-max-microvolt = <1299000>; | |
96 | regulator-always-on; | |
97 | max-duty-cycle = <255>; | |
98 | status = "okay"; | |
99 | }; | |
100 | ||
f563a571 MC |
101 | soc { |
102 | #address-cells = <1>; | |
103 | #size-cells = <1>; | |
104 | interrupt-parent = <&intc>; | |
105 | ranges; | |
106 | compatible = "simple-bus"; | |
107 | ||
48f3fe6b LJ |
108 | restart { |
109 | compatible = "st,stih407-restart"; | |
110 | st,syscfg = <&syscfg_sbc_reg>; | |
111 | status = "okay"; | |
112 | }; | |
113 | ||
b864a0b9 PG |
114 | powerdown: powerdown-controller { |
115 | compatible = "st,stih407-powerdown"; | |
116 | #reset-cells = <1>; | |
117 | }; | |
118 | ||
119 | softreset: softreset-controller { | |
120 | compatible = "st,stih407-softreset"; | |
121 | #reset-cells = <1>; | |
122 | }; | |
123 | ||
124 | picophyreset: picophyreset-controller { | |
125 | compatible = "st,stih407-picophyreset"; | |
126 | #reset-cells = <1>; | |
127 | }; | |
128 | ||
f563a571 MC |
129 | syscfg_sbc: sbc-syscfg@9620000 { |
130 | compatible = "st,stih407-sbc-syscfg", "syscon"; | |
131 | reg = <0x9620000 0x1000>; | |
132 | }; | |
133 | ||
134 | syscfg_front: front-syscfg@9280000 { | |
135 | compatible = "st,stih407-front-syscfg", "syscon"; | |
136 | reg = <0x9280000 0x1000>; | |
137 | }; | |
138 | ||
139 | syscfg_rear: rear-syscfg@9290000 { | |
140 | compatible = "st,stih407-rear-syscfg", "syscon"; | |
141 | reg = <0x9290000 0x1000>; | |
142 | }; | |
143 | ||
144 | syscfg_flash: flash-syscfg@92a0000 { | |
145 | compatible = "st,stih407-flash-syscfg", "syscon"; | |
146 | reg = <0x92a0000 0x1000>; | |
147 | }; | |
148 | ||
149 | syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { | |
150 | compatible = "st,stih407-sbc-reg-syscfg", "syscon"; | |
151 | reg = <0x9600000 0x1000>; | |
152 | }; | |
153 | ||
154 | syscfg_core: core-syscfg@92b0000 { | |
155 | compatible = "st,stih407-core-syscfg", "syscon"; | |
156 | reg = <0x92b0000 0x1000>; | |
157 | }; | |
158 | ||
159 | syscfg_lpm: lpm-syscfg@94b5100 { | |
160 | compatible = "st,stih407-lpm-syscfg", "syscon"; | |
161 | reg = <0x94b5100 0x1000>; | |
162 | }; | |
163 | ||
107dea0c LJ |
164 | irq-syscfg { |
165 | compatible = "st,stih407-irq-syscfg"; | |
166 | st,syscfg = <&syscfg_core>; | |
167 | st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, | |
168 | <ST_IRQ_SYSCFG_PMU_1>; | |
169 | st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, | |
170 | <ST_IRQ_SYSCFG_DISABLED>; | |
171 | }; | |
172 | ||
759742d1 MC |
173 | /* Display */ |
174 | vtg_main: sti-vtg-main@8d02800 { | |
175 | compatible = "st,vtg"; | |
176 | reg = <0x8d02800 0x200>; | |
177 | interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>; | |
178 | }; | |
179 | ||
180 | vtg_aux: sti-vtg-aux@8d00200 { | |
181 | compatible = "st,vtg"; | |
182 | reg = <0x8d00200 0x100>; | |
183 | interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>; | |
184 | }; | |
185 | ||
f563a571 MC |
186 | serial@9830000 { |
187 | compatible = "st,asc"; | |
188 | reg = <0x9830000 0x2c>; | |
189 | interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; | |
190 | pinctrl-names = "default"; | |
191 | pinctrl-0 = <&pinctrl_serial0>; | |
1befe7e4 | 192 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
193 | |
194 | status = "disabled"; | |
195 | }; | |
196 | ||
197 | serial@9831000 { | |
198 | compatible = "st,asc"; | |
199 | reg = <0x9831000 0x2c>; | |
200 | interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; | |
201 | pinctrl-names = "default"; | |
202 | pinctrl-0 = <&pinctrl_serial1>; | |
1befe7e4 | 203 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
204 | |
205 | status = "disabled"; | |
206 | }; | |
207 | ||
208 | serial@9832000 { | |
209 | compatible = "st,asc"; | |
210 | reg = <0x9832000 0x2c>; | |
211 | interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; | |
212 | pinctrl-names = "default"; | |
213 | pinctrl-0 = <&pinctrl_serial2>; | |
1befe7e4 | 214 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
215 | |
216 | status = "disabled"; | |
217 | }; | |
218 | ||
219 | /* SBC_ASC0 - UART10 */ | |
220 | sbc_serial0: serial@9530000 { | |
221 | compatible = "st,asc"; | |
222 | reg = <0x9530000 0x2c>; | |
223 | interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>; | |
224 | pinctrl-names = "default"; | |
225 | pinctrl-0 = <&pinctrl_sbc_serial0>; | |
226 | clocks = <&clk_sysin>; | |
227 | ||
228 | status = "disabled"; | |
229 | }; | |
230 | ||
231 | serial@9531000 { | |
232 | compatible = "st,asc"; | |
233 | reg = <0x9531000 0x2c>; | |
234 | interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>; | |
235 | pinctrl-names = "default"; | |
236 | pinctrl-0 = <&pinctrl_sbc_serial1>; | |
237 | clocks = <&clk_sysin>; | |
238 | ||
239 | status = "disabled"; | |
240 | }; | |
241 | ||
242 | i2c@9840000 { | |
243 | compatible = "st,comms-ssc4-i2c"; | |
244 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
245 | reg = <0x9840000 0x110>; | |
1befe7e4 | 246 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
247 | clock-names = "ssc"; |
248 | clock-frequency = <400000>; | |
249 | pinctrl-names = "default"; | |
250 | pinctrl-0 = <&pinctrl_i2c0_default>; | |
251 | ||
252 | status = "disabled"; | |
253 | }; | |
254 | ||
255 | i2c@9841000 { | |
256 | compatible = "st,comms-ssc4-i2c"; | |
257 | reg = <0x9841000 0x110>; | |
258 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 259 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
260 | clock-names = "ssc"; |
261 | clock-frequency = <400000>; | |
262 | pinctrl-names = "default"; | |
263 | pinctrl-0 = <&pinctrl_i2c1_default>; | |
264 | ||
265 | status = "disabled"; | |
266 | }; | |
267 | ||
268 | i2c@9842000 { | |
269 | compatible = "st,comms-ssc4-i2c"; | |
270 | reg = <0x9842000 0x110>; | |
271 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 272 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
273 | clock-names = "ssc"; |
274 | clock-frequency = <400000>; | |
275 | pinctrl-names = "default"; | |
276 | pinctrl-0 = <&pinctrl_i2c2_default>; | |
277 | ||
278 | status = "disabled"; | |
279 | }; | |
280 | ||
281 | i2c@9843000 { | |
282 | compatible = "st,comms-ssc4-i2c"; | |
283 | reg = <0x9843000 0x110>; | |
284 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 285 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
286 | clock-names = "ssc"; |
287 | clock-frequency = <400000>; | |
288 | pinctrl-names = "default"; | |
289 | pinctrl-0 = <&pinctrl_i2c3_default>; | |
290 | ||
291 | status = "disabled"; | |
292 | }; | |
293 | ||
294 | i2c@9844000 { | |
295 | compatible = "st,comms-ssc4-i2c"; | |
296 | reg = <0x9844000 0x110>; | |
297 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 298 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
299 | clock-names = "ssc"; |
300 | clock-frequency = <400000>; | |
301 | pinctrl-names = "default"; | |
302 | pinctrl-0 = <&pinctrl_i2c4_default>; | |
303 | ||
304 | status = "disabled"; | |
305 | }; | |
306 | ||
307 | i2c@9845000 { | |
308 | compatible = "st,comms-ssc4-i2c"; | |
309 | reg = <0x9845000 0x110>; | |
310 | interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 311 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
312 | clock-names = "ssc"; |
313 | clock-frequency = <400000>; | |
314 | pinctrl-names = "default"; | |
315 | pinctrl-0 = <&pinctrl_i2c5_default>; | |
316 | ||
317 | status = "disabled"; | |
318 | }; | |
319 | ||
320 | ||
321 | /* SSCs on SBC */ | |
322 | i2c@9540000 { | |
323 | compatible = "st,comms-ssc4-i2c"; | |
324 | reg = <0x9540000 0x110>; | |
325 | interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; | |
326 | clocks = <&clk_sysin>; | |
327 | clock-names = "ssc"; | |
328 | clock-frequency = <400000>; | |
329 | pinctrl-names = "default"; | |
330 | pinctrl-0 = <&pinctrl_i2c10_default>; | |
331 | ||
332 | status = "disabled"; | |
333 | }; | |
334 | ||
335 | i2c@9541000 { | |
336 | compatible = "st,comms-ssc4-i2c"; | |
337 | reg = <0x9541000 0x110>; | |
338 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; | |
339 | clocks = <&clk_sysin>; | |
340 | clock-names = "ssc"; | |
341 | clock-frequency = <400000>; | |
342 | pinctrl-names = "default"; | |
343 | pinctrl-0 = <&pinctrl_i2c11_default>; | |
344 | ||
345 | status = "disabled"; | |
346 | }; | |
8facce13 PG |
347 | |
348 | usb2_picophy0: phy1 { | |
349 | compatible = "st,stih407-usb2-phy"; | |
350 | #phy-cells = <0>; | |
351 | st,syscfg = <&syscfg_core 0x100 0xf4>; | |
352 | resets = <&softreset STIH407_PICOPHY_SOFTRESET>, | |
743ac9d2 | 353 | <&picophyreset STIH407_PICOPHY2_RESET>; |
8facce13 PG |
354 | reset-names = "global", "port"; |
355 | }; | |
b26373c0 GF |
356 | |
357 | miphy28lp_phy: miphy28lp@9b22000 { | |
358 | compatible = "st,miphy28lp-phy"; | |
359 | st,syscfg = <&syscfg_core>; | |
360 | #address-cells = <1>; | |
361 | #size-cells = <1>; | |
362 | ranges; | |
363 | ||
364 | phy_port0: port@9b22000 { | |
365 | reg = <0x9b22000 0xff>, | |
366 | <0x9b09000 0xff>, | |
367 | <0x9b04000 0xff>; | |
368 | reg-names = "sata-up", | |
369 | "pcie-up", | |
370 | "pipew"; | |
371 | ||
372 | st,syscfg = <0x114 0x818 0xe0 0xec>; | |
373 | #phy-cells = <1>; | |
374 | ||
375 | reset-names = "miphy-sw-rst"; | |
376 | resets = <&softreset STIH407_MIPHY0_SOFTRESET>; | |
377 | }; | |
378 | ||
379 | phy_port1: port@9b2a000 { | |
380 | reg = <0x9b2a000 0xff>, | |
381 | <0x9b19000 0xff>, | |
382 | <0x9b14000 0xff>; | |
383 | reg-names = "sata-up", | |
384 | "pcie-up", | |
385 | "pipew"; | |
386 | ||
387 | st,syscfg = <0x118 0x81c 0xe4 0xf0>; | |
388 | ||
389 | #phy-cells = <1>; | |
390 | ||
391 | reset-names = "miphy-sw-rst"; | |
392 | resets = <&softreset STIH407_MIPHY1_SOFTRESET>; | |
393 | }; | |
394 | ||
395 | phy_port2: port@8f95000 { | |
396 | reg = <0x8f95000 0xff>, | |
397 | <0x8f90000 0xff>; | |
398 | reg-names = "pipew", | |
399 | "usb3-up"; | |
400 | ||
401 | st,syscfg = <0x11c 0x820>; | |
402 | ||
403 | #phy-cells = <1>; | |
404 | ||
405 | reset-names = "miphy-sw-rst"; | |
406 | resets = <&softreset STIH407_MIPHY2_SOFTRESET>; | |
407 | }; | |
408 | }; | |
2c53c272 LJ |
409 | |
410 | spi@9840000 { | |
411 | compatible = "st,comms-ssc4-spi"; | |
412 | reg = <0x9840000 0x110>; | |
413 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
414 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
415 | clock-names = "ssc"; | |
416 | pinctrl-0 = <&pinctrl_spi0_default>; | |
417 | pinctrl-names = "default"; | |
418 | #address-cells = <1>; | |
419 | #size-cells = <0>; | |
420 | ||
421 | status = "disabled"; | |
422 | }; | |
423 | ||
424 | spi@9841000 { | |
425 | compatible = "st,comms-ssc4-spi"; | |
426 | reg = <0x9841000 0x110>; | |
427 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
428 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
429 | clock-names = "ssc"; | |
55fd9b18 PG |
430 | pinctrl-names = "default"; |
431 | pinctrl-0 = <&pinctrl_spi1_default>; | |
2c53c272 LJ |
432 | |
433 | status = "disabled"; | |
434 | }; | |
435 | ||
436 | spi@9842000 { | |
437 | compatible = "st,comms-ssc4-spi"; | |
438 | reg = <0x9842000 0x110>; | |
439 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
440 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
441 | clock-names = "ssc"; | |
55fd9b18 PG |
442 | pinctrl-names = "default"; |
443 | pinctrl-0 = <&pinctrl_spi2_default>; | |
2c53c272 LJ |
444 | |
445 | status = "disabled"; | |
446 | }; | |
447 | ||
448 | spi@9843000 { | |
449 | compatible = "st,comms-ssc4-spi"; | |
450 | reg = <0x9843000 0x110>; | |
451 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
452 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
453 | clock-names = "ssc"; | |
55fd9b18 PG |
454 | pinctrl-names = "default"; |
455 | pinctrl-0 = <&pinctrl_spi3_default>; | |
2c53c272 LJ |
456 | |
457 | status = "disabled"; | |
458 | }; | |
459 | ||
460 | spi@9844000 { | |
461 | compatible = "st,comms-ssc4-spi"; | |
462 | reg = <0x9844000 0x110>; | |
463 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
464 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
465 | clock-names = "ssc"; | |
55fd9b18 PG |
466 | pinctrl-names = "default"; |
467 | pinctrl-0 = <&pinctrl_spi4_default>; | |
2c53c272 LJ |
468 | |
469 | status = "disabled"; | |
470 | }; | |
b0bb2bae LJ |
471 | |
472 | /* SBC SSC */ | |
473 | spi@9540000 { | |
474 | compatible = "st,comms-ssc4-spi"; | |
475 | reg = <0x9540000 0x110>; | |
476 | interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; | |
477 | clocks = <&clk_sysin>; | |
478 | clock-names = "ssc"; | |
55fd9b18 PG |
479 | pinctrl-names = "default"; |
480 | pinctrl-0 = <&pinctrl_spi10_default>; | |
b0bb2bae LJ |
481 | |
482 | status = "disabled"; | |
483 | }; | |
484 | ||
485 | spi@9541000 { | |
486 | compatible = "st,comms-ssc4-spi"; | |
487 | reg = <0x9541000 0x110>; | |
488 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; | |
489 | clocks = <&clk_sysin>; | |
490 | clock-names = "ssc"; | |
55fd9b18 PG |
491 | pinctrl-names = "default"; |
492 | pinctrl-0 = <&pinctrl_spi11_default>; | |
b0bb2bae LJ |
493 | |
494 | status = "disabled"; | |
495 | }; | |
496 | ||
497 | spi@9542000 { | |
498 | compatible = "st,comms-ssc4-spi"; | |
499 | reg = <0x9542000 0x110>; | |
500 | interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; | |
501 | clocks = <&clk_sysin>; | |
502 | clock-names = "ssc"; | |
55fd9b18 PG |
503 | pinctrl-names = "default"; |
504 | pinctrl-0 = <&pinctrl_spi12_default>; | |
b0bb2bae LJ |
505 | |
506 | status = "disabled"; | |
507 | }; | |
9286ac48 PG |
508 | |
509 | mmc0: sdhci@09060000 { | |
510 | compatible = "st,sdhci-stih407", "st,sdhci"; | |
511 | status = "disabled"; | |
512 | reg = <0x09060000 0x7ff>, <0x9061008 0x20>; | |
513 | reg-names = "mmc", "top-mmc-delay"; | |
514 | interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>; | |
515 | interrupt-names = "mmcirq"; | |
516 | pinctrl-names = "default"; | |
517 | pinctrl-0 = <&pinctrl_mmc0>; | |
518 | clock-names = "mmc"; | |
519 | clocks = <&clk_s_c0_flexgen CLK_MMC_0>; | |
520 | bus-width = <8>; | |
521 | non-removable; | |
522 | }; | |
523 | ||
524 | mmc1: sdhci@09080000 { | |
525 | compatible = "st,sdhci-stih407", "st,sdhci"; | |
526 | status = "disabled"; | |
527 | reg = <0x09080000 0x7ff>; | |
528 | reg-names = "mmc"; | |
529 | interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>; | |
530 | interrupt-names = "mmcirq"; | |
531 | pinctrl-names = "default"; | |
532 | pinctrl-0 = <&pinctrl_sd1>; | |
533 | clock-names = "mmc"; | |
534 | clocks = <&clk_s_c0_flexgen CLK_MMC_1>; | |
535 | resets = <&softreset STIH407_MMC1_SOFTRESET>; | |
536 | bus-width = <4>; | |
537 | }; | |
358764f3 LJ |
538 | |
539 | /* Watchdog and Real-Time Clock */ | |
540 | lpc@8787000 { | |
541 | compatible = "st,stih407-lpc"; | |
542 | reg = <0x8787000 0x1000>; | |
543 | interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>; | |
544 | clocks = <&clk_s_d3_flexgen CLK_LPC_0>; | |
545 | timeout-sec = <120>; | |
546 | st,syscfg = <&syscfg_core>; | |
547 | st,lpc-mode = <ST_LPC_MODE_WDT>; | |
548 | }; | |
549 | ||
550 | lpc@8788000 { | |
551 | compatible = "st,stih407-lpc"; | |
552 | reg = <0x8788000 0x1000>; | |
553 | interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>; | |
554 | clocks = <&clk_s_d3_flexgen CLK_LPC_1>; | |
555 | st,lpc-mode = <ST_LPC_MODE_RTC>; | |
556 | }; | |
b3d37f92 PG |
557 | |
558 | sata0: sata@9b20000 { | |
559 | compatible = "st,ahci"; | |
560 | reg = <0x9b20000 0x1000>; | |
561 | ||
562 | interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; | |
563 | interrupt-names = "hostc"; | |
564 | ||
565 | phys = <&phy_port0 PHY_TYPE_SATA>; | |
566 | phy-names = "ahci_phy"; | |
567 | ||
568 | resets = <&powerdown STIH407_SATA0_POWERDOWN>, | |
569 | <&softreset STIH407_SATA0_SOFTRESET>, | |
570 | <&softreset STIH407_SATA0_PWR_SOFTRESET>; | |
571 | reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; | |
572 | ||
573 | clock-names = "ahci_clk"; | |
574 | clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; | |
575 | ||
576 | status = "disabled"; | |
577 | }; | |
578 | ||
579 | sata1: sata@9b28000 { | |
580 | compatible = "st,ahci"; | |
581 | reg = <0x9b28000 0x1000>; | |
582 | ||
583 | interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>; | |
584 | interrupt-names = "hostc"; | |
585 | ||
586 | phys = <&phy_port1 PHY_TYPE_SATA>; | |
587 | phy-names = "ahci_phy"; | |
588 | ||
589 | resets = <&powerdown STIH407_SATA1_POWERDOWN>, | |
590 | <&softreset STIH407_SATA1_SOFTRESET>, | |
591 | <&softreset STIH407_SATA1_PWR_SOFTRESET>; | |
592 | reset-names = "pwr-dwn", | |
593 | "sw-rst", | |
594 | "pwr-rst"; | |
595 | ||
596 | clock-names = "ahci_clk"; | |
597 | clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; | |
598 | ||
599 | status = "disabled"; | |
600 | }; | |
fd555998 | 601 | |
cd9f59ca | 602 | |
fd555998 PG |
603 | st_dwc3: dwc3@8f94000 { |
604 | compatible = "st,stih407-dwc3"; | |
605 | reg = <0x08f94000 0x1000>, <0x110 0x4>; | |
606 | reg-names = "reg-glue", "syscfg-reg"; | |
607 | st,syscfg = <&syscfg_core>; | |
608 | resets = <&powerdown STIH407_USB3_POWERDOWN>, | |
609 | <&softreset STIH407_MIPHY2_SOFTRESET>; | |
610 | reset-names = "powerdown", "softreset"; | |
611 | #address-cells = <1>; | |
612 | #size-cells = <1>; | |
613 | pinctrl-names = "default"; | |
614 | pinctrl-0 = <&pinctrl_usb3>; | |
615 | ranges; | |
616 | ||
617 | status = "disabled"; | |
618 | ||
619 | dwc3: dwc3@9900000 { | |
620 | compatible = "snps,dwc3"; | |
621 | reg = <0x09900000 0x100000>; | |
622 | interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; | |
623 | dr_mode = "host"; | |
624 | phy-names = "usb2-phy", "usb3-phy"; | |
625 | phys = <&usb2_picophy0>, | |
626 | <&phy_port2 PHY_TYPE_USB3>; | |
627 | }; | |
628 | }; | |
cd9f59ca LJ |
629 | |
630 | /* COMMS PWM Module */ | |
631 | pwm0: pwm@9810000 { | |
632 | compatible = "st,sti-pwm"; | |
cd9f59ca LJ |
633 | #pwm-cells = <2>; |
634 | reg = <0x9810000 0x68>; | |
635 | pinctrl-names = "default"; | |
636 | pinctrl-0 = <&pinctrl_pwm0_chan0_default>; | |
637 | clock-names = "pwm"; | |
638 | clocks = <&clk_sysin>; | |
639 | st,pwm-num-chan = <1>; | |
8aa5f09d MC |
640 | |
641 | status = "disabled"; | |
cd9f59ca LJ |
642 | }; |
643 | ||
644 | /* SBC PWM Module */ | |
645 | pwm1: pwm@9510000 { | |
646 | compatible = "st,sti-pwm"; | |
cd9f59ca LJ |
647 | #pwm-cells = <2>; |
648 | reg = <0x9510000 0x68>; | |
649 | pinctrl-names = "default"; | |
650 | pinctrl-0 = <&pinctrl_pwm1_chan0_default | |
651 | &pinctrl_pwm1_chan1_default | |
652 | &pinctrl_pwm1_chan2_default | |
653 | &pinctrl_pwm1_chan3_default>; | |
654 | clock-names = "pwm"; | |
655 | clocks = <&clk_sysin>; | |
656 | st,pwm-num-chan = <4>; | |
8aa5f09d MC |
657 | |
658 | status = "disabled"; | |
cd9f59ca | 659 | }; |
cae010a1 LJ |
660 | |
661 | rng10: rng@08a89000 { | |
662 | compatible = "st,rng"; | |
663 | reg = <0x08a89000 0x1000>; | |
664 | clocks = <&clk_sysin>; | |
665 | status = "okay"; | |
666 | }; | |
667 | ||
668 | rng11: rng@08a8a000 { | |
669 | compatible = "st,rng"; | |
670 | reg = <0x08a8a000 0x1000>; | |
671 | clocks = <&clk_sysin>; | |
672 | status = "okay"; | |
673 | }; | |
ab511d7d MC |
674 | |
675 | ethernet0: dwmac@9630000 { | |
676 | device_type = "network"; | |
677 | status = "disabled"; | |
678 | compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; | |
679 | reg = <0x9630000 0x8000>, <0x80 0x4>; | |
680 | reg-names = "stmmaceth", "sti-ethconf"; | |
681 | ||
682 | st,syscon = <&syscfg_sbc_reg 0x80>; | |
683 | st,gmac_en; | |
684 | resets = <&softreset STIH407_ETH1_SOFTRESET>; | |
685 | reset-names = "stmmaceth"; | |
686 | ||
687 | interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, | |
688 | <GIC_SPI 99 IRQ_TYPE_NONE>; | |
689 | interrupt-names = "macirq", "eth_wake_irq"; | |
690 | ||
691 | /* DMA Bus Mode */ | |
692 | snps,pbl = <8>; | |
693 | ||
694 | pinctrl-names = "default"; | |
695 | pinctrl-0 = <&pinctrl_rgmii1>; | |
696 | ||
697 | clock-names = "stmmaceth", "sti-ethclk"; | |
698 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, | |
699 | <&clk_s_c0_flexgen CLK_ETH_PHY>; | |
cd9f59ca | 700 | }; |
ba25d8b4 LJ |
701 | |
702 | rng10: rng@08a89000 { | |
703 | compatible = "st,rng"; | |
704 | reg = <0x08a89000 0x1000>; | |
705 | clocks = <&clk_sysin>; | |
706 | status = "okay"; | |
707 | }; | |
708 | ||
709 | rng11: rng@08a8a000 { | |
710 | compatible = "st,rng"; | |
711 | reg = <0x08a8a000 0x1000>; | |
712 | clocks = <&clk_sysin>; | |
713 | status = "okay"; | |
714 | }; | |
f563a571 MC |
715 | }; |
716 | }; |