]>
Commit | Line | Data |
---|---|---|
a5e921b4 | 1 | /* |
77896e4d | 2 | * Device Tree Source for UniPhier PXs2 SoC |
a5e921b4 | 3 | * |
77896e4d MY |
4 | * Copyright (C) 2015-2016 Socionext Inc. |
5 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
a5e921b4 MY |
6 | * |
7 | * This file is dual-licensed: you can use it either under the terms | |
8 | * of the GPL or the X11 license, at your option. Note that this dual | |
9 | * licensing only applies to this file, and not this project as a | |
10 | * whole. | |
11 | * | |
12 | * a) This file is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of the | |
15 | * License, or (at your option) any later version. | |
16 | * | |
17 | * This file is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * Or, alternatively, | |
23 | * | |
24 | * b) Permission is hereby granted, free of charge, to any person | |
25 | * obtaining a copy of this software and associated documentation | |
26 | * files (the "Software"), to deal in the Software without | |
27 | * restriction, including without limitation the rights to use, | |
28 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
29 | * sell copies of the Software, and to permit persons to whom the | |
30 | * Software is furnished to do so, subject to the following | |
31 | * conditions: | |
32 | * | |
33 | * The above copyright notice and this permission notice shall be | |
34 | * included in all copies or substantial portions of the Software. | |
35 | * | |
36 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
37 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
38 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
39 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
40 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
41 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
42 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
43 | * OTHER DEALINGS IN THE SOFTWARE. | |
44 | */ | |
45 | ||
2752bcaa | 46 | /include/ "skeleton.dtsi" |
a5e921b4 MY |
47 | |
48 | / { | |
77896e4d | 49 | compatible = "socionext,uniphier-pxs2"; |
a5e921b4 MY |
50 | |
51 | cpus { | |
52 | #address-cells = <1>; | |
53 | #size-cells = <0>; | |
a5e921b4 MY |
54 | |
55 | cpu@0 { | |
56 | device_type = "cpu"; | |
57 | compatible = "arm,cortex-a9"; | |
58 | reg = <0>; | |
7a8a6588 | 59 | clocks = <&sys_clk 32>; |
3bdba5ac | 60 | enable-method = "psci"; |
7c62f299 | 61 | next-level-cache = <&l2>; |
7a8a6588 | 62 | operating-points-v2 = <&cpu_opp>; |
a5e921b4 MY |
63 | }; |
64 | ||
65 | cpu@1 { | |
66 | device_type = "cpu"; | |
67 | compatible = "arm,cortex-a9"; | |
68 | reg = <1>; | |
7a8a6588 | 69 | clocks = <&sys_clk 32>; |
3bdba5ac | 70 | enable-method = "psci"; |
7c62f299 | 71 | next-level-cache = <&l2>; |
7a8a6588 | 72 | operating-points-v2 = <&cpu_opp>; |
a5e921b4 MY |
73 | }; |
74 | ||
75 | cpu@2 { | |
76 | device_type = "cpu"; | |
77 | compatible = "arm,cortex-a9"; | |
78 | reg = <2>; | |
7a8a6588 | 79 | clocks = <&sys_clk 32>; |
3bdba5ac | 80 | enable-method = "psci"; |
7c62f299 | 81 | next-level-cache = <&l2>; |
7a8a6588 | 82 | operating-points-v2 = <&cpu_opp>; |
a5e921b4 MY |
83 | }; |
84 | ||
85 | cpu@3 { | |
86 | device_type = "cpu"; | |
87 | compatible = "arm,cortex-a9"; | |
88 | reg = <3>; | |
7a8a6588 | 89 | clocks = <&sys_clk 32>; |
3bdba5ac | 90 | enable-method = "psci"; |
7c62f299 | 91 | next-level-cache = <&l2>; |
7a8a6588 MY |
92 | operating-points-v2 = <&cpu_opp>; |
93 | }; | |
94 | }; | |
95 | ||
96 | cpu_opp: opp_table { | |
97 | compatible = "operating-points-v2"; | |
98 | opp-shared; | |
99 | ||
100 | opp@100000000 { | |
101 | opp-hz = /bits/ 64 <100000000>; | |
102 | clock-latency-ns = <300>; | |
103 | }; | |
104 | opp@150000000 { | |
105 | opp-hz = /bits/ 64 <150000000>; | |
106 | clock-latency-ns = <300>; | |
107 | }; | |
108 | opp@200000000 { | |
109 | opp-hz = /bits/ 64 <200000000>; | |
110 | clock-latency-ns = <300>; | |
111 | }; | |
112 | opp@300000000 { | |
113 | opp-hz = /bits/ 64 <300000000>; | |
114 | clock-latency-ns = <300>; | |
115 | }; | |
116 | opp@400000000 { | |
117 | opp-hz = /bits/ 64 <400000000>; | |
118 | clock-latency-ns = <300>; | |
119 | }; | |
120 | opp@600000000 { | |
121 | opp-hz = /bits/ 64 <600000000>; | |
122 | clock-latency-ns = <300>; | |
123 | }; | |
124 | opp@800000000 { | |
125 | opp-hz = /bits/ 64 <800000000>; | |
126 | clock-latency-ns = <300>; | |
127 | }; | |
128 | opp@1200000000 { | |
129 | opp-hz = /bits/ 64 <1200000000>; | |
130 | clock-latency-ns = <300>; | |
a5e921b4 MY |
131 | }; |
132 | }; | |
133 | ||
2752bcaa MY |
134 | psci { |
135 | compatible = "arm,psci-0.2"; | |
136 | method = "smc"; | |
137 | }; | |
138 | ||
a5e921b4 | 139 | clocks { |
2752bcaa MY |
140 | refclk: ref { |
141 | compatible = "fixed-clock"; | |
142 | #clock-cells = <0>; | |
143 | clock-frequency = <25000000>; | |
144 | }; | |
145 | ||
a5e921b4 MY |
146 | arm_timer_clk: arm_timer_clk { |
147 | #clock-cells = <0>; | |
148 | compatible = "fixed-clock"; | |
149 | clock-frequency = <50000000>; | |
150 | }; | |
a5e921b4 MY |
151 | }; |
152 | ||
2752bcaa MY |
153 | soc { |
154 | compatible = "simple-bus"; | |
629b557a | 155 | #address-cells = <1>; |
2752bcaa MY |
156 | #size-cells = <1>; |
157 | ranges; | |
158 | interrupt-parent = <&intc>; | |
a5e921b4 | 159 | |
2752bcaa MY |
160 | l2: l2-cache@500c0000 { |
161 | compatible = "socionext,uniphier-system-cache"; | |
162 | reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, | |
163 | <0x506c0000 0x400>; | |
164 | interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; | |
165 | cache-unified; | |
166 | cache-size = <(1280 * 1024)>; | |
167 | cache-sets = <512>; | |
168 | cache-line-size = <128>; | |
169 | cache-level = <2>; | |
170 | }; | |
a5e921b4 | 171 | |
2752bcaa MY |
172 | serial0: serial@54006800 { |
173 | compatible = "socionext,uniphier-uart"; | |
174 | status = "disabled"; | |
175 | reg = <0x54006800 0x40>; | |
176 | interrupts = <0 33 4>; | |
177 | pinctrl-names = "default"; | |
178 | pinctrl-0 = <&pinctrl_uart0>; | |
179 | clocks = <&peri_clk 0>; | |
180 | }; | |
a5e921b4 | 181 | |
2752bcaa MY |
182 | serial1: serial@54006900 { |
183 | compatible = "socionext,uniphier-uart"; | |
184 | status = "disabled"; | |
185 | reg = <0x54006900 0x40>; | |
186 | interrupts = <0 35 4>; | |
187 | pinctrl-names = "default"; | |
188 | pinctrl-0 = <&pinctrl_uart1>; | |
189 | clocks = <&peri_clk 1>; | |
190 | }; | |
a5e921b4 | 191 | |
2752bcaa MY |
192 | serial2: serial@54006a00 { |
193 | compatible = "socionext,uniphier-uart"; | |
194 | status = "disabled"; | |
195 | reg = <0x54006a00 0x40>; | |
196 | interrupts = <0 37 4>; | |
197 | pinctrl-names = "default"; | |
198 | pinctrl-0 = <&pinctrl_uart2>; | |
199 | clocks = <&peri_clk 2>; | |
200 | }; | |
a5e921b4 | 201 | |
2752bcaa MY |
202 | serial3: serial@54006b00 { |
203 | compatible = "socionext,uniphier-uart"; | |
204 | status = "disabled"; | |
205 | reg = <0x54006b00 0x40>; | |
206 | interrupts = <0 177 4>; | |
207 | pinctrl-names = "default"; | |
208 | pinctrl-0 = <&pinctrl_uart3>; | |
209 | clocks = <&peri_clk 3>; | |
210 | }; | |
a5e921b4 | 211 | |
2752bcaa MY |
212 | i2c0: i2c@58780000 { |
213 | compatible = "socionext,uniphier-fi2c"; | |
214 | status = "disabled"; | |
215 | reg = <0x58780000 0x80>; | |
216 | #address-cells = <1>; | |
217 | #size-cells = <0>; | |
218 | interrupts = <0 41 4>; | |
219 | pinctrl-names = "default"; | |
220 | pinctrl-0 = <&pinctrl_i2c0>; | |
221 | clocks = <&peri_clk 4>; | |
222 | clock-frequency = <100000>; | |
223 | }; | |
a5e921b4 | 224 | |
2752bcaa MY |
225 | i2c1: i2c@58781000 { |
226 | compatible = "socionext,uniphier-fi2c"; | |
227 | status = "disabled"; | |
228 | reg = <0x58781000 0x80>; | |
229 | #address-cells = <1>; | |
230 | #size-cells = <0>; | |
231 | interrupts = <0 42 4>; | |
232 | pinctrl-names = "default"; | |
233 | pinctrl-0 = <&pinctrl_i2c1>; | |
234 | clocks = <&peri_clk 5>; | |
235 | clock-frequency = <100000>; | |
236 | }; | |
61f838c7 | 237 | |
2752bcaa MY |
238 | i2c2: i2c@58782000 { |
239 | compatible = "socionext,uniphier-fi2c"; | |
240 | status = "disabled"; | |
241 | reg = <0x58782000 0x80>; | |
242 | #address-cells = <1>; | |
243 | #size-cells = <0>; | |
244 | interrupts = <0 43 4>; | |
245 | pinctrl-names = "default"; | |
246 | pinctrl-0 = <&pinctrl_i2c2>; | |
247 | clocks = <&peri_clk 6>; | |
248 | clock-frequency = <100000>; | |
249 | }; | |
ad0561d4 | 250 | |
2752bcaa MY |
251 | i2c3: i2c@58783000 { |
252 | compatible = "socionext,uniphier-fi2c"; | |
253 | status = "disabled"; | |
254 | reg = <0x58783000 0x80>; | |
255 | #address-cells = <1>; | |
256 | #size-cells = <0>; | |
257 | interrupts = <0 44 4>; | |
258 | pinctrl-names = "default"; | |
259 | pinctrl-0 = <&pinctrl_i2c3>; | |
260 | clocks = <&peri_clk 7>; | |
261 | clock-frequency = <100000>; | |
262 | }; | |
ad0561d4 | 263 | |
2752bcaa MY |
264 | /* chip-internal connection for DMD */ |
265 | i2c4: i2c@58784000 { | |
266 | compatible = "socionext,uniphier-fi2c"; | |
267 | reg = <0x58784000 0x80>; | |
268 | #address-cells = <1>; | |
269 | #size-cells = <0>; | |
270 | interrupts = <0 45 4>; | |
271 | clocks = <&peri_clk 8>; | |
272 | clock-frequency = <400000>; | |
273 | }; | |
ad0561d4 | 274 | |
2752bcaa MY |
275 | /* chip-internal connection for STM */ |
276 | i2c5: i2c@58785000 { | |
277 | compatible = "socionext,uniphier-fi2c"; | |
278 | reg = <0x58785000 0x80>; | |
279 | #address-cells = <1>; | |
280 | #size-cells = <0>; | |
281 | interrupts = <0 25 4>; | |
282 | clocks = <&peri_clk 9>; | |
283 | clock-frequency = <400000>; | |
284 | }; | |
ad0561d4 | 285 | |
2752bcaa MY |
286 | /* chip-internal connection for HDMI */ |
287 | i2c6: i2c@58786000 { | |
288 | compatible = "socionext,uniphier-fi2c"; | |
289 | reg = <0x58786000 0x80>; | |
290 | #address-cells = <1>; | |
291 | #size-cells = <0>; | |
292 | interrupts = <0 26 4>; | |
293 | clocks = <&peri_clk 10>; | |
294 | clock-frequency = <400000>; | |
295 | }; | |
ad0561d4 | 296 | |
2752bcaa MY |
297 | system_bus: system-bus@58c00000 { |
298 | compatible = "socionext,uniphier-system-bus"; | |
299 | status = "disabled"; | |
300 | reg = <0x58c00000 0x400>; | |
301 | #address-cells = <2>; | |
302 | #size-cells = <1>; | |
303 | pinctrl-names = "default"; | |
304 | pinctrl-0 = <&pinctrl_system_bus>; | |
305 | }; | |
306 | ||
307 | smpctrl@59800000 { | |
308 | compatible = "socionext,uniphier-smpctrl"; | |
309 | reg = <0x59801000 0x400>; | |
310 | }; | |
311 | ||
312 | sdctrl@59810000 { | |
313 | compatible = "socionext,uniphier-pxs2-sdctrl", | |
314 | "simple-mfd", "syscon"; | |
315 | reg = <0x59810000 0x800>; | |
316 | ||
317 | sd_clk: clock { | |
318 | compatible = "socionext,uniphier-pxs2-sd-clock"; | |
319 | #clock-cells = <1>; | |
320 | }; | |
321 | ||
322 | sd_rst: reset { | |
323 | compatible = "socionext,uniphier-pxs2-sd-reset"; | |
324 | #reset-cells = <1>; | |
325 | }; | |
326 | }; | |
ad0561d4 | 327 | |
2752bcaa MY |
328 | perictrl@59820000 { |
329 | compatible = "socionext,uniphier-pxs2-perictrl", | |
330 | "simple-mfd", "syscon"; | |
331 | reg = <0x59820000 0x200>; | |
332 | ||
333 | peri_clk: clock { | |
334 | compatible = "socionext,uniphier-pxs2-peri-clock"; | |
335 | #clock-cells = <1>; | |
336 | }; | |
337 | ||
338 | peri_rst: reset { | |
339 | compatible = "socionext,uniphier-pxs2-peri-reset"; | |
340 | #reset-cells = <1>; | |
341 | }; | |
342 | }; | |
343 | ||
344 | soc-glue@5f800000 { | |
345 | compatible = "socionext,uniphier-pxs2-soc-glue", | |
346 | "simple-mfd", "syscon"; | |
347 | reg = <0x5f800000 0x2000>; | |
348 | ||
349 | pinctrl: pinctrl { | |
350 | compatible = "socionext,uniphier-pxs2-pinctrl"; | |
351 | }; | |
352 | }; | |
353 | ||
354 | timer@60000200 { | |
355 | compatible = "arm,cortex-a9-global-timer"; | |
356 | reg = <0x60000200 0x20>; | |
357 | interrupts = <1 11 0xf04>; | |
358 | clocks = <&arm_timer_clk>; | |
359 | }; | |
360 | ||
361 | timer@60000600 { | |
362 | compatible = "arm,cortex-a9-twd-timer"; | |
363 | reg = <0x60000600 0x20>; | |
364 | interrupts = <1 13 0xf04>; | |
365 | clocks = <&arm_timer_clk>; | |
366 | }; | |
367 | ||
368 | intc: interrupt-controller@60001000 { | |
369 | compatible = "arm,cortex-a9-gic"; | |
370 | reg = <0x60001000 0x1000>, | |
371 | <0x60000100 0x100>; | |
372 | #interrupt-cells = <3>; | |
373 | interrupt-controller; | |
374 | }; | |
375 | ||
376 | sysctrl@61840000 { | |
377 | compatible = "socionext,uniphier-pxs2-sysctrl", | |
378 | "simple-mfd", "syscon"; | |
379 | reg = <0x61840000 0x10000>; | |
380 | ||
381 | sys_clk: clock { | |
382 | compatible = "socionext,uniphier-pxs2-clock"; | |
383 | #clock-cells = <1>; | |
384 | }; | |
385 | ||
386 | sys_rst: reset { | |
387 | compatible = "socionext,uniphier-pxs2-reset"; | |
388 | #reset-cells = <1>; | |
389 | }; | |
390 | }; | |
391 | }; | |
ad0561d4 | 392 | }; |
2752bcaa MY |
393 | |
394 | /include/ "uniphier-pinctrl.dtsi" |