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877d7720 AV |
1 | /* |
2 | * arch/arm/mach-at91/at91sam9rl.c | |
3 | * | |
4 | * Copyright (C) 2005 SAN People | |
5 | * Copyright (C) 2007 Atmel Corporation | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file COPYING in the main directory of this archive for | |
9 | * more details. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
2edb90ae | 13 | #include <linux/clk/at91_pmc.h> |
877d7720 | 14 | |
c9dfafba | 15 | #include <asm/proc-fns.h> |
80b02c17 | 16 | #include <asm/irq.h> |
877d7720 AV |
17 | #include <asm/mach/arch.h> |
18 | #include <asm/mach/map.h> | |
9f97da78 | 19 | #include <asm/system_misc.h> |
a09e64fb | 20 | #include <mach/cpu.h> |
8c3583b6 | 21 | #include <mach/at91_dbgu.h> |
a09e64fb | 22 | #include <mach/at91sam9rl.h> |
877d7720 | 23 | |
a510b9ba | 24 | #include "at91_aic.h" |
f0995d08 | 25 | #include "at91_rstc.h" |
21d08b9d | 26 | #include "soc.h" |
877d7720 AV |
27 | #include "generic.h" |
28 | #include "clock.h" | |
faee0cc3 | 29 | #include "sam9_smc.h" |
5ad945ea | 30 | #include "pm.h" |
877d7720 | 31 | |
877d7720 AV |
32 | /* -------------------------------------------------------------------- |
33 | * Clocks | |
34 | * -------------------------------------------------------------------- */ | |
35 | ||
36 | /* | |
37 | * The peripheral clocks. | |
38 | */ | |
39 | static struct clk pioA_clk = { | |
40 | .name = "pioA_clk", | |
41 | .pmc_mask = 1 << AT91SAM9RL_ID_PIOA, | |
42 | .type = CLK_TYPE_PERIPHERAL, | |
43 | }; | |
44 | static struct clk pioB_clk = { | |
45 | .name = "pioB_clk", | |
46 | .pmc_mask = 1 << AT91SAM9RL_ID_PIOB, | |
47 | .type = CLK_TYPE_PERIPHERAL, | |
48 | }; | |
49 | static struct clk pioC_clk = { | |
50 | .name = "pioC_clk", | |
51 | .pmc_mask = 1 << AT91SAM9RL_ID_PIOC, | |
52 | .type = CLK_TYPE_PERIPHERAL, | |
53 | }; | |
54 | static struct clk pioD_clk = { | |
55 | .name = "pioD_clk", | |
56 | .pmc_mask = 1 << AT91SAM9RL_ID_PIOD, | |
57 | .type = CLK_TYPE_PERIPHERAL, | |
58 | }; | |
59 | static struct clk usart0_clk = { | |
60 | .name = "usart0_clk", | |
61 | .pmc_mask = 1 << AT91SAM9RL_ID_US0, | |
62 | .type = CLK_TYPE_PERIPHERAL, | |
63 | }; | |
64 | static struct clk usart1_clk = { | |
65 | .name = "usart1_clk", | |
66 | .pmc_mask = 1 << AT91SAM9RL_ID_US1, | |
67 | .type = CLK_TYPE_PERIPHERAL, | |
68 | }; | |
69 | static struct clk usart2_clk = { | |
70 | .name = "usart2_clk", | |
71 | .pmc_mask = 1 << AT91SAM9RL_ID_US2, | |
72 | .type = CLK_TYPE_PERIPHERAL, | |
73 | }; | |
74 | static struct clk usart3_clk = { | |
75 | .name = "usart3_clk", | |
76 | .pmc_mask = 1 << AT91SAM9RL_ID_US3, | |
77 | .type = CLK_TYPE_PERIPHERAL, | |
78 | }; | |
79 | static struct clk mmc_clk = { | |
80 | .name = "mci_clk", | |
81 | .pmc_mask = 1 << AT91SAM9RL_ID_MCI, | |
82 | .type = CLK_TYPE_PERIPHERAL, | |
83 | }; | |
84 | static struct clk twi0_clk = { | |
85 | .name = "twi0_clk", | |
86 | .pmc_mask = 1 << AT91SAM9RL_ID_TWI0, | |
87 | .type = CLK_TYPE_PERIPHERAL, | |
88 | }; | |
89 | static struct clk twi1_clk = { | |
90 | .name = "twi1_clk", | |
91 | .pmc_mask = 1 << AT91SAM9RL_ID_TWI1, | |
92 | .type = CLK_TYPE_PERIPHERAL, | |
93 | }; | |
94 | static struct clk spi_clk = { | |
95 | .name = "spi_clk", | |
96 | .pmc_mask = 1 << AT91SAM9RL_ID_SPI, | |
97 | .type = CLK_TYPE_PERIPHERAL, | |
98 | }; | |
99 | static struct clk ssc0_clk = { | |
100 | .name = "ssc0_clk", | |
101 | .pmc_mask = 1 << AT91SAM9RL_ID_SSC0, | |
102 | .type = CLK_TYPE_PERIPHERAL, | |
103 | }; | |
104 | static struct clk ssc1_clk = { | |
105 | .name = "ssc1_clk", | |
106 | .pmc_mask = 1 << AT91SAM9RL_ID_SSC1, | |
107 | .type = CLK_TYPE_PERIPHERAL, | |
108 | }; | |
109 | static struct clk tc0_clk = { | |
110 | .name = "tc0_clk", | |
111 | .pmc_mask = 1 << AT91SAM9RL_ID_TC0, | |
112 | .type = CLK_TYPE_PERIPHERAL, | |
113 | }; | |
114 | static struct clk tc1_clk = { | |
115 | .name = "tc1_clk", | |
116 | .pmc_mask = 1 << AT91SAM9RL_ID_TC1, | |
117 | .type = CLK_TYPE_PERIPHERAL, | |
118 | }; | |
119 | static struct clk tc2_clk = { | |
120 | .name = "tc2_clk", | |
121 | .pmc_mask = 1 << AT91SAM9RL_ID_TC2, | |
122 | .type = CLK_TYPE_PERIPHERAL, | |
123 | }; | |
bb1ad68b AV |
124 | static struct clk pwm_clk = { |
125 | .name = "pwm_clk", | |
877d7720 AV |
126 | .pmc_mask = 1 << AT91SAM9RL_ID_PWMC, |
127 | .type = CLK_TYPE_PERIPHERAL, | |
128 | }; | |
129 | static struct clk tsc_clk = { | |
130 | .name = "tsc_clk", | |
131 | .pmc_mask = 1 << AT91SAM9RL_ID_TSC, | |
132 | .type = CLK_TYPE_PERIPHERAL, | |
133 | }; | |
134 | static struct clk dma_clk = { | |
135 | .name = "dma_clk", | |
136 | .pmc_mask = 1 << AT91SAM9RL_ID_DMA, | |
137 | .type = CLK_TYPE_PERIPHERAL, | |
138 | }; | |
139 | static struct clk udphs_clk = { | |
140 | .name = "udphs_clk", | |
141 | .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS, | |
142 | .type = CLK_TYPE_PERIPHERAL, | |
143 | }; | |
144 | static struct clk lcdc_clk = { | |
145 | .name = "lcdc_clk", | |
146 | .pmc_mask = 1 << AT91SAM9RL_ID_LCDC, | |
147 | .type = CLK_TYPE_PERIPHERAL, | |
148 | }; | |
149 | static struct clk ac97_clk = { | |
150 | .name = "ac97_clk", | |
151 | .pmc_mask = 1 << AT91SAM9RL_ID_AC97C, | |
152 | .type = CLK_TYPE_PERIPHERAL, | |
153 | }; | |
154 | ||
155 | static struct clk *periph_clocks[] __initdata = { | |
156 | &pioA_clk, | |
157 | &pioB_clk, | |
158 | &pioC_clk, | |
159 | &pioD_clk, | |
160 | &usart0_clk, | |
161 | &usart1_clk, | |
162 | &usart2_clk, | |
163 | &usart3_clk, | |
164 | &mmc_clk, | |
165 | &twi0_clk, | |
166 | &twi1_clk, | |
167 | &spi_clk, | |
168 | &ssc0_clk, | |
169 | &ssc1_clk, | |
170 | &tc0_clk, | |
171 | &tc1_clk, | |
172 | &tc2_clk, | |
bb1ad68b | 173 | &pwm_clk, |
877d7720 AV |
174 | &tsc_clk, |
175 | &dma_clk, | |
176 | &udphs_clk, | |
177 | &lcdc_clk, | |
178 | &ac97_clk, | |
179 | // irq0 | |
180 | }; | |
181 | ||
bd602995 | 182 | static struct clk_lookup periph_clocks_lookups[] = { |
bbd44f6b | 183 | CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk), |
9d87159e JCPV |
184 | CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), |
185 | CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), | |
bd602995 JCPV |
186 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), |
187 | CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), | |
188 | CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), | |
636036d2 BS |
189 | CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk), |
190 | CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk), | |
099343c6 BS |
191 | CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk), |
192 | CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk), | |
fac368a0 NV |
193 | CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk), |
194 | CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk), | |
619d4a4b JCPV |
195 | CLKDEV_CON_ID("pioA", &pioA_clk), |
196 | CLKDEV_CON_ID("pioB", &pioB_clk), | |
197 | CLKDEV_CON_ID("pioC", &pioC_clk), | |
198 | CLKDEV_CON_ID("pioD", &pioD_clk), | |
bd602995 JCPV |
199 | }; |
200 | ||
201 | static struct clk_lookup usart_clocks_lookups[] = { | |
202 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), | |
203 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), | |
204 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), | |
205 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), | |
206 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk), | |
207 | }; | |
208 | ||
877d7720 AV |
209 | /* |
210 | * The two programmable clocks. | |
211 | * You must configure pin multiplexing to bring these signals out. | |
212 | */ | |
213 | static struct clk pck0 = { | |
214 | .name = "pck0", | |
215 | .pmc_mask = AT91_PMC_PCK0, | |
216 | .type = CLK_TYPE_PROGRAMMABLE, | |
217 | .id = 0, | |
218 | }; | |
219 | static struct clk pck1 = { | |
220 | .name = "pck1", | |
221 | .pmc_mask = AT91_PMC_PCK1, | |
222 | .type = CLK_TYPE_PROGRAMMABLE, | |
223 | .id = 1, | |
224 | }; | |
225 | ||
226 | static void __init at91sam9rl_register_clocks(void) | |
227 | { | |
228 | int i; | |
229 | ||
230 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) | |
231 | clk_register(periph_clocks[i]); | |
232 | ||
bd602995 JCPV |
233 | clkdev_add_table(periph_clocks_lookups, |
234 | ARRAY_SIZE(periph_clocks_lookups)); | |
235 | clkdev_add_table(usart_clocks_lookups, | |
236 | ARRAY_SIZE(usart_clocks_lookups)); | |
237 | ||
877d7720 AV |
238 | clk_register(&pck0); |
239 | clk_register(&pck1); | |
240 | } | |
241 | ||
242 | /* -------------------------------------------------------------------- | |
243 | * GPIO | |
244 | * -------------------------------------------------------------------- */ | |
245 | ||
1a2d9156 | 246 | static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = { |
877d7720 AV |
247 | { |
248 | .id = AT91SAM9RL_ID_PIOA, | |
80e91cb8 | 249 | .regbase = AT91SAM9RL_BASE_PIOA, |
877d7720 AV |
250 | }, { |
251 | .id = AT91SAM9RL_ID_PIOB, | |
80e91cb8 | 252 | .regbase = AT91SAM9RL_BASE_PIOB, |
877d7720 AV |
253 | }, { |
254 | .id = AT91SAM9RL_ID_PIOC, | |
80e91cb8 | 255 | .regbase = AT91SAM9RL_BASE_PIOC, |
877d7720 AV |
256 | }, { |
257 | .id = AT91SAM9RL_ID_PIOD, | |
80e91cb8 | 258 | .regbase = AT91SAM9RL_BASE_PIOD, |
877d7720 AV |
259 | } |
260 | }; | |
261 | ||
877d7720 AV |
262 | /* -------------------------------------------------------------------- |
263 | * AT91SAM9RL processor initialization | |
264 | * -------------------------------------------------------------------- */ | |
265 | ||
21d08b9d | 266 | static void __init at91sam9rl_map_io(void) |
877d7720 | 267 | { |
8c3583b6 | 268 | unsigned long sram_size; |
877d7720 | 269 | |
8c3583b6 | 270 | switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) { |
877d7720 AV |
271 | case AT91_CIDR_SRAMSIZ_32K: |
272 | sram_size = 2 * SZ_16K; | |
273 | break; | |
274 | case AT91_CIDR_SRAMSIZ_16K: | |
275 | default: | |
276 | sram_size = SZ_16K; | |
277 | } | |
278 | ||
877d7720 | 279 | /* Map SRAM */ |
f0051d82 | 280 | at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size); |
1b021a3b | 281 | } |
877d7720 | 282 | |
cfa5a1fe JCPV |
283 | static void __init at91sam9rl_ioremap_registers(void) |
284 | { | |
f22deee5 | 285 | at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC); |
e9f68b5c | 286 | at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC); |
f363c407 | 287 | at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512); |
4ab0c599 | 288 | at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); |
faee0cc3 | 289 | at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); |
4342d647 | 290 | at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX); |
6b625891 | 291 | at91_pm_set_standby(at91sam9_sdram_standby); |
cfa5a1fe JCPV |
292 | } |
293 | ||
46539374 | 294 | static void __init at91sam9rl_initialize(void) |
1b021a3b | 295 | { |
0d781716 | 296 | arm_pm_idle = at91sam9_idle; |
1b2073e7 | 297 | arm_pm_restart = at91sam9_alt_restart; |
877d7720 | 298 | |
6de714c2 | 299 | at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC); |
94c4c79f | 300 | at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT); |
6de714c2 | 301 | |
877d7720 AV |
302 | /* Register GPIO subsystem */ |
303 | at91_gpio_init(at91sam9rl_gpio, 4); | |
304 | } | |
305 | ||
306 | /* -------------------------------------------------------------------- | |
307 | * Interrupt initialization | |
308 | * -------------------------------------------------------------------- */ | |
309 | ||
310 | /* | |
311 | * The default interrupt priority levels (0 = lowest, 7 = highest). | |
312 | */ | |
313 | static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { | |
314 | 7, /* Advanced Interrupt Controller */ | |
315 | 7, /* System Peripherals */ | |
316 | 1, /* Parallel IO Controller A */ | |
317 | 1, /* Parallel IO Controller B */ | |
318 | 1, /* Parallel IO Controller C */ | |
319 | 1, /* Parallel IO Controller D */ | |
320 | 5, /* USART 0 */ | |
321 | 5, /* USART 1 */ | |
322 | 5, /* USART 2 */ | |
323 | 5, /* USART 3 */ | |
324 | 0, /* Multimedia Card Interface */ | |
325 | 6, /* Two-Wire Interface 0 */ | |
326 | 6, /* Two-Wire Interface 1 */ | |
327 | 5, /* Serial Peripheral Interface */ | |
328 | 4, /* Serial Synchronous Controller 0 */ | |
329 | 4, /* Serial Synchronous Controller 1 */ | |
330 | 0, /* Timer Counter 0 */ | |
331 | 0, /* Timer Counter 1 */ | |
332 | 0, /* Timer Counter 2 */ | |
333 | 0, | |
334 | 0, /* Touch Screen Controller */ | |
335 | 0, /* DMA Controller */ | |
336 | 2, /* USB Device High speed port */ | |
337 | 2, /* LCD Controller */ | |
338 | 6, /* AC97 Controller */ | |
339 | 0, | |
340 | 0, | |
341 | 0, | |
342 | 0, | |
343 | 0, | |
344 | 0, | |
345 | 0, /* Advanced Interrupt Controller */ | |
346 | }; | |
347 | ||
84ddb087 | 348 | AT91_SOC_START(at91sam9rl) |
21d08b9d | 349 | .map_io = at91sam9rl_map_io, |
92100c12 | 350 | .default_irq_priority = at91sam9rl_default_irq_priority, |
546c830c | 351 | .extern_irq = (1 << AT91SAM9RL_ID_IRQ0), |
cfa5a1fe | 352 | .ioremap_registers = at91sam9rl_ioremap_registers, |
51ddec76 | 353 | .register_clocks = at91sam9rl_register_clocks, |
21d08b9d | 354 | .init = at91sam9rl_initialize, |
8d39e0fd | 355 | AT91_SOC_END |