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b3ed3a17 | 1 | /* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h |
c8bef140 | 2 | * |
b3ed3a17 KK |
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
c8bef140 | 5 | * |
b3ed3a17 | 6 | * EXYNOS4 - Clock register definitions |
c8bef140 CY |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_ARCH_REGS_CLOCK_H | |
14 | #define __ASM_ARCH_REGS_CLOCK_H __FILE__ | |
15 | ||
2bc02c0d | 16 | #include <plat/cpu.h> |
c8bef140 CY |
17 | #include <mach/map.h> |
18 | ||
a855039e KK |
19 | #define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x)) |
20 | ||
21 | #define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500) | |
22 | #define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600) | |
23 | #define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800) | |
24 | ||
25 | #define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500) | |
26 | #define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600) | |
27 | #define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800) | |
28 | ||
29 | #define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010) | |
30 | #define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020) | |
31 | ||
32 | #define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110) | |
33 | #define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114) | |
34 | #define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120) | |
35 | #define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124) | |
36 | ||
37 | #define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210) | |
38 | #define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214) | |
39 | #define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220) | |
40 | #define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224) | |
41 | #define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228) | |
42 | #define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C) | |
43 | #define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230) | |
44 | #define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234) | |
45 | #define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C) | |
46 | #define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240) | |
47 | #define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250) | |
48 | #define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254) | |
49 | ||
50 | #define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310) | |
51 | #define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320) | |
52 | #define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324) | |
53 | #define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334) | |
54 | #define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C) | |
55 | #define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340) | |
56 | #define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350) | |
57 | #define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354) | |
58 | ||
59 | #define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510) | |
60 | #define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520) | |
61 | #define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524) | |
62 | #define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528) | |
63 | #define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C) | |
64 | #define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530) | |
65 | #define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534) | |
66 | #define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C) | |
67 | #define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540) | |
68 | #define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544) | |
69 | #define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548) | |
70 | #define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C) | |
71 | #define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550) | |
72 | #define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554) | |
73 | #define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558) | |
74 | #define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C) | |
75 | #define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560) | |
76 | #define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564) | |
77 | #define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580) | |
78 | ||
79 | #define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610) | |
44b2cef5 | 80 | #define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628) |
a855039e KK |
81 | |
82 | #define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820) | |
83 | #define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920) | |
84 | #define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924) | |
85 | #define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928) | |
86 | #define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C) | |
87 | #define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ | |
88 | EXYNOS_CLKREG(0x0C930) : \ | |
89 | EXYNOS_CLKREG(0x04930)) | |
90 | #define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930) | |
91 | #define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930) | |
92 | #define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934) | |
93 | #define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940) | |
94 | #define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C) | |
95 | #define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950) | |
96 | #define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ | |
97 | EXYNOS_CLKREG(0x0C960) : \ | |
98 | EXYNOS_CLKREG(0x08960)) | |
99 | #define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960) | |
100 | #define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960) | |
101 | #define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970) | |
102 | ||
103 | #define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300) | |
104 | #define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200) | |
105 | #define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500) | |
106 | #define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504) | |
107 | #define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600) | |
44b2cef5 | 108 | #define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604) |
a855039e KK |
109 | #define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900) |
110 | ||
44b2cef5 MH |
111 | #define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094) |
112 | #define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0) | |
113 | ||
a855039e KK |
114 | #define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000) |
115 | #define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \ | |
116 | EXYNOS_CLKREG(0x14004) : \ | |
117 | EXYNOS_CLKREG(0x10008)) | |
118 | #define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100) | |
119 | #define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104) | |
120 | #define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \ | |
121 | EXYNOS_CLKREG(0x14108) : \ | |
122 | EXYNOS_CLKREG(0x10108)) | |
123 | #define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \ | |
124 | EXYNOS_CLKREG(0x1410C) : \ | |
125 | EXYNOS_CLKREG(0x1010C)) | |
126 | ||
127 | #define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200) | |
128 | #define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400) | |
129 | ||
130 | #define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500) | |
131 | #define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504) | |
132 | #define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600) | |
133 | #define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604) | |
134 | ||
135 | #define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800) | |
136 | #define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900) | |
137 | ||
bca10b90 KC |
138 | #define EXYNOS4_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x18800) |
139 | #define EXYNOS4_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x18804) | |
140 | ||
a855039e KK |
141 | #define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */ |
142 | ||
143 | #define EXYNOS4_APLLCON0_ENABLE_SHIFT (31) | |
144 | #define EXYNOS4_APLLCON0_LOCKED_SHIFT (29) | |
145 | #define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) | |
146 | #define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) | |
147 | ||
148 | #define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31) | |
149 | #define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) | |
150 | ||
151 | #define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31) | |
152 | #define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) | |
153 | ||
154 | #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) | |
155 | #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) | |
156 | ||
157 | #define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0) | |
158 | #define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) | |
159 | #define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4) | |
160 | #define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) | |
161 | #define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8) | |
162 | #define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) | |
163 | #define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12) | |
164 | #define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) | |
165 | #define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16) | |
166 | #define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) | |
167 | #define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20) | |
168 | #define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) | |
169 | #define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24) | |
170 | #define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) | |
d074de8e JL |
171 | #define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28 |
172 | #define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT) | |
173 | ||
174 | #define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0 | |
175 | #define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) | |
176 | #define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4 | |
177 | #define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) | |
178 | #define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8 | |
179 | #define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT) | |
a855039e KK |
180 | |
181 | #define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) | |
182 | #define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) | |
183 | #define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4) | |
184 | #define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) | |
185 | #define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8) | |
186 | #define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) | |
187 | #define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12) | |
188 | #define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) | |
189 | #define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16) | |
190 | #define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) | |
191 | #define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20) | |
192 | #define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) | |
193 | #define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24) | |
194 | #define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) | |
195 | #define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28) | |
196 | #define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT) | |
197 | ||
44b2cef5 MH |
198 | #define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0) |
199 | #define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) | |
200 | #define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4) | |
201 | #define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) | |
202 | #define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8) | |
203 | #define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT) | |
204 | #define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12) | |
205 | #define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT) | |
206 | #define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16) | |
207 | #define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT) | |
208 | #define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24) | |
209 | #define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT) | |
210 | ||
211 | #define EXYNOS4_CLKDIV_MFC_SHIFT (0) | |
212 | #define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT) | |
213 | ||
a855039e KK |
214 | #define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0) |
215 | #define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) | |
216 | #define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4) | |
217 | #define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) | |
218 | #define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8) | |
219 | #define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) | |
220 | #define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12) | |
221 | #define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) | |
222 | #define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16) | |
223 | #define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT) | |
44b2cef5 MH |
224 | #define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20) |
225 | #define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) | |
226 | #define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24) | |
227 | #define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT) | |
a855039e KK |
228 | |
229 | #define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0) | |
230 | #define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | |
231 | #define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4) | |
232 | #define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT) | |
7af36b97 | 233 | |
44b2cef5 MH |
234 | #define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0) |
235 | #define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) | |
236 | #define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4) | |
237 | #define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) | |
238 | #define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8) | |
239 | #define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) | |
240 | #define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12) | |
241 | #define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT) | |
242 | ||
2bc02c0d KK |
243 | /* Only for EXYNOS4210 */ |
244 | ||
a855039e KK |
245 | #define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238) |
246 | #define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338) | |
247 | #define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538) | |
248 | #define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938) | |
2bc02c0d | 249 | |
44b2cef5 MH |
250 | /* Only for EXYNOS4212 */ |
251 | ||
252 | #define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568) | |
253 | ||
254 | #define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668) | |
255 | ||
256 | #define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) | |
257 | #define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) | |
258 | ||
87b3c6ef KK |
259 | /* For EXYNOS5250 */ |
260 | ||
32db797f | 261 | #define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000) |
87b3c6ef KK |
262 | #define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100) |
263 | #define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200) | |
32db797f | 264 | #define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400) |
87b3c6ef | 265 | #define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500) |
32db797f JC |
266 | #define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504) |
267 | #define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600) | |
268 | #define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604) | |
269 | ||
87b3c6ef KK |
270 | #define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100) |
271 | #define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204) | |
272 | ||
273 | #define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900) | |
274 | ||
275 | #define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500) | |
276 | ||
277 | #define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218) | |
278 | #define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130) | |
279 | #define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134) | |
280 | #define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140) | |
281 | #define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144) | |
282 | #define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120) | |
283 | ||
284 | #define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210) | |
285 | #define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C) | |
286 | #define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220) | |
287 | #define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C) | |
288 | #define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244) | |
289 | #define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250) | |
290 | ||
291 | #define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310) | |
292 | #define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320) | |
293 | #define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C) | |
294 | #define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340) | |
295 | #define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350) | |
296 | ||
297 | #define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510) | |
298 | #define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514) | |
299 | #define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520) | |
300 | #define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C) | |
301 | #define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C) | |
302 | #define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548) | |
303 | #define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C) | |
304 | #define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550) | |
305 | #define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554) | |
306 | #define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558) | |
307 | ||
308 | #define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800) | |
bca10b90 KC |
309 | #define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800) |
310 | #define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804) | |
87b3c6ef KK |
311 | #define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920) |
312 | #define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928) | |
313 | #define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C) | |
314 | #define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934) | |
315 | #define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944) | |
316 | #define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C) | |
317 | #define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950) | |
318 | #define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960) | |
319 | #define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980) | |
320 | ||
321 | #define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110) | |
322 | #define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) | |
323 | #define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) | |
324 | ||
325 | #define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030) | |
326 | ||
327 | #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) | |
328 | ||
1d45ac49 SN |
329 | /* Compatibility defines and inclusion */ |
330 | ||
331 | #include <mach/regs-pmu.h> | |
d4b34c6c | 332 | |
a855039e | 333 | #define S5P_EPLL_CON EXYNOS4_EPLL_CON0 |
d4b34c6c | 334 | |
c8bef140 | 335 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ |