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Commit | Line | Data |
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4bbbc1ad JY |
1 | /* |
2 | * GPMC support functions | |
3 | * | |
4 | * Copyright (C) 2005-2006 Nokia Corporation | |
5 | * | |
6 | * Author: Juha Yrjola | |
7 | * | |
44169075 SS |
8 | * Copyright (C) 2009 Texas Instruments |
9 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
10 | * | |
4bbbc1ad JY |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
fd1dc87d PW |
15 | #undef DEBUG |
16 | ||
4bbbc1ad JY |
17 | #include <linux/kernel.h> |
18 | #include <linux/init.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/clk.h> | |
f37e4580 ID |
21 | #include <linux/ioport.h> |
22 | #include <linux/spinlock.h> | |
fced80c7 | 23 | #include <linux/io.h> |
fd1dc87d | 24 | #include <linux/module.h> |
4bbbc1ad | 25 | |
7f245162 | 26 | #include <asm/mach-types.h> |
ce491cf8 | 27 | #include <plat/gpmc.h> |
4bbbc1ad | 28 | |
ce491cf8 | 29 | #include <plat/sdrc.h> |
72d0f1c3 | 30 | |
fd1dc87d | 31 | /* GPMC register offsets */ |
4bbbc1ad JY |
32 | #define GPMC_REVISION 0x00 |
33 | #define GPMC_SYSCONFIG 0x10 | |
34 | #define GPMC_SYSSTATUS 0x14 | |
35 | #define GPMC_IRQSTATUS 0x18 | |
36 | #define GPMC_IRQENABLE 0x1c | |
37 | #define GPMC_TIMEOUT_CONTROL 0x40 | |
38 | #define GPMC_ERR_ADDRESS 0x44 | |
39 | #define GPMC_ERR_TYPE 0x48 | |
40 | #define GPMC_CONFIG 0x50 | |
41 | #define GPMC_STATUS 0x54 | |
42 | #define GPMC_PREFETCH_CONFIG1 0x1e0 | |
43 | #define GPMC_PREFETCH_CONFIG2 0x1e4 | |
15e02a3b | 44 | #define GPMC_PREFETCH_CONTROL 0x1ec |
4bbbc1ad JY |
45 | #define GPMC_PREFETCH_STATUS 0x1f0 |
46 | #define GPMC_ECC_CONFIG 0x1f4 | |
47 | #define GPMC_ECC_CONTROL 0x1f8 | |
48 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | |
49 | ||
50 | #define GPMC_CS0 0x60 | |
51 | #define GPMC_CS_SIZE 0x30 | |
52 | ||
f37e4580 ID |
53 | #define GPMC_MEM_START 0x00000000 |
54 | #define GPMC_MEM_END 0x3FFFFFFF | |
55 | #define BOOT_ROM_SPACE 0x100000 /* 1MB */ | |
56 | ||
57 | #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ | |
58 | #define GPMC_SECTION_SHIFT 28 /* 128 MB */ | |
59 | ||
59e9c5ae | 60 | #define PREFETCH_FIFOTHRESHOLD (0x40 << 8) |
61 | #define CS_NUM_SHIFT 24 | |
62 | #define ENABLE_PREFETCH (0x1 << 7) | |
63 | #define DMA_MPU_MODE 2 | |
64 | ||
a2d3e7ba RN |
65 | /* Structure to save gpmc cs context */ |
66 | struct gpmc_cs_config { | |
67 | u32 config1; | |
68 | u32 config2; | |
69 | u32 config3; | |
70 | u32 config4; | |
71 | u32 config5; | |
72 | u32 config6; | |
73 | u32 config7; | |
74 | int is_valid; | |
75 | }; | |
76 | ||
77 | /* | |
78 | * Structure to save/restore gpmc context | |
79 | * to support core off on OMAP3 | |
80 | */ | |
81 | struct omap3_gpmc_regs { | |
82 | u32 sysconfig; | |
83 | u32 irqenable; | |
84 | u32 timeout_ctrl; | |
85 | u32 config; | |
86 | u32 prefetch_config1; | |
87 | u32 prefetch_config2; | |
88 | u32 prefetch_control; | |
89 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; | |
90 | }; | |
91 | ||
f37e4580 ID |
92 | static struct resource gpmc_mem_root; |
93 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; | |
87b247c4 | 94 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
f37e4580 ID |
95 | static unsigned gpmc_cs_map; |
96 | ||
fd1dc87d | 97 | static void __iomem *gpmc_base; |
4bbbc1ad | 98 | |
fd1dc87d | 99 | static struct clk *gpmc_l3_clk; |
4bbbc1ad JY |
100 | |
101 | static void gpmc_write_reg(int idx, u32 val) | |
102 | { | |
103 | __raw_writel(val, gpmc_base + idx); | |
104 | } | |
105 | ||
106 | static u32 gpmc_read_reg(int idx) | |
107 | { | |
108 | return __raw_readl(gpmc_base + idx); | |
109 | } | |
110 | ||
111 | void gpmc_cs_write_reg(int cs, int idx, u32 val) | |
112 | { | |
113 | void __iomem *reg_addr; | |
114 | ||
fd1dc87d | 115 | reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx; |
4bbbc1ad JY |
116 | __raw_writel(val, reg_addr); |
117 | } | |
118 | ||
119 | u32 gpmc_cs_read_reg(int cs, int idx) | |
120 | { | |
fd1dc87d PW |
121 | void __iomem *reg_addr; |
122 | ||
123 | reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx; | |
124 | return __raw_readl(reg_addr); | |
4bbbc1ad JY |
125 | } |
126 | ||
fd1dc87d | 127 | /* TODO: Add support for gpmc_fck to clock framework and use it */ |
1c22cc13 | 128 | unsigned long gpmc_get_fclk_period(void) |
4bbbc1ad | 129 | { |
fd1dc87d PW |
130 | unsigned long rate = clk_get_rate(gpmc_l3_clk); |
131 | ||
132 | if (rate == 0) { | |
133 | printk(KERN_WARNING "gpmc_l3_clk not enabled\n"); | |
134 | return 0; | |
135 | } | |
136 | ||
137 | rate /= 1000; | |
138 | rate = 1000000000 / rate; /* In picoseconds */ | |
139 | ||
140 | return rate; | |
4bbbc1ad JY |
141 | } |
142 | ||
143 | unsigned int gpmc_ns_to_ticks(unsigned int time_ns) | |
144 | { | |
145 | unsigned long tick_ps; | |
146 | ||
147 | /* Calculate in picosecs to yield more exact results */ | |
148 | tick_ps = gpmc_get_fclk_period(); | |
149 | ||
150 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | |
151 | } | |
152 | ||
fd1dc87d PW |
153 | unsigned int gpmc_ticks_to_ns(unsigned int ticks) |
154 | { | |
155 | return ticks * gpmc_get_fclk_period() / 1000; | |
156 | } | |
157 | ||
23300597 KS |
158 | unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) |
159 | { | |
160 | unsigned long ticks = gpmc_ns_to_ticks(time_ns); | |
161 | ||
162 | return ticks * gpmc_get_fclk_period() / 1000; | |
163 | } | |
164 | ||
4bbbc1ad JY |
165 | #ifdef DEBUG |
166 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
2aab6468 | 167 | int time, const char *name) |
4bbbc1ad JY |
168 | #else |
169 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
170 | int time) | |
171 | #endif | |
172 | { | |
173 | u32 l; | |
174 | int ticks, mask, nr_bits; | |
175 | ||
176 | if (time == 0) | |
177 | ticks = 0; | |
178 | else | |
179 | ticks = gpmc_ns_to_ticks(time); | |
180 | nr_bits = end_bit - st_bit + 1; | |
1c22cc13 DB |
181 | if (ticks >= 1 << nr_bits) { |
182 | #ifdef DEBUG | |
183 | printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n", | |
184 | cs, name, time, ticks, 1 << nr_bits); | |
185 | #endif | |
4bbbc1ad | 186 | return -1; |
1c22cc13 | 187 | } |
4bbbc1ad JY |
188 | |
189 | mask = (1 << nr_bits) - 1; | |
190 | l = gpmc_cs_read_reg(cs, reg); | |
191 | #ifdef DEBUG | |
1c22cc13 DB |
192 | printk(KERN_INFO |
193 | "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", | |
2aab6468 | 194 | cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000, |
1c22cc13 | 195 | (l >> st_bit) & mask, time); |
4bbbc1ad JY |
196 | #endif |
197 | l &= ~(mask << st_bit); | |
198 | l |= ticks << st_bit; | |
199 | gpmc_cs_write_reg(cs, reg, l); | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | #ifdef DEBUG | |
205 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
206 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ | |
207 | t->field, #field) < 0) \ | |
208 | return -1 | |
209 | #else | |
210 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
211 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \ | |
212 | return -1 | |
213 | #endif | |
214 | ||
215 | int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) | |
216 | { | |
217 | int div; | |
218 | u32 l; | |
219 | ||
220 | l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1); | |
221 | div = l / gpmc_get_fclk_period(); | |
222 | if (div > 4) | |
223 | return -1; | |
1c22cc13 | 224 | if (div <= 0) |
4bbbc1ad JY |
225 | div = 1; |
226 | ||
227 | return div; | |
228 | } | |
229 | ||
230 | int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) | |
231 | { | |
232 | int div; | |
233 | u32 l; | |
234 | ||
235 | div = gpmc_cs_calc_divider(cs, t->sync_clk); | |
236 | if (div < 0) | |
237 | return -1; | |
238 | ||
239 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); | |
240 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); | |
241 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); | |
242 | ||
243 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); | |
244 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); | |
245 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); | |
246 | ||
247 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); | |
248 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); | |
249 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); | |
250 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); | |
251 | ||
252 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); | |
253 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); | |
254 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); | |
255 | ||
256 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); | |
257 | ||
cc26b3b0 SMK |
258 | if (cpu_is_omap34xx()) { |
259 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); | |
260 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); | |
261 | } | |
262 | ||
1c22cc13 DB |
263 | /* caller is expected to have initialized CONFIG1 to cover |
264 | * at least sync vs async | |
265 | */ | |
266 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
267 | if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) { | |
4bbbc1ad | 268 | #ifdef DEBUG |
1c22cc13 DB |
269 | printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n", |
270 | cs, (div * gpmc_get_fclk_period()) / 1000, div); | |
4bbbc1ad | 271 | #endif |
1c22cc13 DB |
272 | l &= ~0x03; |
273 | l |= (div - 1); | |
274 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); | |
275 | } | |
4bbbc1ad JY |
276 | |
277 | return 0; | |
278 | } | |
279 | ||
f37e4580 ID |
280 | static void gpmc_cs_enable_mem(int cs, u32 base, u32 size) |
281 | { | |
282 | u32 l; | |
283 | u32 mask; | |
284 | ||
285 | mask = (1 << GPMC_SECTION_SHIFT) - size; | |
286 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
287 | l &= ~0x3f; | |
288 | l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; | |
289 | l &= ~(0x0f << 8); | |
290 | l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; | |
a2d3e7ba | 291 | l |= GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
292 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
293 | } | |
294 | ||
295 | static void gpmc_cs_disable_mem(int cs) | |
296 | { | |
297 | u32 l; | |
298 | ||
299 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 300 | l &= ~GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
301 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
302 | } | |
303 | ||
304 | static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) | |
305 | { | |
306 | u32 l; | |
307 | u32 mask; | |
308 | ||
309 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
310 | *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; | |
311 | mask = (l >> 8) & 0x0f; | |
312 | *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); | |
313 | } | |
314 | ||
315 | static int gpmc_cs_mem_enabled(int cs) | |
316 | { | |
317 | u32 l; | |
318 | ||
319 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 320 | return l & GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
321 | } |
322 | ||
c40fae95 | 323 | int gpmc_cs_set_reserved(int cs, int reserved) |
4bbbc1ad | 324 | { |
c40fae95 TL |
325 | if (cs > GPMC_CS_NUM) |
326 | return -ENODEV; | |
327 | ||
f37e4580 ID |
328 | gpmc_cs_map &= ~(1 << cs); |
329 | gpmc_cs_map |= (reserved ? 1 : 0) << cs; | |
c40fae95 TL |
330 | |
331 | return 0; | |
f37e4580 ID |
332 | } |
333 | ||
c40fae95 | 334 | int gpmc_cs_reserved(int cs) |
f37e4580 | 335 | { |
c40fae95 TL |
336 | if (cs > GPMC_CS_NUM) |
337 | return -ENODEV; | |
338 | ||
f37e4580 ID |
339 | return gpmc_cs_map & (1 << cs); |
340 | } | |
341 | ||
342 | static unsigned long gpmc_mem_align(unsigned long size) | |
343 | { | |
344 | int order; | |
345 | ||
346 | size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); | |
347 | order = GPMC_CHUNK_SHIFT - 1; | |
348 | do { | |
349 | size >>= 1; | |
350 | order++; | |
351 | } while (size); | |
352 | size = 1 << order; | |
353 | return size; | |
354 | } | |
355 | ||
356 | static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) | |
357 | { | |
358 | struct resource *res = &gpmc_cs_mem[cs]; | |
359 | int r; | |
360 | ||
361 | size = gpmc_mem_align(size); | |
362 | spin_lock(&gpmc_mem_lock); | |
363 | res->start = base; | |
364 | res->end = base + size - 1; | |
365 | r = request_resource(&gpmc_mem_root, res); | |
366 | spin_unlock(&gpmc_mem_lock); | |
367 | ||
368 | return r; | |
369 | } | |
370 | ||
371 | int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) | |
372 | { | |
373 | struct resource *res = &gpmc_cs_mem[cs]; | |
374 | int r = -1; | |
375 | ||
376 | if (cs > GPMC_CS_NUM) | |
377 | return -ENODEV; | |
378 | ||
379 | size = gpmc_mem_align(size); | |
380 | if (size > (1 << GPMC_SECTION_SHIFT)) | |
381 | return -ENOMEM; | |
382 | ||
383 | spin_lock(&gpmc_mem_lock); | |
384 | if (gpmc_cs_reserved(cs)) { | |
385 | r = -EBUSY; | |
386 | goto out; | |
387 | } | |
388 | if (gpmc_cs_mem_enabled(cs)) | |
389 | r = adjust_resource(res, res->start & ~(size - 1), size); | |
390 | if (r < 0) | |
391 | r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, | |
392 | size, NULL, NULL); | |
393 | if (r < 0) | |
394 | goto out; | |
395 | ||
6d135242 | 396 | gpmc_cs_enable_mem(cs, res->start, resource_size(res)); |
f37e4580 ID |
397 | *base = res->start; |
398 | gpmc_cs_set_reserved(cs, 1); | |
399 | out: | |
400 | spin_unlock(&gpmc_mem_lock); | |
401 | return r; | |
402 | } | |
fd1dc87d | 403 | EXPORT_SYMBOL(gpmc_cs_request); |
f37e4580 ID |
404 | |
405 | void gpmc_cs_free(int cs) | |
406 | { | |
407 | spin_lock(&gpmc_mem_lock); | |
e7fdc605 | 408 | if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) { |
f37e4580 ID |
409 | printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); |
410 | BUG(); | |
411 | spin_unlock(&gpmc_mem_lock); | |
412 | return; | |
413 | } | |
414 | gpmc_cs_disable_mem(cs); | |
415 | release_resource(&gpmc_cs_mem[cs]); | |
416 | gpmc_cs_set_reserved(cs, 0); | |
417 | spin_unlock(&gpmc_mem_lock); | |
418 | } | |
fd1dc87d | 419 | EXPORT_SYMBOL(gpmc_cs_free); |
f37e4580 | 420 | |
59e9c5ae | 421 | /** |
422 | * gpmc_prefetch_enable - configures and starts prefetch transfer | |
423 | * @cs: nand cs (chip select) number | |
424 | * @dma_mode: dma mode enable (1) or disable (0) | |
425 | * @u32_count: number of bytes to be transferred | |
426 | * @is_write: prefetch read(0) or write post(1) mode | |
427 | */ | |
428 | int gpmc_prefetch_enable(int cs, int dma_mode, | |
429 | unsigned int u32_count, int is_write) | |
430 | { | |
431 | uint32_t prefetch_config1; | |
432 | ||
433 | if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { | |
434 | /* Set the amount of bytes to be prefetched */ | |
435 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count); | |
436 | ||
437 | /* Set dma/mpu mode, the prefetch read / post write and | |
438 | * enable the engine. Set which cs is has requested for. | |
439 | */ | |
440 | prefetch_config1 = ((cs << CS_NUM_SHIFT) | | |
441 | PREFETCH_FIFOTHRESHOLD | | |
442 | ENABLE_PREFETCH | | |
443 | (dma_mode << DMA_MPU_MODE) | | |
444 | (0x1 & is_write)); | |
445 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1); | |
446 | } else { | |
447 | return -EBUSY; | |
448 | } | |
449 | /* Start the prefetch engine */ | |
450 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1); | |
451 | ||
452 | return 0; | |
453 | } | |
454 | EXPORT_SYMBOL(gpmc_prefetch_enable); | |
455 | ||
456 | /** | |
457 | * gpmc_prefetch_reset - disables and stops the prefetch engine | |
458 | */ | |
459 | void gpmc_prefetch_reset(void) | |
460 | { | |
461 | /* Stop the PFPW engine */ | |
462 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0); | |
463 | ||
464 | /* Reset/disable the PFPW engine */ | |
465 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0); | |
466 | } | |
467 | EXPORT_SYMBOL(gpmc_prefetch_reset); | |
468 | ||
469 | /** | |
470 | * gpmc_prefetch_status - reads prefetch status of engine | |
471 | */ | |
472 | int gpmc_prefetch_status(void) | |
473 | { | |
474 | return gpmc_read_reg(GPMC_PREFETCH_STATUS); | |
475 | } | |
476 | EXPORT_SYMBOL(gpmc_prefetch_status); | |
477 | ||
fd1dc87d | 478 | static void __init gpmc_mem_init(void) |
f37e4580 ID |
479 | { |
480 | int cs; | |
481 | unsigned long boot_rom_space = 0; | |
482 | ||
7f245162 KP |
483 | /* never allocate the first page, to facilitate bug detection; |
484 | * even if we didn't boot from ROM. | |
485 | */ | |
486 | boot_rom_space = BOOT_ROM_SPACE; | |
487 | /* In apollon the CS0 is mapped as 0x0000 0000 */ | |
488 | if (machine_is_omap_apollon()) | |
489 | boot_rom_space = 0; | |
f37e4580 ID |
490 | gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space; |
491 | gpmc_mem_root.end = GPMC_MEM_END; | |
492 | ||
493 | /* Reserve all regions that has been set up by bootloader */ | |
494 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | |
495 | u32 base, size; | |
496 | ||
497 | if (!gpmc_cs_mem_enabled(cs)) | |
498 | continue; | |
499 | gpmc_cs_get_memconf(cs, &base, &size); | |
500 | if (gpmc_cs_insert_mem(cs, base, size) < 0) | |
501 | BUG(); | |
502 | } | |
4bbbc1ad JY |
503 | } |
504 | ||
505 | void __init gpmc_init(void) | |
506 | { | |
507 | u32 l; | |
8d08436d | 508 | char *ck = NULL; |
fd1dc87d PW |
509 | |
510 | if (cpu_is_omap24xx()) { | |
511 | ck = "core_l3_ck"; | |
512 | if (cpu_is_omap2420()) | |
513 | l = OMAP2420_GPMC_BASE; | |
514 | else | |
515 | l = OMAP34XX_GPMC_BASE; | |
516 | } else if (cpu_is_omap34xx()) { | |
517 | ck = "gpmc_fck"; | |
518 | l = OMAP34XX_GPMC_BASE; | |
44169075 | 519 | } else if (cpu_is_omap44xx()) { |
d79b1267 | 520 | ck = "gpmc_ck"; |
44169075 | 521 | l = OMAP44XX_GPMC_BASE; |
fd1dc87d | 522 | } |
4bbbc1ad | 523 | |
8d08436d KH |
524 | if (WARN_ON(!ck)) |
525 | return; | |
526 | ||
fd1dc87d PW |
527 | gpmc_l3_clk = clk_get(NULL, ck); |
528 | if (IS_ERR(gpmc_l3_clk)) { | |
529 | printk(KERN_ERR "Could not get GPMC clock %s\n", ck); | |
85d7a070 | 530 | BUG(); |
fd1dc87d PW |
531 | } |
532 | ||
533 | gpmc_base = ioremap(l, SZ_4K); | |
534 | if (!gpmc_base) { | |
535 | clk_put(gpmc_l3_clk); | |
536 | printk(KERN_ERR "Could not get GPMC register memory\n"); | |
85d7a070 | 537 | BUG(); |
fd1dc87d PW |
538 | } |
539 | ||
1daa8c1d OJ |
540 | clk_enable(gpmc_l3_clk); |
541 | ||
4bbbc1ad JY |
542 | l = gpmc_read_reg(GPMC_REVISION); |
543 | printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); | |
544 | /* Set smart idle mode and automatic L3 clock gating */ | |
545 | l = gpmc_read_reg(GPMC_SYSCONFIG); | |
546 | l &= 0x03 << 3; | |
547 | l |= (0x02 << 3) | (1 << 0); | |
548 | gpmc_write_reg(GPMC_SYSCONFIG, l); | |
f37e4580 | 549 | gpmc_mem_init(); |
4bbbc1ad | 550 | } |
a2d3e7ba RN |
551 | |
552 | #ifdef CONFIG_ARCH_OMAP3 | |
553 | static struct omap3_gpmc_regs gpmc_context; | |
554 | ||
555 | void omap3_gpmc_save_context() | |
556 | { | |
557 | int i; | |
558 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); | |
559 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); | |
560 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); | |
561 | gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); | |
562 | gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
563 | gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); | |
564 | gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); | |
565 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
566 | gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); | |
567 | if (gpmc_context.cs_context[i].is_valid) { | |
568 | gpmc_context.cs_context[i].config1 = | |
569 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); | |
570 | gpmc_context.cs_context[i].config2 = | |
571 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); | |
572 | gpmc_context.cs_context[i].config3 = | |
573 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); | |
574 | gpmc_context.cs_context[i].config4 = | |
575 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); | |
576 | gpmc_context.cs_context[i].config5 = | |
577 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); | |
578 | gpmc_context.cs_context[i].config6 = | |
579 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); | |
580 | gpmc_context.cs_context[i].config7 = | |
581 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); | |
582 | } | |
583 | } | |
584 | } | |
585 | ||
586 | void omap3_gpmc_restore_context() | |
587 | { | |
588 | int i; | |
589 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); | |
590 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); | |
591 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); | |
592 | gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); | |
593 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); | |
594 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); | |
595 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); | |
596 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
597 | if (gpmc_context.cs_context[i].is_valid) { | |
598 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, | |
599 | gpmc_context.cs_context[i].config1); | |
600 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, | |
601 | gpmc_context.cs_context[i].config2); | |
602 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, | |
603 | gpmc_context.cs_context[i].config3); | |
604 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, | |
605 | gpmc_context.cs_context[i].config4); | |
606 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, | |
607 | gpmc_context.cs_context[i].config5); | |
608 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, | |
609 | gpmc_context.cs_context[i].config6); | |
610 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, | |
611 | gpmc_context.cs_context[i].config7); | |
612 | } | |
613 | } | |
614 | } | |
615 | #endif /* CONFIG_ARCH_OMAP3 */ |