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1 | /* |
2 | * GPMC support functions | |
3 | * | |
4 | * Copyright (C) 2005-2006 Nokia Corporation | |
5 | * | |
6 | * Author: Juha Yrjola | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/clk.h> | |
16 | ||
17 | #include <asm/io.h> | |
18 | #include <asm/arch/gpmc.h> | |
19 | ||
20 | #undef DEBUG | |
21 | ||
22 | #define GPMC_BASE 0x6800a000 | |
23 | #define GPMC_REVISION 0x00 | |
24 | #define GPMC_SYSCONFIG 0x10 | |
25 | #define GPMC_SYSSTATUS 0x14 | |
26 | #define GPMC_IRQSTATUS 0x18 | |
27 | #define GPMC_IRQENABLE 0x1c | |
28 | #define GPMC_TIMEOUT_CONTROL 0x40 | |
29 | #define GPMC_ERR_ADDRESS 0x44 | |
30 | #define GPMC_ERR_TYPE 0x48 | |
31 | #define GPMC_CONFIG 0x50 | |
32 | #define GPMC_STATUS 0x54 | |
33 | #define GPMC_PREFETCH_CONFIG1 0x1e0 | |
34 | #define GPMC_PREFETCH_CONFIG2 0x1e4 | |
35 | #define GPMC_PREFETCH_CONTROL 0x1e8 | |
36 | #define GPMC_PREFETCH_STATUS 0x1f0 | |
37 | #define GPMC_ECC_CONFIG 0x1f4 | |
38 | #define GPMC_ECC_CONTROL 0x1f8 | |
39 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | |
40 | ||
41 | #define GPMC_CS0 0x60 | |
42 | #define GPMC_CS_SIZE 0x30 | |
43 | ||
44 | static void __iomem *gpmc_base = | |
45 | (void __iomem *) IO_ADDRESS(GPMC_BASE); | |
46 | static void __iomem *gpmc_cs_base = | |
47 | (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0; | |
48 | ||
49 | static struct clk *gpmc_l3_clk; | |
50 | ||
51 | static void gpmc_write_reg(int idx, u32 val) | |
52 | { | |
53 | __raw_writel(val, gpmc_base + idx); | |
54 | } | |
55 | ||
56 | static u32 gpmc_read_reg(int idx) | |
57 | { | |
58 | return __raw_readl(gpmc_base + idx); | |
59 | } | |
60 | ||
61 | void gpmc_cs_write_reg(int cs, int idx, u32 val) | |
62 | { | |
63 | void __iomem *reg_addr; | |
64 | ||
65 | reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx; | |
66 | __raw_writel(val, reg_addr); | |
67 | } | |
68 | ||
69 | u32 gpmc_cs_read_reg(int cs, int idx) | |
70 | { | |
71 | return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx); | |
72 | } | |
73 | ||
74 | /* TODO: Add support for gpmc_fck to clock framework and use it */ | |
75 | static unsigned long gpmc_get_fclk_period(void) | |
76 | { | |
77 | /* In picoseconds */ | |
78 | return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000); | |
79 | } | |
80 | ||
81 | unsigned int gpmc_ns_to_ticks(unsigned int time_ns) | |
82 | { | |
83 | unsigned long tick_ps; | |
84 | ||
85 | /* Calculate in picosecs to yield more exact results */ | |
86 | tick_ps = gpmc_get_fclk_period(); | |
87 | ||
88 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | |
89 | } | |
90 | ||
91 | #ifdef DEBUG | |
92 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
93 | int time, int div, const char *name) | |
94 | #else | |
95 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
96 | int time) | |
97 | #endif | |
98 | { | |
99 | u32 l; | |
100 | int ticks, mask, nr_bits; | |
101 | ||
102 | if (time == 0) | |
103 | ticks = 0; | |
104 | else | |
105 | ticks = gpmc_ns_to_ticks(time); | |
106 | nr_bits = end_bit - st_bit + 1; | |
107 | if (ticks >= 1 << nr_bits) | |
108 | return -1; | |
109 | ||
110 | mask = (1 << nr_bits) - 1; | |
111 | l = gpmc_cs_read_reg(cs, reg); | |
112 | #ifdef DEBUG | |
113 | printk(KERN_INFO "GPMC CS%d: %-10s: %d ticks, %3lu ns (was %i ticks)\n", | |
114 | cs, name, ticks, gpmc_get_clk_period(div) * ticks / 1000, | |
115 | (l >> st_bit) & mask); | |
116 | #endif | |
117 | l &= ~(mask << st_bit); | |
118 | l |= ticks << st_bit; | |
119 | gpmc_cs_write_reg(cs, reg, l); | |
120 | ||
121 | return 0; | |
122 | } | |
123 | ||
124 | #ifdef DEBUG | |
125 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
126 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ | |
127 | t->field, #field) < 0) \ | |
128 | return -1 | |
129 | #else | |
130 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
131 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \ | |
132 | return -1 | |
133 | #endif | |
134 | ||
135 | int gpmc_cs_calc_divider(int cs, unsigned int sync_clk) | |
136 | { | |
137 | int div; | |
138 | u32 l; | |
139 | ||
140 | l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1); | |
141 | div = l / gpmc_get_fclk_period(); | |
142 | if (div > 4) | |
143 | return -1; | |
144 | if (div < 0) | |
145 | div = 1; | |
146 | ||
147 | return div; | |
148 | } | |
149 | ||
150 | int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) | |
151 | { | |
152 | int div; | |
153 | u32 l; | |
154 | ||
155 | div = gpmc_cs_calc_divider(cs, t->sync_clk); | |
156 | if (div < 0) | |
157 | return -1; | |
158 | ||
159 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); | |
160 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); | |
161 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); | |
162 | ||
163 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); | |
164 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); | |
165 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); | |
166 | ||
167 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); | |
168 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); | |
169 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); | |
170 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); | |
171 | ||
172 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); | |
173 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); | |
174 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); | |
175 | ||
176 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); | |
177 | ||
178 | #ifdef DEBUG | |
179 | printk(KERN_INFO "GPMC CLK period is %d (div %d)\n", | |
180 | cs, get_gpmc_clk_period(div), div); | |
181 | #endif | |
182 | ||
183 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
184 | l &= ~0x03; | |
185 | l |= (div - 1); | |
186 | ||
187 | return 0; | |
188 | } | |
189 | ||
190 | unsigned long gpmc_cs_get_base_addr(int cs) | |
191 | { | |
192 | return (gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7) & 0x1f) << 24; | |
193 | } | |
194 | ||
195 | void __init gpmc_init(void) | |
196 | { | |
197 | u32 l; | |
198 | ||
199 | gpmc_l3_clk = clk_get(NULL, "core_l3_ck"); | |
200 | BUG_ON(IS_ERR(gpmc_l3_clk)); | |
201 | ||
202 | l = gpmc_read_reg(GPMC_REVISION); | |
203 | printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); | |
204 | /* Set smart idle mode and automatic L3 clock gating */ | |
205 | l = gpmc_read_reg(GPMC_SYSCONFIG); | |
206 | l &= 0x03 << 3; | |
207 | l |= (0x02 << 3) | (1 << 0); | |
208 | gpmc_write_reg(GPMC_SYSCONFIG, l); | |
209 | } |