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7359154e PW |
1 | /* |
2 | * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips | |
3 | * | |
4 | * Copyright (C) 2009-2010 Nokia Corporation | |
5 | * Paul Walmsley | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * The data in this file should be completely autogeneratable from | |
12 | * the TI hardware database or other technical documentation. | |
13 | * | |
14 | * XXX these should be marked initdata for multi-OMAP kernels | |
15 | */ | |
16 | #include <plat/omap_hwmod.h> | |
17 | #include <mach/irqs.h> | |
18 | #include <plat/cpu.h> | |
19 | #include <plat/dma.h> | |
046465b7 | 20 | #include <plat/serial.h> |
e04d9e1e | 21 | #include <plat/l3_3xxx.h> |
4fe20e97 RN |
22 | #include <plat/l4_3xxx.h> |
23 | #include <plat/i2c.h> | |
70034d38 | 24 | #include <plat/gpio.h> |
d3442726 | 25 | #include <plat/smartreflex.h> |
0f616a4e | 26 | #include <plat/mcspi.h> |
7359154e | 27 | |
43b40992 PW |
28 | #include "omap_hwmod_common_data.h" |
29 | ||
7359154e | 30 | #include "prm-regbits-34xx.h" |
6b667f88 | 31 | #include "cm-regbits-34xx.h" |
ff2516fb | 32 | #include "wd_timer.h" |
273ff8c3 | 33 | #include <mach/am35xx.h> |
7359154e PW |
34 | |
35 | /* | |
36 | * OMAP3xxx hardware module integration data | |
37 | * | |
38 | * ALl of the data in this section should be autogeneratable from the | |
39 | * TI hardware database or other technical documentation. Data that | |
40 | * is driver-specific or driver-kernel integration-specific belongs | |
41 | * elsewhere. | |
42 | */ | |
43 | ||
44 | static struct omap_hwmod omap3xxx_mpu_hwmod; | |
540064bf | 45 | static struct omap_hwmod omap3xxx_iva_hwmod; |
4a7cf90a | 46 | static struct omap_hwmod omap3xxx_l3_main_hwmod; |
7359154e PW |
47 | static struct omap_hwmod omap3xxx_l4_core_hwmod; |
48 | static struct omap_hwmod omap3xxx_l4_per_hwmod; | |
6b667f88 | 49 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod; |
e04d9e1e SG |
50 | static struct omap_hwmod omap3430es1_dss_core_hwmod; |
51 | static struct omap_hwmod omap3xxx_dss_core_hwmod; | |
52 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod; | |
53 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod; | |
54 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod; | |
55 | static struct omap_hwmod omap3xxx_dss_venc_hwmod; | |
4fe20e97 RN |
56 | static struct omap_hwmod omap3xxx_i2c1_hwmod; |
57 | static struct omap_hwmod omap3xxx_i2c2_hwmod; | |
58 | static struct omap_hwmod omap3xxx_i2c3_hwmod; | |
70034d38 VC |
59 | static struct omap_hwmod omap3xxx_gpio1_hwmod; |
60 | static struct omap_hwmod omap3xxx_gpio2_hwmod; | |
61 | static struct omap_hwmod omap3xxx_gpio3_hwmod; | |
62 | static struct omap_hwmod omap3xxx_gpio4_hwmod; | |
63 | static struct omap_hwmod omap3xxx_gpio5_hwmod; | |
64 | static struct omap_hwmod omap3xxx_gpio6_hwmod; | |
d3442726 TG |
65 | static struct omap_hwmod omap34xx_sr1_hwmod; |
66 | static struct omap_hwmod omap34xx_sr2_hwmod; | |
0f616a4e C |
67 | static struct omap_hwmod omap34xx_mcspi1; |
68 | static struct omap_hwmod omap34xx_mcspi2; | |
69 | static struct omap_hwmod omap34xx_mcspi3; | |
70 | static struct omap_hwmod omap34xx_mcspi4; | |
273ff8c3 | 71 | static struct omap_hwmod am35xx_usbhsotg_hwmod; |
7359154e | 72 | |
01438ab6 MK |
73 | static struct omap_hwmod omap3xxx_dma_system_hwmod; |
74 | ||
7359154e | 75 | /* L3 -> L4_CORE interface */ |
4a7cf90a KH |
76 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { |
77 | .master = &omap3xxx_l3_main_hwmod, | |
7359154e PW |
78 | .slave = &omap3xxx_l4_core_hwmod, |
79 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
80 | }; | |
81 | ||
82 | /* L3 -> L4_PER interface */ | |
4a7cf90a KH |
83 | static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { |
84 | .master = &omap3xxx_l3_main_hwmod, | |
7359154e PW |
85 | .slave = &omap3xxx_l4_per_hwmod, |
86 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
87 | }; | |
88 | ||
89 | /* MPU -> L3 interface */ | |
4a7cf90a | 90 | static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { |
7359154e | 91 | .master = &omap3xxx_mpu_hwmod, |
4a7cf90a | 92 | .slave = &omap3xxx_l3_main_hwmod, |
7359154e PW |
93 | .user = OCP_USER_MPU, |
94 | }; | |
95 | ||
96 | /* Slave interfaces on the L3 interconnect */ | |
4a7cf90a KH |
97 | static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { |
98 | &omap3xxx_mpu__l3_main, | |
7359154e PW |
99 | }; |
100 | ||
e04d9e1e SG |
101 | /* DSS -> l3 */ |
102 | static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { | |
103 | .master = &omap3xxx_dss_core_hwmod, | |
104 | .slave = &omap3xxx_l3_main_hwmod, | |
105 | .fw = { | |
106 | .omap2 = { | |
107 | .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, | |
108 | .flags = OMAP_FIREWALL_L3, | |
109 | } | |
110 | }, | |
111 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
112 | }; | |
113 | ||
7359154e | 114 | /* Master interfaces on the L3 interconnect */ |
4a7cf90a KH |
115 | static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { |
116 | &omap3xxx_l3_main__l4_core, | |
117 | &omap3xxx_l3_main__l4_per, | |
7359154e PW |
118 | }; |
119 | ||
120 | /* L3 */ | |
4a7cf90a | 121 | static struct omap_hwmod omap3xxx_l3_main_hwmod = { |
fa98347e | 122 | .name = "l3_main", |
43b40992 | 123 | .class = &l3_hwmod_class, |
4a7cf90a KH |
124 | .masters = omap3xxx_l3_main_masters, |
125 | .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), | |
126 | .slaves = omap3xxx_l3_main_slaves, | |
127 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), | |
2eb1875d KH |
128 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
129 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
130 | }; |
131 | ||
132 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod; | |
046465b7 KH |
133 | static struct omap_hwmod omap3xxx_uart1_hwmod; |
134 | static struct omap_hwmod omap3xxx_uart2_hwmod; | |
135 | static struct omap_hwmod omap3xxx_uart3_hwmod; | |
136 | static struct omap_hwmod omap3xxx_uart4_hwmod; | |
870ea2b8 | 137 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod; |
7359154e | 138 | |
870ea2b8 HH |
139 | /* l3_core -> usbhsotg interface */ |
140 | static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |
141 | .master = &omap3xxx_usbhsotg_hwmod, | |
142 | .slave = &omap3xxx_l3_main_hwmod, | |
143 | .clk = "core_l3_ick", | |
144 | .user = OCP_USER_MPU, | |
145 | }; | |
7359154e | 146 | |
273ff8c3 HH |
147 | /* l3_core -> am35xx_usbhsotg interface */ |
148 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | |
149 | .master = &am35xx_usbhsotg_hwmod, | |
150 | .slave = &omap3xxx_l3_main_hwmod, | |
151 | .clk = "core_l3_ick", | |
152 | .user = OCP_USER_MPU, | |
153 | }; | |
7359154e PW |
154 | /* L4_CORE -> L4_WKUP interface */ |
155 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | |
156 | .master = &omap3xxx_l4_core_hwmod, | |
157 | .slave = &omap3xxx_l4_wkup_hwmod, | |
158 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
159 | }; | |
160 | ||
046465b7 KH |
161 | /* L4 CORE -> UART1 interface */ |
162 | static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { | |
163 | { | |
164 | .pa_start = OMAP3_UART1_BASE, | |
165 | .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, | |
166 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
167 | }, | |
168 | }; | |
169 | ||
170 | static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { | |
171 | .master = &omap3xxx_l4_core_hwmod, | |
172 | .slave = &omap3xxx_uart1_hwmod, | |
173 | .clk = "uart1_ick", | |
174 | .addr = omap3xxx_uart1_addr_space, | |
175 | .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space), | |
176 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
177 | }; | |
178 | ||
179 | /* L4 CORE -> UART2 interface */ | |
180 | static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { | |
181 | { | |
182 | .pa_start = OMAP3_UART2_BASE, | |
183 | .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, | |
184 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
185 | }, | |
186 | }; | |
187 | ||
188 | static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { | |
189 | .master = &omap3xxx_l4_core_hwmod, | |
190 | .slave = &omap3xxx_uart2_hwmod, | |
191 | .clk = "uart2_ick", | |
192 | .addr = omap3xxx_uart2_addr_space, | |
193 | .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space), | |
194 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
195 | }; | |
196 | ||
197 | /* L4 PER -> UART3 interface */ | |
198 | static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { | |
199 | { | |
200 | .pa_start = OMAP3_UART3_BASE, | |
201 | .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, | |
202 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
203 | }, | |
204 | }; | |
205 | ||
206 | static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { | |
207 | .master = &omap3xxx_l4_per_hwmod, | |
208 | .slave = &omap3xxx_uart3_hwmod, | |
209 | .clk = "uart3_ick", | |
210 | .addr = omap3xxx_uart3_addr_space, | |
211 | .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space), | |
212 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
213 | }; | |
214 | ||
215 | /* L4 PER -> UART4 interface */ | |
216 | static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { | |
217 | { | |
218 | .pa_start = OMAP3_UART4_BASE, | |
219 | .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, | |
220 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | |
221 | }, | |
222 | }; | |
223 | ||
224 | static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { | |
225 | .master = &omap3xxx_l4_per_hwmod, | |
226 | .slave = &omap3xxx_uart4_hwmod, | |
227 | .clk = "uart4_ick", | |
228 | .addr = omap3xxx_uart4_addr_space, | |
229 | .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space), | |
230 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
231 | }; | |
232 | ||
4fe20e97 RN |
233 | /* I2C IP block address space length (in bytes) */ |
234 | #define OMAP2_I2C_AS_LEN 128 | |
235 | ||
236 | /* L4 CORE -> I2C1 interface */ | |
237 | static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = { | |
238 | { | |
239 | .pa_start = 0x48070000, | |
240 | .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, | |
241 | .flags = ADDR_TYPE_RT, | |
242 | }, | |
243 | }; | |
244 | ||
245 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { | |
246 | .master = &omap3xxx_l4_core_hwmod, | |
247 | .slave = &omap3xxx_i2c1_hwmod, | |
248 | .clk = "i2c1_ick", | |
249 | .addr = omap3xxx_i2c1_addr_space, | |
250 | .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space), | |
251 | .fw = { | |
252 | .omap2 = { | |
253 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, | |
254 | .l4_prot_group = 7, | |
255 | .flags = OMAP_FIREWALL_L4, | |
256 | } | |
257 | }, | |
258 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
259 | }; | |
260 | ||
261 | /* L4 CORE -> I2C2 interface */ | |
262 | static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = { | |
263 | { | |
264 | .pa_start = 0x48072000, | |
265 | .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, | |
266 | .flags = ADDR_TYPE_RT, | |
267 | }, | |
268 | }; | |
269 | ||
270 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { | |
271 | .master = &omap3xxx_l4_core_hwmod, | |
272 | .slave = &omap3xxx_i2c2_hwmod, | |
273 | .clk = "i2c2_ick", | |
274 | .addr = omap3xxx_i2c2_addr_space, | |
275 | .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space), | |
276 | .fw = { | |
277 | .omap2 = { | |
278 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, | |
279 | .l4_prot_group = 7, | |
280 | .flags = OMAP_FIREWALL_L4, | |
281 | } | |
282 | }, | |
283 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
284 | }; | |
285 | ||
286 | /* L4 CORE -> I2C3 interface */ | |
287 | static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { | |
288 | { | |
289 | .pa_start = 0x48060000, | |
290 | .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1, | |
291 | .flags = ADDR_TYPE_RT, | |
292 | }, | |
293 | }; | |
294 | ||
295 | static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { | |
296 | .master = &omap3xxx_l4_core_hwmod, | |
297 | .slave = &omap3xxx_i2c3_hwmod, | |
298 | .clk = "i2c3_ick", | |
299 | .addr = omap3xxx_i2c3_addr_space, | |
300 | .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space), | |
301 | .fw = { | |
302 | .omap2 = { | |
303 | .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, | |
304 | .l4_prot_group = 7, | |
305 | .flags = OMAP_FIREWALL_L4, | |
306 | } | |
307 | }, | |
308 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
309 | }; | |
310 | ||
d3442726 TG |
311 | /* L4 CORE -> SR1 interface */ |
312 | static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { | |
313 | { | |
314 | .pa_start = OMAP34XX_SR1_BASE, | |
315 | .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, | |
316 | .flags = ADDR_TYPE_RT, | |
317 | }, | |
318 | }; | |
319 | ||
320 | static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { | |
321 | .master = &omap3xxx_l4_core_hwmod, | |
322 | .slave = &omap34xx_sr1_hwmod, | |
323 | .clk = "sr_l4_ick", | |
324 | .addr = omap3_sr1_addr_space, | |
325 | .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space), | |
326 | .user = OCP_USER_MPU, | |
327 | }; | |
328 | ||
329 | /* L4 CORE -> SR1 interface */ | |
330 | static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { | |
331 | { | |
332 | .pa_start = OMAP34XX_SR2_BASE, | |
333 | .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, | |
334 | .flags = ADDR_TYPE_RT, | |
335 | }, | |
336 | }; | |
337 | ||
338 | static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { | |
339 | .master = &omap3xxx_l4_core_hwmod, | |
340 | .slave = &omap34xx_sr2_hwmod, | |
341 | .clk = "sr_l4_ick", | |
342 | .addr = omap3_sr2_addr_space, | |
343 | .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space), | |
344 | .user = OCP_USER_MPU, | |
345 | }; | |
346 | ||
870ea2b8 HH |
347 | /* |
348 | * usbhsotg interface data | |
349 | */ | |
350 | ||
351 | static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { | |
352 | { | |
353 | .pa_start = OMAP34XX_HSUSB_OTG_BASE, | |
354 | .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, | |
355 | .flags = ADDR_TYPE_RT | |
356 | }, | |
357 | }; | |
358 | ||
359 | /* l4_core -> usbhsotg */ | |
360 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { | |
361 | .master = &omap3xxx_l4_core_hwmod, | |
362 | .slave = &omap3xxx_usbhsotg_hwmod, | |
363 | .clk = "l4_ick", | |
364 | .addr = omap3xxx_usbhsotg_addrs, | |
365 | .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs), | |
366 | .user = OCP_USER_MPU, | |
367 | }; | |
368 | ||
369 | static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = { | |
370 | &omap3xxx_usbhsotg__l3, | |
371 | }; | |
372 | ||
373 | static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { | |
374 | &omap3xxx_l4_core__usbhsotg, | |
375 | }; | |
376 | ||
273ff8c3 HH |
377 | static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { |
378 | { | |
379 | .pa_start = AM35XX_IPSS_USBOTGSS_BASE, | |
380 | .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, | |
381 | .flags = ADDR_TYPE_RT | |
382 | }, | |
383 | }; | |
384 | ||
385 | /* l4_core -> usbhsotg */ | |
386 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | |
387 | .master = &omap3xxx_l4_core_hwmod, | |
388 | .slave = &am35xx_usbhsotg_hwmod, | |
389 | .clk = "l4_ick", | |
390 | .addr = am35xx_usbhsotg_addrs, | |
391 | .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs), | |
392 | .user = OCP_USER_MPU, | |
393 | }; | |
394 | ||
395 | static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = { | |
396 | &am35xx_usbhsotg__l3, | |
397 | }; | |
398 | ||
399 | static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = { | |
400 | &am35xx_l4_core__usbhsotg, | |
401 | }; | |
7359154e PW |
402 | /* Slave interfaces on the L4_CORE interconnect */ |
403 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { | |
4a7cf90a | 404 | &omap3xxx_l3_main__l4_core, |
d3442726 TG |
405 | &omap3_l4_core__sr1, |
406 | &omap3_l4_core__sr2, | |
7359154e PW |
407 | }; |
408 | ||
409 | /* Master interfaces on the L4_CORE interconnect */ | |
410 | static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { | |
411 | &omap3xxx_l4_core__l4_wkup, | |
046465b7 KH |
412 | &omap3_l4_core__uart1, |
413 | &omap3_l4_core__uart2, | |
4fe20e97 RN |
414 | &omap3_l4_core__i2c1, |
415 | &omap3_l4_core__i2c2, | |
416 | &omap3_l4_core__i2c3, | |
7359154e PW |
417 | }; |
418 | ||
419 | /* L4 CORE */ | |
420 | static struct omap_hwmod omap3xxx_l4_core_hwmod = { | |
fa98347e | 421 | .name = "l4_core", |
43b40992 | 422 | .class = &l4_hwmod_class, |
7359154e PW |
423 | .masters = omap3xxx_l4_core_masters, |
424 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters), | |
425 | .slaves = omap3xxx_l4_core_slaves, | |
426 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), | |
2eb1875d KH |
427 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
428 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
429 | }; |
430 | ||
431 | /* Slave interfaces on the L4_PER interconnect */ | |
432 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { | |
4a7cf90a | 433 | &omap3xxx_l3_main__l4_per, |
7359154e PW |
434 | }; |
435 | ||
436 | /* Master interfaces on the L4_PER interconnect */ | |
437 | static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { | |
046465b7 KH |
438 | &omap3_l4_per__uart3, |
439 | &omap3_l4_per__uart4, | |
7359154e PW |
440 | }; |
441 | ||
442 | /* L4 PER */ | |
443 | static struct omap_hwmod omap3xxx_l4_per_hwmod = { | |
fa98347e | 444 | .name = "l4_per", |
43b40992 | 445 | .class = &l4_hwmod_class, |
7359154e PW |
446 | .masters = omap3xxx_l4_per_masters, |
447 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters), | |
448 | .slaves = omap3xxx_l4_per_slaves, | |
449 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), | |
2eb1875d KH |
450 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
451 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
452 | }; |
453 | ||
454 | /* Slave interfaces on the L4_WKUP interconnect */ | |
455 | static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { | |
456 | &omap3xxx_l4_core__l4_wkup, | |
457 | }; | |
458 | ||
459 | /* Master interfaces on the L4_WKUP interconnect */ | |
460 | static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = { | |
461 | }; | |
462 | ||
463 | /* L4 WKUP */ | |
464 | static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { | |
fa98347e | 465 | .name = "l4_wkup", |
43b40992 | 466 | .class = &l4_hwmod_class, |
7359154e PW |
467 | .masters = omap3xxx_l4_wkup_masters, |
468 | .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters), | |
469 | .slaves = omap3xxx_l4_wkup_slaves, | |
470 | .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), | |
2eb1875d KH |
471 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
472 | .flags = HWMOD_NO_IDLEST, | |
7359154e PW |
473 | }; |
474 | ||
475 | /* Master interfaces on the MPU device */ | |
476 | static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { | |
4a7cf90a | 477 | &omap3xxx_mpu__l3_main, |
7359154e PW |
478 | }; |
479 | ||
480 | /* MPU */ | |
481 | static struct omap_hwmod omap3xxx_mpu_hwmod = { | |
5c2c0296 | 482 | .name = "mpu", |
43b40992 | 483 | .class = &mpu_hwmod_class, |
7359154e PW |
484 | .main_clk = "arm_fck", |
485 | .masters = omap3xxx_mpu_masters, | |
486 | .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters), | |
487 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
488 | }; | |
489 | ||
540064bf KH |
490 | /* |
491 | * IVA2_2 interface data | |
492 | */ | |
493 | ||
494 | /* IVA2 <- L3 interface */ | |
495 | static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { | |
496 | .master = &omap3xxx_l3_main_hwmod, | |
497 | .slave = &omap3xxx_iva_hwmod, | |
498 | .clk = "iva2_ck", | |
499 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
500 | }; | |
501 | ||
502 | static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = { | |
503 | &omap3xxx_l3__iva, | |
504 | }; | |
505 | ||
506 | /* | |
507 | * IVA2 (IVA2) | |
508 | */ | |
509 | ||
510 | static struct omap_hwmod omap3xxx_iva_hwmod = { | |
511 | .name = "iva", | |
512 | .class = &iva_hwmod_class, | |
513 | .masters = omap3xxx_iva_masters, | |
514 | .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), | |
515 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
516 | }; | |
517 | ||
6b667f88 VC |
518 | /* l4_wkup -> wd_timer2 */ |
519 | static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { | |
520 | { | |
521 | .pa_start = 0x48314000, | |
522 | .pa_end = 0x4831407f, | |
523 | .flags = ADDR_TYPE_RT | |
524 | }, | |
525 | }; | |
526 | ||
527 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { | |
528 | .master = &omap3xxx_l4_wkup_hwmod, | |
529 | .slave = &omap3xxx_wd_timer2_hwmod, | |
530 | .clk = "wdt2_ick", | |
531 | .addr = omap3xxx_wd_timer2_addrs, | |
532 | .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs), | |
533 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
534 | }; | |
535 | ||
536 | /* | |
537 | * 'wd_timer' class | |
538 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on | |
539 | * overflow condition | |
540 | */ | |
541 | ||
542 | static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { | |
543 | .rev_offs = 0x0000, | |
544 | .sysc_offs = 0x0010, | |
545 | .syss_offs = 0x0014, | |
546 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | | |
547 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
548 | SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY), | |
549 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
550 | .sysc_fields = &omap_hwmod_sysc_type1, | |
551 | }; | |
552 | ||
4fe20e97 RN |
553 | /* I2C common */ |
554 | static struct omap_hwmod_class_sysconfig i2c_sysc = { | |
555 | .rev_offs = 0x00, | |
556 | .sysc_offs = 0x20, | |
557 | .syss_offs = 0x10, | |
558 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
559 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
560 | SYSC_HAS_AUTOIDLE), | |
561 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
562 | .sysc_fields = &omap_hwmod_sysc_type1, | |
563 | }; | |
564 | ||
6b667f88 | 565 | static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { |
ff2516fb PW |
566 | .name = "wd_timer", |
567 | .sysc = &omap3xxx_wd_timer_sysc, | |
568 | .pre_shutdown = &omap2_wd_timer_disable | |
6b667f88 VC |
569 | }; |
570 | ||
571 | /* wd_timer2 */ | |
572 | static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { | |
573 | &omap3xxx_l4_wkup__wd_timer2, | |
574 | }; | |
575 | ||
576 | static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { | |
577 | .name = "wd_timer2", | |
578 | .class = &omap3xxx_wd_timer_hwmod_class, | |
579 | .main_clk = "wdt2_fck", | |
580 | .prcm = { | |
581 | .omap2 = { | |
582 | .prcm_reg_id = 1, | |
583 | .module_bit = OMAP3430_EN_WDT2_SHIFT, | |
584 | .module_offs = WKUP_MOD, | |
585 | .idlest_reg_id = 1, | |
586 | .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, | |
587 | }, | |
588 | }, | |
589 | .slaves = omap3xxx_wd_timer2_slaves, | |
590 | .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), | |
591 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
592 | }; | |
593 | ||
046465b7 KH |
594 | /* UART common */ |
595 | ||
596 | static struct omap_hwmod_class_sysconfig uart_sysc = { | |
597 | .rev_offs = 0x50, | |
598 | .sysc_offs = 0x54, | |
599 | .syss_offs = 0x58, | |
600 | .sysc_flags = (SYSC_HAS_SIDLEMODE | | |
601 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
602 | SYSC_HAS_AUTOIDLE), | |
603 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
604 | .sysc_fields = &omap_hwmod_sysc_type1, | |
605 | }; | |
606 | ||
607 | static struct omap_hwmod_class uart_class = { | |
608 | .name = "uart", | |
609 | .sysc = &uart_sysc, | |
610 | }; | |
611 | ||
612 | /* UART1 */ | |
613 | ||
614 | static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { | |
615 | { .irq = INT_24XX_UART1_IRQ, }, | |
616 | }; | |
617 | ||
618 | static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { | |
619 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, | |
620 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, | |
621 | }; | |
622 | ||
623 | static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { | |
624 | &omap3_l4_core__uart1, | |
625 | }; | |
626 | ||
627 | static struct omap_hwmod omap3xxx_uart1_hwmod = { | |
628 | .name = "uart1", | |
629 | .mpu_irqs = uart1_mpu_irqs, | |
630 | .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), | |
631 | .sdma_reqs = uart1_sdma_reqs, | |
632 | .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), | |
633 | .main_clk = "uart1_fck", | |
634 | .prcm = { | |
635 | .omap2 = { | |
636 | .module_offs = CORE_MOD, | |
637 | .prcm_reg_id = 1, | |
638 | .module_bit = OMAP3430_EN_UART1_SHIFT, | |
639 | .idlest_reg_id = 1, | |
640 | .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, | |
641 | }, | |
642 | }, | |
643 | .slaves = omap3xxx_uart1_slaves, | |
644 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), | |
645 | .class = &uart_class, | |
646 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
647 | }; | |
648 | ||
649 | /* UART2 */ | |
650 | ||
651 | static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { | |
652 | { .irq = INT_24XX_UART2_IRQ, }, | |
653 | }; | |
654 | ||
655 | static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { | |
656 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, | |
657 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, | |
658 | }; | |
659 | ||
660 | static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { | |
661 | &omap3_l4_core__uart2, | |
662 | }; | |
663 | ||
664 | static struct omap_hwmod omap3xxx_uart2_hwmod = { | |
665 | .name = "uart2", | |
666 | .mpu_irqs = uart2_mpu_irqs, | |
667 | .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), | |
668 | .sdma_reqs = uart2_sdma_reqs, | |
669 | .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), | |
670 | .main_clk = "uart2_fck", | |
671 | .prcm = { | |
672 | .omap2 = { | |
673 | .module_offs = CORE_MOD, | |
674 | .prcm_reg_id = 1, | |
675 | .module_bit = OMAP3430_EN_UART2_SHIFT, | |
676 | .idlest_reg_id = 1, | |
677 | .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, | |
678 | }, | |
679 | }, | |
680 | .slaves = omap3xxx_uart2_slaves, | |
681 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), | |
682 | .class = &uart_class, | |
683 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
684 | }; | |
685 | ||
686 | /* UART3 */ | |
687 | ||
688 | static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { | |
689 | { .irq = INT_24XX_UART3_IRQ, }, | |
690 | }; | |
691 | ||
692 | static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { | |
693 | { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, | |
694 | { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, | |
695 | }; | |
696 | ||
697 | static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { | |
698 | &omap3_l4_per__uart3, | |
699 | }; | |
700 | ||
701 | static struct omap_hwmod omap3xxx_uart3_hwmod = { | |
702 | .name = "uart3", | |
703 | .mpu_irqs = uart3_mpu_irqs, | |
704 | .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), | |
705 | .sdma_reqs = uart3_sdma_reqs, | |
706 | .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), | |
707 | .main_clk = "uart3_fck", | |
708 | .prcm = { | |
709 | .omap2 = { | |
710 | .module_offs = OMAP3430_PER_MOD, | |
711 | .prcm_reg_id = 1, | |
712 | .module_bit = OMAP3430_EN_UART3_SHIFT, | |
713 | .idlest_reg_id = 1, | |
714 | .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, | |
715 | }, | |
716 | }, | |
717 | .slaves = omap3xxx_uart3_slaves, | |
718 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), | |
719 | .class = &uart_class, | |
720 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
721 | }; | |
722 | ||
723 | /* UART4 */ | |
724 | ||
725 | static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { | |
726 | { .irq = INT_36XX_UART4_IRQ, }, | |
727 | }; | |
728 | ||
729 | static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { | |
730 | { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, | |
731 | { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, | |
732 | }; | |
733 | ||
734 | static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { | |
735 | &omap3_l4_per__uart4, | |
736 | }; | |
737 | ||
738 | static struct omap_hwmod omap3xxx_uart4_hwmod = { | |
739 | .name = "uart4", | |
740 | .mpu_irqs = uart4_mpu_irqs, | |
741 | .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs), | |
742 | .sdma_reqs = uart4_sdma_reqs, | |
743 | .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs), | |
744 | .main_clk = "uart4_fck", | |
745 | .prcm = { | |
746 | .omap2 = { | |
747 | .module_offs = OMAP3430_PER_MOD, | |
748 | .prcm_reg_id = 1, | |
749 | .module_bit = OMAP3630_EN_UART4_SHIFT, | |
750 | .idlest_reg_id = 1, | |
751 | .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, | |
752 | }, | |
753 | }, | |
754 | .slaves = omap3xxx_uart4_slaves, | |
755 | .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), | |
756 | .class = &uart_class, | |
757 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), | |
758 | }; | |
759 | ||
4fe20e97 RN |
760 | static struct omap_hwmod_class i2c_class = { |
761 | .name = "i2c", | |
762 | .sysc = &i2c_sysc, | |
763 | }; | |
764 | ||
e04d9e1e SG |
765 | /* |
766 | * 'dss' class | |
767 | * display sub-system | |
768 | */ | |
769 | ||
770 | static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = { | |
771 | .rev_offs = 0x0000, | |
772 | .sysc_offs = 0x0010, | |
773 | .syss_offs = 0x0014, | |
774 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
775 | .sysc_fields = &omap_hwmod_sysc_type1, | |
776 | }; | |
777 | ||
778 | static struct omap_hwmod_class omap3xxx_dss_hwmod_class = { | |
779 | .name = "dss", | |
780 | .sysc = &omap3xxx_dss_sysc, | |
781 | }; | |
782 | ||
783 | /* dss */ | |
784 | static struct omap_hwmod_irq_info omap3xxx_dss_irqs[] = { | |
785 | { .irq = 25 }, | |
786 | }; | |
787 | ||
788 | static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { | |
789 | { .name = "dispc", .dma_req = 5 }, | |
790 | { .name = "dsi1", .dma_req = 74 }, | |
791 | }; | |
792 | ||
793 | /* dss */ | |
794 | /* dss master ports */ | |
795 | static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = { | |
796 | &omap3xxx_dss__l3, | |
797 | }; | |
798 | ||
799 | static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = { | |
800 | { | |
801 | .pa_start = 0x48050000, | |
802 | .pa_end = 0x480503FF, | |
803 | .flags = ADDR_TYPE_RT | |
804 | }, | |
805 | }; | |
806 | ||
807 | /* l4_core -> dss */ | |
808 | static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { | |
809 | .master = &omap3xxx_l4_core_hwmod, | |
810 | .slave = &omap3430es1_dss_core_hwmod, | |
811 | .clk = "dss_ick", | |
812 | .addr = omap3xxx_dss_addrs, | |
813 | .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs), | |
814 | .fw = { | |
815 | .omap2 = { | |
816 | .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, | |
817 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
818 | .flags = OMAP_FIREWALL_L4, | |
819 | } | |
820 | }, | |
821 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
822 | }; | |
823 | ||
824 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { | |
825 | .master = &omap3xxx_l4_core_hwmod, | |
826 | .slave = &omap3xxx_dss_core_hwmod, | |
827 | .clk = "dss_ick", | |
828 | .addr = omap3xxx_dss_addrs, | |
829 | .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs), | |
830 | .fw = { | |
831 | .omap2 = { | |
832 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, | |
833 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
834 | .flags = OMAP_FIREWALL_L4, | |
835 | } | |
836 | }, | |
837 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
838 | }; | |
839 | ||
840 | /* dss slave ports */ | |
841 | static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = { | |
842 | &omap3430es1_l4_core__dss, | |
843 | }; | |
844 | ||
845 | static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { | |
846 | &omap3xxx_l4_core__dss, | |
847 | }; | |
848 | ||
849 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { | |
850 | { .role = "tv_clk", .clk = "dss_tv_fck" }, | |
851 | { .role = "dssclk", .clk = "dss_96m_fck" }, | |
852 | { .role = "sys_clk", .clk = "dss2_alwon_fck" }, | |
853 | }; | |
854 | ||
855 | static struct omap_hwmod omap3430es1_dss_core_hwmod = { | |
856 | .name = "dss_core", | |
857 | .class = &omap3xxx_dss_hwmod_class, | |
858 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
859 | .mpu_irqs = omap3xxx_dss_irqs, | |
860 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs), | |
861 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
862 | .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), | |
863 | ||
864 | .prcm = { | |
865 | .omap2 = { | |
866 | .prcm_reg_id = 1, | |
867 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
868 | .module_offs = OMAP3430_DSS_MOD, | |
869 | .idlest_reg_id = 1, | |
870 | .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, | |
871 | }, | |
872 | }, | |
873 | .opt_clks = dss_opt_clks, | |
874 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
875 | .slaves = omap3430es1_dss_slaves, | |
876 | .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), | |
877 | .masters = omap3xxx_dss_masters, | |
878 | .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), | |
879 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), | |
880 | .flags = HWMOD_NO_IDLEST, | |
881 | }; | |
882 | ||
883 | static struct omap_hwmod omap3xxx_dss_core_hwmod = { | |
884 | .name = "dss_core", | |
885 | .class = &omap3xxx_dss_hwmod_class, | |
886 | .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ | |
887 | .mpu_irqs = omap3xxx_dss_irqs, | |
888 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dss_irqs), | |
889 | .sdma_reqs = omap3xxx_dss_sdma_chs, | |
890 | .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), | |
891 | ||
892 | .prcm = { | |
893 | .omap2 = { | |
894 | .prcm_reg_id = 1, | |
895 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
896 | .module_offs = OMAP3430_DSS_MOD, | |
897 | .idlest_reg_id = 1, | |
898 | .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, | |
899 | .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, | |
900 | }, | |
901 | }, | |
902 | .opt_clks = dss_opt_clks, | |
903 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), | |
904 | .slaves = omap3xxx_dss_slaves, | |
905 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves), | |
906 | .masters = omap3xxx_dss_masters, | |
907 | .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), | |
908 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 | | |
909 | CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1), | |
910 | }; | |
911 | ||
912 | /* | |
913 | * 'dispc' class | |
914 | * display controller | |
915 | */ | |
916 | ||
917 | static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = { | |
918 | .rev_offs = 0x0000, | |
919 | .sysc_offs = 0x0010, | |
920 | .syss_offs = 0x0014, | |
921 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
922 | SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
923 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
924 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
925 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
926 | .sysc_fields = &omap_hwmod_sysc_type1, | |
927 | }; | |
928 | ||
929 | static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = { | |
930 | .name = "dispc", | |
931 | .sysc = &omap3xxx_dispc_sysc, | |
932 | }; | |
933 | ||
934 | static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = { | |
935 | { | |
936 | .pa_start = 0x48050400, | |
937 | .pa_end = 0x480507FF, | |
938 | .flags = ADDR_TYPE_RT | |
939 | }, | |
940 | }; | |
941 | ||
942 | /* l4_core -> dss_dispc */ | |
943 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { | |
944 | .master = &omap3xxx_l4_core_hwmod, | |
945 | .slave = &omap3xxx_dss_dispc_hwmod, | |
946 | .clk = "dss_ick", | |
947 | .addr = omap3xxx_dss_dispc_addrs, | |
948 | .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs), | |
949 | .fw = { | |
950 | .omap2 = { | |
951 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, | |
952 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
953 | .flags = OMAP_FIREWALL_L4, | |
954 | } | |
955 | }, | |
956 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
957 | }; | |
958 | ||
959 | /* dss_dispc slave ports */ | |
960 | static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { | |
961 | &omap3xxx_l4_core__dss_dispc, | |
962 | }; | |
963 | ||
964 | static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { | |
965 | .name = "dss_dispc", | |
966 | .class = &omap3xxx_dispc_hwmod_class, | |
967 | .main_clk = "dss1_alwon_fck", | |
968 | .prcm = { | |
969 | .omap2 = { | |
970 | .prcm_reg_id = 1, | |
971 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
972 | .module_offs = OMAP3430_DSS_MOD, | |
973 | }, | |
974 | }, | |
975 | .slaves = omap3xxx_dss_dispc_slaves, | |
976 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), | |
977 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | | |
978 | CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | | |
979 | CHIP_GE_OMAP3630ES1_1), | |
980 | .flags = HWMOD_NO_IDLEST, | |
981 | }; | |
982 | ||
983 | /* | |
984 | * 'dsi' class | |
985 | * display serial interface controller | |
986 | */ | |
987 | ||
988 | static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { | |
989 | .name = "dsi", | |
990 | }; | |
991 | ||
992 | /* dss_dsi1 */ | |
993 | static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { | |
994 | { | |
995 | .pa_start = 0x4804FC00, | |
996 | .pa_end = 0x4804FFFF, | |
997 | .flags = ADDR_TYPE_RT | |
998 | }, | |
999 | }; | |
1000 | ||
1001 | /* l4_core -> dss_dsi1 */ | |
1002 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { | |
1003 | .master = &omap3xxx_l4_core_hwmod, | |
1004 | .slave = &omap3xxx_dss_dsi1_hwmod, | |
1005 | .addr = omap3xxx_dss_dsi1_addrs, | |
1006 | .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs), | |
1007 | .fw = { | |
1008 | .omap2 = { | |
1009 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, | |
1010 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
1011 | .flags = OMAP_FIREWALL_L4, | |
1012 | } | |
1013 | }, | |
1014 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1015 | }; | |
1016 | ||
1017 | /* dss_dsi1 slave ports */ | |
1018 | static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { | |
1019 | &omap3xxx_l4_core__dss_dsi1, | |
1020 | }; | |
1021 | ||
1022 | static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { | |
1023 | .name = "dss_dsi1", | |
1024 | .class = &omap3xxx_dsi_hwmod_class, | |
1025 | .main_clk = "dss1_alwon_fck", | |
1026 | .prcm = { | |
1027 | .omap2 = { | |
1028 | .prcm_reg_id = 1, | |
1029 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1030 | .module_offs = OMAP3430_DSS_MOD, | |
1031 | }, | |
1032 | }, | |
1033 | .slaves = omap3xxx_dss_dsi1_slaves, | |
1034 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), | |
1035 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | | |
1036 | CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | | |
1037 | CHIP_GE_OMAP3630ES1_1), | |
1038 | .flags = HWMOD_NO_IDLEST, | |
1039 | }; | |
1040 | ||
1041 | /* | |
1042 | * 'rfbi' class | |
1043 | * remote frame buffer interface | |
1044 | */ | |
1045 | ||
1046 | static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = { | |
1047 | .rev_offs = 0x0000, | |
1048 | .sysc_offs = 0x0010, | |
1049 | .syss_offs = 0x0014, | |
1050 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1051 | SYSC_HAS_AUTOIDLE), | |
1052 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1053 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1054 | }; | |
1055 | ||
1056 | static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = { | |
1057 | .name = "rfbi", | |
1058 | .sysc = &omap3xxx_rfbi_sysc, | |
1059 | }; | |
1060 | ||
1061 | static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = { | |
1062 | { | |
1063 | .pa_start = 0x48050800, | |
1064 | .pa_end = 0x48050BFF, | |
1065 | .flags = ADDR_TYPE_RT | |
1066 | }, | |
1067 | }; | |
1068 | ||
1069 | /* l4_core -> dss_rfbi */ | |
1070 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { | |
1071 | .master = &omap3xxx_l4_core_hwmod, | |
1072 | .slave = &omap3xxx_dss_rfbi_hwmod, | |
1073 | .clk = "dss_ick", | |
1074 | .addr = omap3xxx_dss_rfbi_addrs, | |
1075 | .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs), | |
1076 | .fw = { | |
1077 | .omap2 = { | |
1078 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, | |
1079 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , | |
1080 | .flags = OMAP_FIREWALL_L4, | |
1081 | } | |
1082 | }, | |
1083 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1084 | }; | |
1085 | ||
1086 | /* dss_rfbi slave ports */ | |
1087 | static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { | |
1088 | &omap3xxx_l4_core__dss_rfbi, | |
1089 | }; | |
1090 | ||
1091 | static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { | |
1092 | .name = "dss_rfbi", | |
1093 | .class = &omap3xxx_rfbi_hwmod_class, | |
1094 | .main_clk = "dss1_alwon_fck", | |
1095 | .prcm = { | |
1096 | .omap2 = { | |
1097 | .prcm_reg_id = 1, | |
1098 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1099 | .module_offs = OMAP3430_DSS_MOD, | |
1100 | }, | |
1101 | }, | |
1102 | .slaves = omap3xxx_dss_rfbi_slaves, | |
1103 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), | |
1104 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | | |
1105 | CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | | |
1106 | CHIP_GE_OMAP3630ES1_1), | |
1107 | .flags = HWMOD_NO_IDLEST, | |
1108 | }; | |
1109 | ||
1110 | /* | |
1111 | * 'venc' class | |
1112 | * video encoder | |
1113 | */ | |
1114 | ||
1115 | static struct omap_hwmod_class omap3xxx_venc_hwmod_class = { | |
1116 | .name = "venc", | |
1117 | }; | |
1118 | ||
1119 | /* dss_venc */ | |
1120 | static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = { | |
1121 | { | |
1122 | .pa_start = 0x48050C00, | |
1123 | .pa_end = 0x48050FFF, | |
1124 | .flags = ADDR_TYPE_RT | |
1125 | }, | |
1126 | }; | |
1127 | ||
1128 | /* l4_core -> dss_venc */ | |
1129 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { | |
1130 | .master = &omap3xxx_l4_core_hwmod, | |
1131 | .slave = &omap3xxx_dss_venc_hwmod, | |
1132 | .clk = "dss_tv_fck", | |
1133 | .addr = omap3xxx_dss_venc_addrs, | |
1134 | .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs), | |
1135 | .fw = { | |
1136 | .omap2 = { | |
1137 | .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, | |
1138 | .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, | |
1139 | .flags = OMAP_FIREWALL_L4, | |
1140 | } | |
1141 | }, | |
1142 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1143 | }; | |
1144 | ||
1145 | /* dss_venc slave ports */ | |
1146 | static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { | |
1147 | &omap3xxx_l4_core__dss_venc, | |
1148 | }; | |
1149 | ||
1150 | static struct omap_hwmod omap3xxx_dss_venc_hwmod = { | |
1151 | .name = "dss_venc", | |
1152 | .class = &omap3xxx_venc_hwmod_class, | |
1153 | .main_clk = "dss1_alwon_fck", | |
1154 | .prcm = { | |
1155 | .omap2 = { | |
1156 | .prcm_reg_id = 1, | |
1157 | .module_bit = OMAP3430_EN_DSS1_SHIFT, | |
1158 | .module_offs = OMAP3430_DSS_MOD, | |
1159 | }, | |
1160 | }, | |
1161 | .slaves = omap3xxx_dss_venc_slaves, | |
1162 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), | |
1163 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | | |
1164 | CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | | |
1165 | CHIP_GE_OMAP3630ES1_1), | |
1166 | .flags = HWMOD_NO_IDLEST, | |
1167 | }; | |
1168 | ||
4fe20e97 RN |
1169 | /* I2C1 */ |
1170 | ||
1171 | static struct omap_i2c_dev_attr i2c1_dev_attr = { | |
1172 | .fifo_depth = 8, /* bytes */ | |
1173 | }; | |
1174 | ||
1175 | static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { | |
1176 | { .irq = INT_24XX_I2C1_IRQ, }, | |
1177 | }; | |
1178 | ||
1179 | static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { | |
1180 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, | |
1181 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, | |
1182 | }; | |
1183 | ||
1184 | static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { | |
1185 | &omap3_l4_core__i2c1, | |
1186 | }; | |
1187 | ||
1188 | static struct omap_hwmod omap3xxx_i2c1_hwmod = { | |
1189 | .name = "i2c1", | |
1190 | .mpu_irqs = i2c1_mpu_irqs, | |
1191 | .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), | |
1192 | .sdma_reqs = i2c1_sdma_reqs, | |
1193 | .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), | |
1194 | .main_clk = "i2c1_fck", | |
1195 | .prcm = { | |
1196 | .omap2 = { | |
1197 | .module_offs = CORE_MOD, | |
1198 | .prcm_reg_id = 1, | |
1199 | .module_bit = OMAP3430_EN_I2C1_SHIFT, | |
1200 | .idlest_reg_id = 1, | |
1201 | .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, | |
1202 | }, | |
1203 | }, | |
1204 | .slaves = omap3xxx_i2c1_slaves, | |
1205 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), | |
1206 | .class = &i2c_class, | |
1207 | .dev_attr = &i2c1_dev_attr, | |
1208 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1209 | }; | |
1210 | ||
1211 | /* I2C2 */ | |
1212 | ||
1213 | static struct omap_i2c_dev_attr i2c2_dev_attr = { | |
1214 | .fifo_depth = 8, /* bytes */ | |
1215 | }; | |
1216 | ||
1217 | static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { | |
1218 | { .irq = INT_24XX_I2C2_IRQ, }, | |
1219 | }; | |
1220 | ||
1221 | static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { | |
1222 | { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, | |
1223 | { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, | |
1224 | }; | |
1225 | ||
1226 | static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { | |
1227 | &omap3_l4_core__i2c2, | |
1228 | }; | |
1229 | ||
1230 | static struct omap_hwmod omap3xxx_i2c2_hwmod = { | |
1231 | .name = "i2c2", | |
1232 | .mpu_irqs = i2c2_mpu_irqs, | |
1233 | .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), | |
1234 | .sdma_reqs = i2c2_sdma_reqs, | |
1235 | .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), | |
1236 | .main_clk = "i2c2_fck", | |
1237 | .prcm = { | |
1238 | .omap2 = { | |
1239 | .module_offs = CORE_MOD, | |
1240 | .prcm_reg_id = 1, | |
1241 | .module_bit = OMAP3430_EN_I2C2_SHIFT, | |
1242 | .idlest_reg_id = 1, | |
1243 | .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, | |
1244 | }, | |
1245 | }, | |
1246 | .slaves = omap3xxx_i2c2_slaves, | |
1247 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), | |
1248 | .class = &i2c_class, | |
1249 | .dev_attr = &i2c2_dev_attr, | |
1250 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1251 | }; | |
1252 | ||
1253 | /* I2C3 */ | |
1254 | ||
1255 | static struct omap_i2c_dev_attr i2c3_dev_attr = { | |
1256 | .fifo_depth = 64, /* bytes */ | |
1257 | }; | |
1258 | ||
1259 | static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { | |
1260 | { .irq = INT_34XX_I2C3_IRQ, }, | |
1261 | }; | |
1262 | ||
1263 | static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { | |
1264 | { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, | |
1265 | { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, | |
1266 | }; | |
1267 | ||
1268 | static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { | |
1269 | &omap3_l4_core__i2c3, | |
1270 | }; | |
1271 | ||
1272 | static struct omap_hwmod omap3xxx_i2c3_hwmod = { | |
1273 | .name = "i2c3", | |
1274 | .mpu_irqs = i2c3_mpu_irqs, | |
1275 | .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs), | |
1276 | .sdma_reqs = i2c3_sdma_reqs, | |
1277 | .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs), | |
1278 | .main_clk = "i2c3_fck", | |
1279 | .prcm = { | |
1280 | .omap2 = { | |
1281 | .module_offs = CORE_MOD, | |
1282 | .prcm_reg_id = 1, | |
1283 | .module_bit = OMAP3430_EN_I2C3_SHIFT, | |
1284 | .idlest_reg_id = 1, | |
1285 | .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, | |
1286 | }, | |
1287 | }, | |
1288 | .slaves = omap3xxx_i2c3_slaves, | |
1289 | .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), | |
1290 | .class = &i2c_class, | |
1291 | .dev_attr = &i2c3_dev_attr, | |
1292 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1293 | }; | |
1294 | ||
70034d38 VC |
1295 | /* l4_wkup -> gpio1 */ |
1296 | static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { | |
1297 | { | |
1298 | .pa_start = 0x48310000, | |
1299 | .pa_end = 0x483101ff, | |
1300 | .flags = ADDR_TYPE_RT | |
1301 | }, | |
1302 | }; | |
1303 | ||
1304 | static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { | |
1305 | .master = &omap3xxx_l4_wkup_hwmod, | |
1306 | .slave = &omap3xxx_gpio1_hwmod, | |
1307 | .addr = omap3xxx_gpio1_addrs, | |
1308 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs), | |
1309 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1310 | }; | |
1311 | ||
1312 | /* l4_per -> gpio2 */ | |
1313 | static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { | |
1314 | { | |
1315 | .pa_start = 0x49050000, | |
1316 | .pa_end = 0x490501ff, | |
1317 | .flags = ADDR_TYPE_RT | |
1318 | }, | |
1319 | }; | |
1320 | ||
1321 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { | |
1322 | .master = &omap3xxx_l4_per_hwmod, | |
1323 | .slave = &omap3xxx_gpio2_hwmod, | |
1324 | .addr = omap3xxx_gpio2_addrs, | |
1325 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs), | |
1326 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1327 | }; | |
1328 | ||
1329 | /* l4_per -> gpio3 */ | |
1330 | static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { | |
1331 | { | |
1332 | .pa_start = 0x49052000, | |
1333 | .pa_end = 0x490521ff, | |
1334 | .flags = ADDR_TYPE_RT | |
1335 | }, | |
1336 | }; | |
1337 | ||
1338 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { | |
1339 | .master = &omap3xxx_l4_per_hwmod, | |
1340 | .slave = &omap3xxx_gpio3_hwmod, | |
1341 | .addr = omap3xxx_gpio3_addrs, | |
1342 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs), | |
1343 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1344 | }; | |
1345 | ||
1346 | /* l4_per -> gpio4 */ | |
1347 | static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { | |
1348 | { | |
1349 | .pa_start = 0x49054000, | |
1350 | .pa_end = 0x490541ff, | |
1351 | .flags = ADDR_TYPE_RT | |
1352 | }, | |
1353 | }; | |
1354 | ||
1355 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { | |
1356 | .master = &omap3xxx_l4_per_hwmod, | |
1357 | .slave = &omap3xxx_gpio4_hwmod, | |
1358 | .addr = omap3xxx_gpio4_addrs, | |
1359 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs), | |
1360 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1361 | }; | |
1362 | ||
1363 | /* l4_per -> gpio5 */ | |
1364 | static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { | |
1365 | { | |
1366 | .pa_start = 0x49056000, | |
1367 | .pa_end = 0x490561ff, | |
1368 | .flags = ADDR_TYPE_RT | |
1369 | }, | |
1370 | }; | |
1371 | ||
1372 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { | |
1373 | .master = &omap3xxx_l4_per_hwmod, | |
1374 | .slave = &omap3xxx_gpio5_hwmod, | |
1375 | .addr = omap3xxx_gpio5_addrs, | |
1376 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs), | |
1377 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1378 | }; | |
1379 | ||
1380 | /* l4_per -> gpio6 */ | |
1381 | static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { | |
1382 | { | |
1383 | .pa_start = 0x49058000, | |
1384 | .pa_end = 0x490581ff, | |
1385 | .flags = ADDR_TYPE_RT | |
1386 | }, | |
1387 | }; | |
1388 | ||
1389 | static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { | |
1390 | .master = &omap3xxx_l4_per_hwmod, | |
1391 | .slave = &omap3xxx_gpio6_hwmod, | |
1392 | .addr = omap3xxx_gpio6_addrs, | |
1393 | .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs), | |
1394 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1395 | }; | |
1396 | ||
1397 | /* | |
1398 | * 'gpio' class | |
1399 | * general purpose io module | |
1400 | */ | |
1401 | ||
1402 | static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { | |
1403 | .rev_offs = 0x0000, | |
1404 | .sysc_offs = 0x0010, | |
1405 | .syss_offs = 0x0014, | |
1406 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | | |
1407 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), | |
1408 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1409 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1410 | }; | |
1411 | ||
1412 | static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { | |
1413 | .name = "gpio", | |
1414 | .sysc = &omap3xxx_gpio_sysc, | |
1415 | .rev = 1, | |
1416 | }; | |
1417 | ||
1418 | /* gpio_dev_attr*/ | |
1419 | static struct omap_gpio_dev_attr gpio_dev_attr = { | |
1420 | .bank_width = 32, | |
1421 | .dbck_flag = true, | |
1422 | }; | |
1423 | ||
1424 | /* gpio1 */ | |
1425 | static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = { | |
1426 | { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */ | |
1427 | }; | |
1428 | ||
1429 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { | |
1430 | { .role = "dbclk", .clk = "gpio1_dbck", }, | |
1431 | }; | |
1432 | ||
1433 | static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = { | |
1434 | &omap3xxx_l4_wkup__gpio1, | |
1435 | }; | |
1436 | ||
1437 | static struct omap_hwmod omap3xxx_gpio1_hwmod = { | |
1438 | .name = "gpio1", | |
1439 | .mpu_irqs = omap3xxx_gpio1_irqs, | |
1440 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs), | |
1441 | .main_clk = "gpio1_ick", | |
1442 | .opt_clks = gpio1_opt_clks, | |
1443 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), | |
1444 | .prcm = { | |
1445 | .omap2 = { | |
1446 | .prcm_reg_id = 1, | |
1447 | .module_bit = OMAP3430_EN_GPIO1_SHIFT, | |
1448 | .module_offs = WKUP_MOD, | |
1449 | .idlest_reg_id = 1, | |
1450 | .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, | |
1451 | }, | |
1452 | }, | |
1453 | .slaves = omap3xxx_gpio1_slaves, | |
1454 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves), | |
1455 | .class = &omap3xxx_gpio_hwmod_class, | |
1456 | .dev_attr = &gpio_dev_attr, | |
1457 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1458 | }; | |
1459 | ||
1460 | /* gpio2 */ | |
1461 | static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = { | |
1462 | { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */ | |
1463 | }; | |
1464 | ||
1465 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { | |
1466 | { .role = "dbclk", .clk = "gpio2_dbck", }, | |
1467 | }; | |
1468 | ||
1469 | static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = { | |
1470 | &omap3xxx_l4_per__gpio2, | |
1471 | }; | |
1472 | ||
1473 | static struct omap_hwmod omap3xxx_gpio2_hwmod = { | |
1474 | .name = "gpio2", | |
1475 | .mpu_irqs = omap3xxx_gpio2_irqs, | |
1476 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs), | |
1477 | .main_clk = "gpio2_ick", | |
1478 | .opt_clks = gpio2_opt_clks, | |
1479 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), | |
1480 | .prcm = { | |
1481 | .omap2 = { | |
1482 | .prcm_reg_id = 1, | |
1483 | .module_bit = OMAP3430_EN_GPIO2_SHIFT, | |
1484 | .module_offs = OMAP3430_PER_MOD, | |
1485 | .idlest_reg_id = 1, | |
1486 | .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, | |
1487 | }, | |
1488 | }, | |
1489 | .slaves = omap3xxx_gpio2_slaves, | |
1490 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves), | |
1491 | .class = &omap3xxx_gpio_hwmod_class, | |
1492 | .dev_attr = &gpio_dev_attr, | |
1493 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1494 | }; | |
1495 | ||
1496 | /* gpio3 */ | |
1497 | static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = { | |
1498 | { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */ | |
1499 | }; | |
1500 | ||
1501 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { | |
1502 | { .role = "dbclk", .clk = "gpio3_dbck", }, | |
1503 | }; | |
1504 | ||
1505 | static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = { | |
1506 | &omap3xxx_l4_per__gpio3, | |
1507 | }; | |
1508 | ||
1509 | static struct omap_hwmod omap3xxx_gpio3_hwmod = { | |
1510 | .name = "gpio3", | |
1511 | .mpu_irqs = omap3xxx_gpio3_irqs, | |
1512 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs), | |
1513 | .main_clk = "gpio3_ick", | |
1514 | .opt_clks = gpio3_opt_clks, | |
1515 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), | |
1516 | .prcm = { | |
1517 | .omap2 = { | |
1518 | .prcm_reg_id = 1, | |
1519 | .module_bit = OMAP3430_EN_GPIO3_SHIFT, | |
1520 | .module_offs = OMAP3430_PER_MOD, | |
1521 | .idlest_reg_id = 1, | |
1522 | .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, | |
1523 | }, | |
1524 | }, | |
1525 | .slaves = omap3xxx_gpio3_slaves, | |
1526 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves), | |
1527 | .class = &omap3xxx_gpio_hwmod_class, | |
1528 | .dev_attr = &gpio_dev_attr, | |
1529 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1530 | }; | |
1531 | ||
1532 | /* gpio4 */ | |
1533 | static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = { | |
1534 | { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */ | |
1535 | }; | |
1536 | ||
1537 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { | |
1538 | { .role = "dbclk", .clk = "gpio4_dbck", }, | |
1539 | }; | |
1540 | ||
1541 | static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = { | |
1542 | &omap3xxx_l4_per__gpio4, | |
1543 | }; | |
1544 | ||
1545 | static struct omap_hwmod omap3xxx_gpio4_hwmod = { | |
1546 | .name = "gpio4", | |
1547 | .mpu_irqs = omap3xxx_gpio4_irqs, | |
1548 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs), | |
1549 | .main_clk = "gpio4_ick", | |
1550 | .opt_clks = gpio4_opt_clks, | |
1551 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), | |
1552 | .prcm = { | |
1553 | .omap2 = { | |
1554 | .prcm_reg_id = 1, | |
1555 | .module_bit = OMAP3430_EN_GPIO4_SHIFT, | |
1556 | .module_offs = OMAP3430_PER_MOD, | |
1557 | .idlest_reg_id = 1, | |
1558 | .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, | |
1559 | }, | |
1560 | }, | |
1561 | .slaves = omap3xxx_gpio4_slaves, | |
1562 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves), | |
1563 | .class = &omap3xxx_gpio_hwmod_class, | |
1564 | .dev_attr = &gpio_dev_attr, | |
1565 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1566 | }; | |
1567 | ||
1568 | /* gpio5 */ | |
1569 | static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { | |
1570 | { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ | |
1571 | }; | |
1572 | ||
1573 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { | |
1574 | { .role = "dbclk", .clk = "gpio5_dbck", }, | |
1575 | }; | |
1576 | ||
1577 | static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = { | |
1578 | &omap3xxx_l4_per__gpio5, | |
1579 | }; | |
1580 | ||
1581 | static struct omap_hwmod omap3xxx_gpio5_hwmod = { | |
1582 | .name = "gpio5", | |
1583 | .mpu_irqs = omap3xxx_gpio5_irqs, | |
1584 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs), | |
1585 | .main_clk = "gpio5_ick", | |
1586 | .opt_clks = gpio5_opt_clks, | |
1587 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), | |
1588 | .prcm = { | |
1589 | .omap2 = { | |
1590 | .prcm_reg_id = 1, | |
1591 | .module_bit = OMAP3430_EN_GPIO5_SHIFT, | |
1592 | .module_offs = OMAP3430_PER_MOD, | |
1593 | .idlest_reg_id = 1, | |
1594 | .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, | |
1595 | }, | |
1596 | }, | |
1597 | .slaves = omap3xxx_gpio5_slaves, | |
1598 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves), | |
1599 | .class = &omap3xxx_gpio_hwmod_class, | |
1600 | .dev_attr = &gpio_dev_attr, | |
1601 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1602 | }; | |
1603 | ||
1604 | /* gpio6 */ | |
1605 | static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { | |
1606 | { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ | |
1607 | }; | |
1608 | ||
1609 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { | |
1610 | { .role = "dbclk", .clk = "gpio6_dbck", }, | |
1611 | }; | |
1612 | ||
1613 | static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = { | |
1614 | &omap3xxx_l4_per__gpio6, | |
1615 | }; | |
1616 | ||
1617 | static struct omap_hwmod omap3xxx_gpio6_hwmod = { | |
1618 | .name = "gpio6", | |
1619 | .mpu_irqs = omap3xxx_gpio6_irqs, | |
1620 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs), | |
1621 | .main_clk = "gpio6_ick", | |
1622 | .opt_clks = gpio6_opt_clks, | |
1623 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), | |
1624 | .prcm = { | |
1625 | .omap2 = { | |
1626 | .prcm_reg_id = 1, | |
1627 | .module_bit = OMAP3430_EN_GPIO6_SHIFT, | |
1628 | .module_offs = OMAP3430_PER_MOD, | |
1629 | .idlest_reg_id = 1, | |
1630 | .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, | |
1631 | }, | |
1632 | }, | |
1633 | .slaves = omap3xxx_gpio6_slaves, | |
1634 | .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves), | |
1635 | .class = &omap3xxx_gpio_hwmod_class, | |
1636 | .dev_attr = &gpio_dev_attr, | |
1637 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1638 | }; | |
1639 | ||
01438ab6 MK |
1640 | /* dma_system -> L3 */ |
1641 | static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { | |
1642 | .master = &omap3xxx_dma_system_hwmod, | |
1643 | .slave = &omap3xxx_l3_main_hwmod, | |
1644 | .clk = "core_l3_ick", | |
1645 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1646 | }; | |
1647 | ||
1648 | /* dma attributes */ | |
1649 | static struct omap_dma_dev_attr dma_dev_attr = { | |
1650 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | | |
1651 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, | |
1652 | .lch_count = 32, | |
1653 | }; | |
1654 | ||
1655 | static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { | |
1656 | .rev_offs = 0x0000, | |
1657 | .sysc_offs = 0x002c, | |
1658 | .syss_offs = 0x0028, | |
1659 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | | |
1660 | SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | | |
1661 | SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), | |
1662 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
1663 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
1664 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1665 | }; | |
1666 | ||
1667 | static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { | |
1668 | .name = "dma", | |
1669 | .sysc = &omap3xxx_dma_sysc, | |
1670 | }; | |
1671 | ||
1672 | /* dma_system */ | |
1673 | static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = { | |
1674 | { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ | |
1675 | { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ | |
1676 | { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ | |
1677 | { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ | |
1678 | }; | |
1679 | ||
1680 | static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { | |
1681 | { | |
1682 | .pa_start = 0x48056000, | |
1683 | .pa_end = 0x4a0560ff, | |
1684 | .flags = ADDR_TYPE_RT | |
1685 | }, | |
1686 | }; | |
1687 | ||
1688 | /* dma_system master ports */ | |
1689 | static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = { | |
1690 | &omap3xxx_dma_system__l3, | |
1691 | }; | |
1692 | ||
1693 | /* l4_cfg -> dma_system */ | |
1694 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { | |
1695 | .master = &omap3xxx_l4_core_hwmod, | |
1696 | .slave = &omap3xxx_dma_system_hwmod, | |
1697 | .clk = "core_l4_ick", | |
1698 | .addr = omap3xxx_dma_system_addrs, | |
1699 | .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs), | |
1700 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1701 | }; | |
1702 | ||
1703 | /* dma_system slave ports */ | |
1704 | static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = { | |
1705 | &omap3xxx_l4_core__dma_system, | |
1706 | }; | |
1707 | ||
1708 | static struct omap_hwmod omap3xxx_dma_system_hwmod = { | |
1709 | .name = "dma", | |
1710 | .class = &omap3xxx_dma_hwmod_class, | |
1711 | .mpu_irqs = omap3xxx_dma_system_irqs, | |
1712 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs), | |
1713 | .main_clk = "core_l3_ick", | |
1714 | .prcm = { | |
1715 | .omap2 = { | |
1716 | .module_offs = CORE_MOD, | |
1717 | .prcm_reg_id = 1, | |
1718 | .module_bit = OMAP3430_ST_SDMA_SHIFT, | |
1719 | .idlest_reg_id = 1, | |
1720 | .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, | |
1721 | }, | |
1722 | }, | |
1723 | .slaves = omap3xxx_dma_system_slaves, | |
1724 | .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves), | |
1725 | .masters = omap3xxx_dma_system_masters, | |
1726 | .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), | |
1727 | .dev_attr = &dma_dev_attr, | |
1728 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
1729 | .flags = HWMOD_NO_IDLEST, | |
1730 | }; | |
1731 | ||
d3442726 TG |
1732 | /* SR common */ |
1733 | static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { | |
1734 | .clkact_shift = 20, | |
1735 | }; | |
1736 | ||
1737 | static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { | |
1738 | .sysc_offs = 0x24, | |
1739 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), | |
1740 | .clockact = CLOCKACT_TEST_ICLK, | |
1741 | .sysc_fields = &omap34xx_sr_sysc_fields, | |
1742 | }; | |
1743 | ||
1744 | static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { | |
1745 | .name = "smartreflex", | |
1746 | .sysc = &omap34xx_sr_sysc, | |
1747 | .rev = 1, | |
1748 | }; | |
1749 | ||
1750 | static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { | |
1751 | .sidle_shift = 24, | |
1752 | .enwkup_shift = 26 | |
1753 | }; | |
1754 | ||
1755 | static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { | |
1756 | .sysc_offs = 0x38, | |
1757 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1758 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | | |
1759 | SYSC_NO_CACHE), | |
1760 | .sysc_fields = &omap36xx_sr_sysc_fields, | |
1761 | }; | |
1762 | ||
1763 | static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { | |
1764 | .name = "smartreflex", | |
1765 | .sysc = &omap36xx_sr_sysc, | |
1766 | .rev = 2, | |
1767 | }; | |
1768 | ||
1769 | /* SR1 */ | |
1770 | static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = { | |
1771 | &omap3_l4_core__sr1, | |
1772 | }; | |
1773 | ||
1774 | static struct omap_hwmod omap34xx_sr1_hwmod = { | |
1775 | .name = "sr1_hwmod", | |
1776 | .class = &omap34xx_smartreflex_hwmod_class, | |
1777 | .main_clk = "sr1_fck", | |
1778 | .vdd_name = "mpu", | |
1779 | .prcm = { | |
1780 | .omap2 = { | |
1781 | .prcm_reg_id = 1, | |
1782 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1783 | .module_offs = WKUP_MOD, | |
1784 | .idlest_reg_id = 1, | |
1785 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1786 | }, | |
1787 | }, | |
1788 | .slaves = omap3_sr1_slaves, | |
1789 | .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), | |
1790 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | | |
1791 | CHIP_IS_OMAP3430ES3_0 | | |
1792 | CHIP_IS_OMAP3430ES3_1), | |
1793 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
1794 | }; | |
1795 | ||
1796 | static struct omap_hwmod omap36xx_sr1_hwmod = { | |
1797 | .name = "sr1_hwmod", | |
1798 | .class = &omap36xx_smartreflex_hwmod_class, | |
1799 | .main_clk = "sr1_fck", | |
1800 | .vdd_name = "mpu", | |
1801 | .prcm = { | |
1802 | .omap2 = { | |
1803 | .prcm_reg_id = 1, | |
1804 | .module_bit = OMAP3430_EN_SR1_SHIFT, | |
1805 | .module_offs = WKUP_MOD, | |
1806 | .idlest_reg_id = 1, | |
1807 | .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, | |
1808 | }, | |
1809 | }, | |
1810 | .slaves = omap3_sr1_slaves, | |
1811 | .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves), | |
1812 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), | |
1813 | }; | |
1814 | ||
1815 | /* SR2 */ | |
1816 | static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = { | |
1817 | &omap3_l4_core__sr2, | |
1818 | }; | |
1819 | ||
1820 | static struct omap_hwmod omap34xx_sr2_hwmod = { | |
1821 | .name = "sr2_hwmod", | |
1822 | .class = &omap34xx_smartreflex_hwmod_class, | |
1823 | .main_clk = "sr2_fck", | |
1824 | .vdd_name = "core", | |
1825 | .prcm = { | |
1826 | .omap2 = { | |
1827 | .prcm_reg_id = 1, | |
1828 | .module_bit = OMAP3430_EN_SR2_SHIFT, | |
1829 | .module_offs = WKUP_MOD, | |
1830 | .idlest_reg_id = 1, | |
1831 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, | |
1832 | }, | |
1833 | }, | |
1834 | .slaves = omap3_sr2_slaves, | |
1835 | .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), | |
1836 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 | | |
1837 | CHIP_IS_OMAP3430ES3_0 | | |
1838 | CHIP_IS_OMAP3430ES3_1), | |
1839 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | |
1840 | }; | |
1841 | ||
1842 | static struct omap_hwmod omap36xx_sr2_hwmod = { | |
1843 | .name = "sr2_hwmod", | |
1844 | .class = &omap36xx_smartreflex_hwmod_class, | |
1845 | .main_clk = "sr2_fck", | |
1846 | .vdd_name = "core", | |
1847 | .prcm = { | |
1848 | .omap2 = { | |
1849 | .prcm_reg_id = 1, | |
1850 | .module_bit = OMAP3430_EN_SR2_SHIFT, | |
1851 | .module_offs = WKUP_MOD, | |
1852 | .idlest_reg_id = 1, | |
1853 | .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, | |
1854 | }, | |
1855 | }, | |
1856 | .slaves = omap3_sr2_slaves, | |
1857 | .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves), | |
1858 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), | |
1859 | }; | |
1860 | ||
0f616a4e C |
1861 | /* l4 core -> mcspi1 interface */ |
1862 | static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = { | |
1863 | { | |
1864 | .pa_start = 0x48098000, | |
1865 | .pa_end = 0x480980ff, | |
1866 | .flags = ADDR_TYPE_RT, | |
1867 | }, | |
1868 | }; | |
1869 | ||
1870 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { | |
1871 | .master = &omap3xxx_l4_core_hwmod, | |
1872 | .slave = &omap34xx_mcspi1, | |
1873 | .clk = "mcspi1_ick", | |
1874 | .addr = omap34xx_mcspi1_addr_space, | |
1875 | .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space), | |
1876 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1877 | }; | |
1878 | ||
1879 | /* l4 core -> mcspi2 interface */ | |
1880 | static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = { | |
1881 | { | |
1882 | .pa_start = 0x4809a000, | |
1883 | .pa_end = 0x4809a0ff, | |
1884 | .flags = ADDR_TYPE_RT, | |
1885 | }, | |
1886 | }; | |
1887 | ||
1888 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { | |
1889 | .master = &omap3xxx_l4_core_hwmod, | |
1890 | .slave = &omap34xx_mcspi2, | |
1891 | .clk = "mcspi2_ick", | |
1892 | .addr = omap34xx_mcspi2_addr_space, | |
1893 | .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space), | |
1894 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1895 | }; | |
1896 | ||
1897 | /* l4 core -> mcspi3 interface */ | |
1898 | static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = { | |
1899 | { | |
1900 | .pa_start = 0x480b8000, | |
1901 | .pa_end = 0x480b80ff, | |
1902 | .flags = ADDR_TYPE_RT, | |
1903 | }, | |
1904 | }; | |
1905 | ||
1906 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { | |
1907 | .master = &omap3xxx_l4_core_hwmod, | |
1908 | .slave = &omap34xx_mcspi3, | |
1909 | .clk = "mcspi3_ick", | |
1910 | .addr = omap34xx_mcspi3_addr_space, | |
1911 | .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space), | |
1912 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1913 | }; | |
1914 | ||
1915 | /* l4 core -> mcspi4 interface */ | |
1916 | static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { | |
1917 | { | |
1918 | .pa_start = 0x480ba000, | |
1919 | .pa_end = 0x480ba0ff, | |
1920 | .flags = ADDR_TYPE_RT, | |
1921 | }, | |
1922 | }; | |
1923 | ||
1924 | static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { | |
1925 | .master = &omap3xxx_l4_core_hwmod, | |
1926 | .slave = &omap34xx_mcspi4, | |
1927 | .clk = "mcspi4_ick", | |
1928 | .addr = omap34xx_mcspi4_addr_space, | |
1929 | .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space), | |
1930 | .user = OCP_USER_MPU | OCP_USER_SDMA, | |
1931 | }; | |
1932 | ||
1933 | /* | |
1934 | * 'mcspi' class | |
1935 | * multichannel serial port interface (mcspi) / master/slave synchronous serial | |
1936 | * bus | |
1937 | */ | |
1938 | ||
1939 | static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { | |
1940 | .rev_offs = 0x0000, | |
1941 | .sysc_offs = 0x0010, | |
1942 | .syss_offs = 0x0014, | |
1943 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | | |
1944 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
1945 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), | |
1946 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), | |
1947 | .sysc_fields = &omap_hwmod_sysc_type1, | |
1948 | }; | |
1949 | ||
1950 | static struct omap_hwmod_class omap34xx_mcspi_class = { | |
1951 | .name = "mcspi", | |
1952 | .sysc = &omap34xx_mcspi_sysc, | |
1953 | .rev = OMAP3_MCSPI_REV, | |
1954 | }; | |
1955 | ||
1956 | /* mcspi1 */ | |
1957 | static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = { | |
1958 | { .name = "irq", .irq = 65 }, | |
1959 | }; | |
1960 | ||
1961 | static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = { | |
1962 | { .name = "tx0", .dma_req = 35 }, | |
1963 | { .name = "rx0", .dma_req = 36 }, | |
1964 | { .name = "tx1", .dma_req = 37 }, | |
1965 | { .name = "rx1", .dma_req = 38 }, | |
1966 | { .name = "tx2", .dma_req = 39 }, | |
1967 | { .name = "rx2", .dma_req = 40 }, | |
1968 | { .name = "tx3", .dma_req = 41 }, | |
1969 | { .name = "rx3", .dma_req = 42 }, | |
1970 | }; | |
1971 | ||
1972 | static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { | |
1973 | &omap34xx_l4_core__mcspi1, | |
1974 | }; | |
1975 | ||
1976 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { | |
1977 | .num_chipselect = 4, | |
1978 | }; | |
1979 | ||
1980 | static struct omap_hwmod omap34xx_mcspi1 = { | |
1981 | .name = "mcspi1", | |
1982 | .mpu_irqs = omap34xx_mcspi1_mpu_irqs, | |
1983 | .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs), | |
1984 | .sdma_reqs = omap34xx_mcspi1_sdma_reqs, | |
1985 | .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs), | |
1986 | .main_clk = "mcspi1_fck", | |
1987 | .prcm = { | |
1988 | .omap2 = { | |
1989 | .module_offs = CORE_MOD, | |
1990 | .prcm_reg_id = 1, | |
1991 | .module_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1992 | .idlest_reg_id = 1, | |
1993 | .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, | |
1994 | }, | |
1995 | }, | |
1996 | .slaves = omap34xx_mcspi1_slaves, | |
1997 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves), | |
1998 | .class = &omap34xx_mcspi_class, | |
1999 | .dev_attr = &omap_mcspi1_dev_attr, | |
2000 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
2001 | }; | |
2002 | ||
2003 | /* mcspi2 */ | |
2004 | static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = { | |
2005 | { .name = "irq", .irq = 66 }, | |
2006 | }; | |
2007 | ||
2008 | static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = { | |
2009 | { .name = "tx0", .dma_req = 43 }, | |
2010 | { .name = "rx0", .dma_req = 44 }, | |
2011 | { .name = "tx1", .dma_req = 45 }, | |
2012 | { .name = "rx1", .dma_req = 46 }, | |
2013 | }; | |
2014 | ||
2015 | static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { | |
2016 | &omap34xx_l4_core__mcspi2, | |
2017 | }; | |
2018 | ||
2019 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { | |
2020 | .num_chipselect = 2, | |
2021 | }; | |
2022 | ||
2023 | static struct omap_hwmod omap34xx_mcspi2 = { | |
2024 | .name = "mcspi2", | |
2025 | .mpu_irqs = omap34xx_mcspi2_mpu_irqs, | |
2026 | .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs), | |
2027 | .sdma_reqs = omap34xx_mcspi2_sdma_reqs, | |
2028 | .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs), | |
2029 | .main_clk = "mcspi2_fck", | |
2030 | .prcm = { | |
2031 | .omap2 = { | |
2032 | .module_offs = CORE_MOD, | |
2033 | .prcm_reg_id = 1, | |
2034 | .module_bit = OMAP3430_EN_MCSPI2_SHIFT, | |
2035 | .idlest_reg_id = 1, | |
2036 | .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, | |
2037 | }, | |
2038 | }, | |
2039 | .slaves = omap34xx_mcspi2_slaves, | |
2040 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves), | |
2041 | .class = &omap34xx_mcspi_class, | |
2042 | .dev_attr = &omap_mcspi2_dev_attr, | |
2043 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
2044 | }; | |
2045 | ||
2046 | /* mcspi3 */ | |
2047 | static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { | |
2048 | { .name = "irq", .irq = 91 }, /* 91 */ | |
2049 | }; | |
2050 | ||
2051 | static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { | |
2052 | { .name = "tx0", .dma_req = 15 }, | |
2053 | { .name = "rx0", .dma_req = 16 }, | |
2054 | { .name = "tx1", .dma_req = 23 }, | |
2055 | { .name = "rx1", .dma_req = 24 }, | |
2056 | }; | |
2057 | ||
2058 | static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { | |
2059 | &omap34xx_l4_core__mcspi3, | |
2060 | }; | |
2061 | ||
2062 | static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { | |
2063 | .num_chipselect = 2, | |
2064 | }; | |
2065 | ||
2066 | static struct omap_hwmod omap34xx_mcspi3 = { | |
2067 | .name = "mcspi3", | |
2068 | .mpu_irqs = omap34xx_mcspi3_mpu_irqs, | |
2069 | .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs), | |
2070 | .sdma_reqs = omap34xx_mcspi3_sdma_reqs, | |
2071 | .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs), | |
2072 | .main_clk = "mcspi3_fck", | |
2073 | .prcm = { | |
2074 | .omap2 = { | |
2075 | .module_offs = CORE_MOD, | |
2076 | .prcm_reg_id = 1, | |
2077 | .module_bit = OMAP3430_EN_MCSPI3_SHIFT, | |
2078 | .idlest_reg_id = 1, | |
2079 | .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, | |
2080 | }, | |
2081 | }, | |
2082 | .slaves = omap34xx_mcspi3_slaves, | |
2083 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves), | |
2084 | .class = &omap34xx_mcspi_class, | |
2085 | .dev_attr = &omap_mcspi3_dev_attr, | |
2086 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
2087 | }; | |
2088 | ||
2089 | /* SPI4 */ | |
2090 | static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { | |
2091 | { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ | |
2092 | }; | |
2093 | ||
2094 | static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { | |
2095 | { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ | |
2096 | { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ | |
2097 | }; | |
2098 | ||
2099 | static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { | |
2100 | &omap34xx_l4_core__mcspi4, | |
2101 | }; | |
2102 | ||
2103 | static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { | |
2104 | .num_chipselect = 1, | |
2105 | }; | |
2106 | ||
2107 | static struct omap_hwmod omap34xx_mcspi4 = { | |
2108 | .name = "mcspi4", | |
2109 | .mpu_irqs = omap34xx_mcspi4_mpu_irqs, | |
2110 | .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs), | |
2111 | .sdma_reqs = omap34xx_mcspi4_sdma_reqs, | |
2112 | .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs), | |
2113 | .main_clk = "mcspi4_fck", | |
2114 | .prcm = { | |
2115 | .omap2 = { | |
2116 | .module_offs = CORE_MOD, | |
2117 | .prcm_reg_id = 1, | |
2118 | .module_bit = OMAP3430_EN_MCSPI4_SHIFT, | |
2119 | .idlest_reg_id = 1, | |
2120 | .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, | |
2121 | }, | |
2122 | }, | |
2123 | .slaves = omap34xx_mcspi4_slaves, | |
2124 | .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves), | |
2125 | .class = &omap34xx_mcspi_class, | |
2126 | .dev_attr = &omap_mcspi4_dev_attr, | |
2127 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | |
2128 | }; | |
2129 | ||
870ea2b8 HH |
2130 | /* |
2131 | * usbhsotg | |
2132 | */ | |
2133 | static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { | |
2134 | .rev_offs = 0x0400, | |
2135 | .sysc_offs = 0x0404, | |
2136 | .syss_offs = 0x0408, | |
2137 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| | |
2138 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | | |
2139 | SYSC_HAS_AUTOIDLE), | |
2140 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | |
2141 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), | |
2142 | .sysc_fields = &omap_hwmod_sysc_type1, | |
2143 | }; | |
2144 | ||
2145 | static struct omap_hwmod_class usbotg_class = { | |
2146 | .name = "usbotg", | |
2147 | .sysc = &omap3xxx_usbhsotg_sysc, | |
2148 | }; | |
870ea2b8 HH |
2149 | /* usb_otg_hs */ |
2150 | static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { | |
2151 | ||
2152 | { .name = "mc", .irq = 92 }, | |
2153 | { .name = "dma", .irq = 93 }, | |
2154 | }; | |
2155 | ||
2156 | static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |
2157 | .name = "usb_otg_hs", | |
2158 | .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, | |
2159 | .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs), | |
2160 | .main_clk = "hsotgusb_ick", | |
2161 | .prcm = { | |
2162 | .omap2 = { | |
2163 | .prcm_reg_id = 1, | |
2164 | .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | |
2165 | .module_offs = CORE_MOD, | |
2166 | .idlest_reg_id = 1, | |
2167 | .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, | |
2168 | .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT | |
2169 | }, | |
2170 | }, | |
2171 | .masters = omap3xxx_usbhsotg_masters, | |
2172 | .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters), | |
2173 | .slaves = omap3xxx_usbhsotg_slaves, | |
2174 | .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves), | |
2175 | .class = &usbotg_class, | |
2176 | ||
2177 | /* | |
2178 | * Erratum ID: i479 idle_req / idle_ack mechanism potentially | |
2179 | * broken when autoidle is enabled | |
2180 | * workaround is to disable the autoidle bit at module level. | |
2181 | */ | |
2182 | .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | |
2183 | | HWMOD_SWSUP_MSTANDBY, | |
2184 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | |
2185 | }; | |
04aa67de | 2186 | |
273ff8c3 HH |
2187 | /* usb_otg_hs */ |
2188 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | |
2189 | ||
2190 | { .name = "mc", .irq = 71 }, | |
2191 | }; | |
2192 | ||
2193 | static struct omap_hwmod_class am35xx_usbotg_class = { | |
2194 | .name = "am35xx_usbotg", | |
2195 | .sysc = NULL, | |
2196 | }; | |
2197 | ||
2198 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { | |
2199 | .name = "am35x_otg_hs", | |
2200 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | |
2201 | .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs), | |
2202 | .main_clk = NULL, | |
2203 | .prcm = { | |
2204 | .omap2 = { | |
2205 | }, | |
2206 | }, | |
2207 | .masters = am35xx_usbhsotg_masters, | |
2208 | .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters), | |
2209 | .slaves = am35xx_usbhsotg_slaves, | |
2210 | .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves), | |
2211 | .class = &am35xx_usbotg_class, | |
2212 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1) | |
2213 | }; | |
870ea2b8 | 2214 | |
7359154e | 2215 | static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { |
4a7cf90a | 2216 | &omap3xxx_l3_main_hwmod, |
7359154e PW |
2217 | &omap3xxx_l4_core_hwmod, |
2218 | &omap3xxx_l4_per_hwmod, | |
2219 | &omap3xxx_l4_wkup_hwmod, | |
2220 | &omap3xxx_mpu_hwmod, | |
540064bf | 2221 | &omap3xxx_iva_hwmod, |
6b667f88 | 2222 | &omap3xxx_wd_timer2_hwmod, |
046465b7 KH |
2223 | &omap3xxx_uart1_hwmod, |
2224 | &omap3xxx_uart2_hwmod, | |
2225 | &omap3xxx_uart3_hwmod, | |
2226 | &omap3xxx_uart4_hwmod, | |
e04d9e1e SG |
2227 | /* dss class */ |
2228 | &omap3430es1_dss_core_hwmod, | |
2229 | &omap3xxx_dss_core_hwmod, | |
2230 | &omap3xxx_dss_dispc_hwmod, | |
2231 | &omap3xxx_dss_dsi1_hwmod, | |
2232 | &omap3xxx_dss_rfbi_hwmod, | |
2233 | &omap3xxx_dss_venc_hwmod, | |
2234 | ||
2235 | /* i2c class */ | |
4fe20e97 RN |
2236 | &omap3xxx_i2c1_hwmod, |
2237 | &omap3xxx_i2c2_hwmod, | |
2238 | &omap3xxx_i2c3_hwmod, | |
d3442726 TG |
2239 | &omap34xx_sr1_hwmod, |
2240 | &omap34xx_sr2_hwmod, | |
2241 | &omap36xx_sr1_hwmod, | |
2242 | &omap36xx_sr2_hwmod, | |
2243 | ||
70034d38 VC |
2244 | |
2245 | /* gpio class */ | |
2246 | &omap3xxx_gpio1_hwmod, | |
2247 | &omap3xxx_gpio2_hwmod, | |
2248 | &omap3xxx_gpio3_hwmod, | |
2249 | &omap3xxx_gpio4_hwmod, | |
2250 | &omap3xxx_gpio5_hwmod, | |
2251 | &omap3xxx_gpio6_hwmod, | |
01438ab6 MK |
2252 | |
2253 | /* dma_system class*/ | |
2254 | &omap3xxx_dma_system_hwmod, | |
0f616a4e C |
2255 | |
2256 | /* mcspi class */ | |
2257 | &omap34xx_mcspi1, | |
2258 | &omap34xx_mcspi2, | |
2259 | &omap34xx_mcspi3, | |
2260 | &omap34xx_mcspi4, | |
04aa67de | 2261 | |
870ea2b8 HH |
2262 | /* usbotg class */ |
2263 | &omap3xxx_usbhsotg_hwmod, | |
2264 | ||
273ff8c3 HH |
2265 | /* usbotg for am35x */ |
2266 | &am35xx_usbhsotg_hwmod, | |
2267 | ||
7359154e PW |
2268 | NULL, |
2269 | }; | |
2270 | ||
2271 | int __init omap3xxx_hwmod_init(void) | |
2272 | { | |
2273 | return omap_hwmod_init(omap3xxx_hwmods); | |
2274 | } |