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Commit | Line | Data |
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6f88e9bc KH |
1 | /* |
2 | * pm.c - Common OMAP2+ power management-related code | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments, Inc. | |
5 | * Copyright (C) 2010 Nokia Corporation | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/err.h> | |
1482d8be | 16 | #include <linux/opp.h> |
dc28094b | 17 | #include <linux/export.h> |
6f88e9bc KH |
18 | |
19 | #include <plat/omap-pm.h> | |
20 | #include <plat/omap_device.h> | |
4e65331c | 21 | #include "common.h" |
6f88e9bc | 22 | |
e1d6f472 | 23 | #include "voltage.h" |
72e06d08 | 24 | #include "powerdomain.h" |
1540f214 | 25 | #include "clockdomain.h" |
0c0a5d61 | 26 | #include "pm.h" |
46232a36 | 27 | #include "twl-common.h" |
eb6a2c75 | 28 | |
6f88e9bc KH |
29 | static struct omap_device_pm_latency *pm_lats; |
30 | ||
766e7afc | 31 | static int _init_omap_device(char *name) |
6f88e9bc KH |
32 | { |
33 | struct omap_hwmod *oh; | |
3528c58e | 34 | struct platform_device *pdev; |
6f88e9bc KH |
35 | |
36 | oh = omap_hwmod_lookup(name); | |
37 | if (WARN(!oh, "%s: could not find omap_hwmod for %s\n", | |
38 | __func__, name)) | |
39 | return -ENODEV; | |
40 | ||
3528c58e KH |
41 | pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false); |
42 | if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n", | |
6f88e9bc KH |
43 | __func__, name)) |
44 | return -ENODEV; | |
45 | ||
6f88e9bc KH |
46 | return 0; |
47 | } | |
48 | ||
49 | /* | |
50 | * Build omap_devices for processors and bus. | |
51 | */ | |
52 | static void omap2_init_processor_devices(void) | |
53 | { | |
766e7afc | 54 | _init_omap_device("mpu"); |
2de0baef | 55 | if (omap3_has_iva()) |
766e7afc | 56 | _init_omap_device("iva"); |
2de0baef | 57 | |
cbf27660 | 58 | if (cpu_is_omap44xx()) { |
766e7afc BC |
59 | _init_omap_device("l3_main_1"); |
60 | _init_omap_device("dsp"); | |
61 | _init_omap_device("iva"); | |
cbf27660 | 62 | } else { |
766e7afc | 63 | _init_omap_device("l3_main"); |
cbf27660 | 64 | } |
6f88e9bc KH |
65 | } |
66 | ||
71a488db RN |
67 | /* Types of sleep_switch used in omap_set_pwrdm_state */ |
68 | #define FORCEWAKEUP_SWITCH 0 | |
69 | #define LOWPOWERSTATE_SWITCH 1 | |
70 | ||
eb6a2c75 SS |
71 | /* |
72 | * This sets pwrdm state (other than mpu & core. Currently only ON & | |
33de32b3 | 73 | * RET are supported. |
eb6a2c75 SS |
74 | */ |
75 | int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state) | |
76 | { | |
77 | u32 cur_state; | |
6349b96b | 78 | int sleep_switch = -1; |
eb6a2c75 | 79 | int ret = 0; |
b86cfb52 | 80 | int hwsup = 0; |
eb6a2c75 SS |
81 | |
82 | if (pwrdm == NULL || IS_ERR(pwrdm)) | |
83 | return -EINVAL; | |
84 | ||
85 | while (!(pwrdm->pwrsts & (1 << state))) { | |
86 | if (state == PWRDM_POWER_OFF) | |
87 | return ret; | |
88 | state--; | |
89 | } | |
90 | ||
91 | cur_state = pwrdm_read_next_pwrst(pwrdm); | |
92 | if (cur_state == state) | |
93 | return ret; | |
94 | ||
95 | if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { | |
71a488db RN |
96 | if ((pwrdm_read_pwrst(pwrdm) > state) && |
97 | (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) { | |
98 | sleep_switch = LOWPOWERSTATE_SWITCH; | |
99 | } else { | |
b86cfb52 | 100 | hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]); |
68b921ad | 101 | clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); |
71a488db RN |
102 | sleep_switch = FORCEWAKEUP_SWITCH; |
103 | } | |
eb6a2c75 SS |
104 | } |
105 | ||
106 | ret = pwrdm_set_next_pwrst(pwrdm, state); | |
107 | if (ret) { | |
e9a5190a JH |
108 | pr_err("%s: unable to set state of powerdomain: %s\n", |
109 | __func__, pwrdm->name); | |
eb6a2c75 SS |
110 | goto err; |
111 | } | |
112 | ||
71a488db RN |
113 | switch (sleep_switch) { |
114 | case FORCEWAKEUP_SWITCH: | |
b86cfb52 | 115 | if (hwsup) |
5cd1937b | 116 | clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); |
33de32b3 | 117 | else |
68b921ad | 118 | clkdm_sleep(pwrdm->pwrdm_clkdms[0]); |
71a488db RN |
119 | break; |
120 | case LOWPOWERSTATE_SWITCH: | |
121 | pwrdm_set_lowpwrstchange(pwrdm); | |
122 | break; | |
123 | default: | |
124 | return ret; | |
eb6a2c75 SS |
125 | } |
126 | ||
71a488db | 127 | pwrdm_state_switch(pwrdm); |
eb6a2c75 SS |
128 | err: |
129 | return ret; | |
130 | } | |
131 | ||
1482d8be | 132 | /* |
1e2d2df3 | 133 | * This API is to be called during init to set the various voltage |
1482d8be TG |
134 | * domains to the voltage as per the opp table. Typically we boot up |
135 | * at the nominal voltage. So this function finds out the rate of | |
136 | * the clock associated with the voltage domain, finds out the correct | |
1e2d2df3 | 137 | * opp entry and sets the voltage domain to the voltage specified |
1482d8be TG |
138 | * in the opp entry |
139 | */ | |
140 | static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, | |
0f7aa005 | 141 | const char *oh_name) |
1482d8be TG |
142 | { |
143 | struct voltagedomain *voltdm; | |
144 | struct clk *clk; | |
145 | struct opp *opp; | |
146 | unsigned long freq, bootup_volt; | |
0f7aa005 | 147 | struct device *dev; |
1482d8be | 148 | |
0f7aa005 | 149 | if (!vdd_name || !clk_name || !oh_name) { |
e9a5190a | 150 | pr_err("%s: invalid parameters\n", __func__); |
1482d8be TG |
151 | goto exit; |
152 | } | |
153 | ||
0f7aa005 BC |
154 | dev = omap_device_get_by_hwmod_name(oh_name); |
155 | if (IS_ERR(dev)) { | |
156 | pr_err("%s: Unable to get dev pointer for hwmod %s\n", | |
157 | __func__, oh_name); | |
158 | goto exit; | |
159 | } | |
160 | ||
81a60482 | 161 | voltdm = voltdm_lookup(vdd_name); |
1482d8be | 162 | if (IS_ERR(voltdm)) { |
e9a5190a | 163 | pr_err("%s: unable to get vdd pointer for vdd_%s\n", |
1482d8be TG |
164 | __func__, vdd_name); |
165 | goto exit; | |
166 | } | |
167 | ||
168 | clk = clk_get(NULL, clk_name); | |
169 | if (IS_ERR(clk)) { | |
e9a5190a | 170 | pr_err("%s: unable to get clk %s\n", __func__, clk_name); |
1482d8be TG |
171 | goto exit; |
172 | } | |
173 | ||
174 | freq = clk->rate; | |
175 | clk_put(clk); | |
176 | ||
6369fd41 | 177 | rcu_read_lock(); |
1482d8be TG |
178 | opp = opp_find_freq_ceil(dev, &freq); |
179 | if (IS_ERR(opp)) { | |
6369fd41 | 180 | rcu_read_unlock(); |
e9a5190a | 181 | pr_err("%s: unable to find boot up OPP for vdd_%s\n", |
1482d8be TG |
182 | __func__, vdd_name); |
183 | goto exit; | |
184 | } | |
185 | ||
186 | bootup_volt = opp_get_voltage(opp); | |
6369fd41 | 187 | rcu_read_unlock(); |
1482d8be | 188 | if (!bootup_volt) { |
e9a5190a | 189 | pr_err("%s: unable to find voltage corresponding " |
1482d8be TG |
190 | "to the bootup OPP for vdd_%s\n", __func__, vdd_name); |
191 | goto exit; | |
192 | } | |
193 | ||
5e5651be | 194 | voltdm_scale(voltdm, bootup_volt); |
1482d8be TG |
195 | return 0; |
196 | ||
197 | exit: | |
e9a5190a | 198 | pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name); |
1482d8be TG |
199 | return -EINVAL; |
200 | } | |
201 | ||
202 | static void __init omap3_init_voltages(void) | |
203 | { | |
204 | if (!cpu_is_omap34xx()) | |
205 | return; | |
206 | ||
0f7aa005 BC |
207 | omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu"); |
208 | omap2_set_init_voltage("core", "l3_ick", "l3_main"); | |
1482d8be TG |
209 | } |
210 | ||
1376ee1d TG |
211 | static void __init omap4_init_voltages(void) |
212 | { | |
213 | if (!cpu_is_omap44xx()) | |
214 | return; | |
215 | ||
0f7aa005 BC |
216 | omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu"); |
217 | omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1"); | |
218 | omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva"); | |
1376ee1d TG |
219 | } |
220 | ||
6f88e9bc KH |
221 | static int __init omap2_common_pm_init(void) |
222 | { | |
476b679a BC |
223 | if (!of_have_populated_dt()) |
224 | omap2_init_processor_devices(); | |
6f88e9bc KH |
225 | omap_pm_if_init(); |
226 | ||
227 | return 0; | |
228 | } | |
1cbbe37a | 229 | postcore_initcall(omap2_common_pm_init); |
6f88e9bc | 230 | |
2f34ce81 TG |
231 | static int __init omap2_common_pm_late_init(void) |
232 | { | |
fbc319f6 | 233 | /* Init the voltage layer */ |
46232a36 | 234 | omap_pmic_late_init(); |
2f34ce81 | 235 | omap_voltage_late_init(); |
1482d8be TG |
236 | |
237 | /* Initialize the voltages */ | |
238 | omap3_init_voltages(); | |
1376ee1d | 239 | omap4_init_voltages(); |
1482d8be | 240 | |
fbc319f6 | 241 | /* Smartreflex device init */ |
0c0a5d61 | 242 | omap_devinit_smartreflex(); |
2f34ce81 TG |
243 | |
244 | return 0; | |
245 | } | |
246 | late_initcall(omap2_common_pm_late_init); |