[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-omap2 / pm24xx.c

/*
 * OMAP2 Power Management Routines
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Copyright (C) 2006-2008 Nokia Corporation
 *
 * Written by:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Tony Lindgren
 * Juha Yrjola
 * Amit Kucheria <amit.kucheria@nokia.com>
 * Igor Stoppa <igor.stoppa@nokia.com>
 *
 * Based on pm.c for omap1
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/time.h>
#include <linux/gpio.h>
#include <linux/console.h>

#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>

#include <mach/irqs.h>
#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/dma.h>
#include <plat/board.h>

#include "prm.h"
#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "pm.h"
#include "control.h"

#include <plat/powerdomain.h>
#include <plat/clockdomain.h>

static void (*omap2_sram_idle)(void);
static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
				  void __iomem *sdrc_power);

static struct powerdomain *mpu_pwrdm, *core_pwrdm;
static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;

static struct clk *osc_ck, *emul_ck;

static int omap2_fclks_active(void)
{
	u32 f1, f2;

	f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);

	/* Ignore UART clocks.  These are handled by UART core (serial.c) */
	f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
	f2 &= ~OMAP24XX_EN_UART3_MASK;

	if (f1 | f2)
		return 1;
	return 0;
}

static void omap2_enter_full_retention(void)
{
	u32 l;
	struct timespec ts_preidle, ts_postidle, ts_idle;

	/* There is 1 reference hold for all children of the oscillator
	 * clock, the following will remove it. If no one else uses the
	 * oscillator itself it will be disabled if/when we enter retention
	 * mode.
	 */
	clk_disable(osc_ck);

	/* Clear old wake-up events */
	/* REVISIT: These write to reserved bits? */
	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

	/*
	 * Set MPU powerdomain's next power state to RETENTION;
	 * preserve logic state during retention
	 */
	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Workaround to kill USB */
	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);

	omap2_gpio_prepare_for_idle(PWRDM_POWER_RET);

	if (omap2_pm_debug) {
		omap2_pm_dump(0, 0, 0);
		getnstimeofday(&ts_preidle);
	}

	/* One last check for pending IRQs to avoid extra latency due
	 * to sleeping unnecessarily. */
	if (omap_irq_pending())
		goto no_sleep;

	/* Block console output in case it is on one of the OMAP UARTs */
	if (try_acquire_console_sem())
		goto no_sleep;

	omap_uart_prepare_idle(0);
	omap_uart_prepare_idle(1);
	omap_uart_prepare_idle(2);

	/* Jump to SRAM suspend code */
	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_POWER));

	omap_uart_resume_idle(2);
	omap_uart_resume_idle(1);
	omap_uart_resume_idle(0);

	release_console_sem();

no_sleep:
	if (omap2_pm_debug) {
		unsigned long long tmp;

		getnstimeofday(&ts_postidle);
		ts_idle = timespec_sub(ts_postidle, ts_preidle);
		tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
		omap2_pm_dump(0, 1, tmp);
	}
	omap2_gpio_resume_after_idle();

	clk_enable(osc_ck);

	/* clear CORE wake-up events */
	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);

	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
	prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);

	/* MPU domain wake events */
	l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x01)
		prm_write_mod_reg(0x01, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x20)
		prm_write_mod_reg(0x20, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);

	/* Mask future PRCM-to-MPU interrupts */
	prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
}

static int omap2_i2c_active(void)
{
	u32 l;

	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
}

static int sti_console_enabled;

static int omap2_allow_mpu_retention(void)
{
	u32 l;

	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
		 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
		 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
		return 0;
	/* Check for UART3. */
	l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
	if (l & OMAP24XX_EN_UART3_MASK)
		return 0;
	if (sti_console_enabled)
		return 0;

	return 1;
}

static void omap2_enter_mpu_retention(void)
{
	int only_idle = 0;
	struct timespec ts_preidle, ts_postidle, ts_idle;

	/* Putting MPU into the WFI state while a transfer is active
	 * seems to cause the I2C block to timeout. Why? Good question. */
	if (omap2_i2c_active())
		return;

	/* The peripherals seem not to be able to wake up the MPU when
	 * it is in retention mode. */
	if (omap2_allow_mpu_retention()) {
		/* REVISIT: These write to reserved bits? */
		prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
		prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
		prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

		/* Try to enter MPU retention */
		prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
				  OMAP_LOGICRETSTATE_MASK,
				  MPU_MOD, OMAP2_PM_PWSTCTRL);
	} else {
		/* Block MPU retention */

		prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
						 OMAP2_PM_PWSTCTRL);
		only_idle = 1;
	}

	if (omap2_pm_debug) {
		omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
		getnstimeofday(&ts_preidle);
	}

	omap2_sram_idle();

	if (omap2_pm_debug) {
		unsigned long long tmp;

		getnstimeofday(&ts_postidle);
		ts_idle = timespec_sub(ts_postidle, ts_preidle);
		tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
		omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
	}
}

static int omap2_can_sleep(void)
{
	if (omap2_fclks_active())
		return 0;
	if (!omap_uart_can_sleep())
		return 0;
	if (osc_ck->usecount > 1)
		return 0;
	if (omap_dma_running())
		return 0;

	return 1;
}

static void omap2_pm_idle(void)
{
	local_irq_disable();
	local_fiq_disable();

	if (!omap2_can_sleep()) {
		if (omap_irq_pending())
			goto out;
		omap2_enter_mpu_retention();
		goto out;
	}

	if (omap_irq_pending())
		goto out;

	omap2_enter_full_retention();

out:
	local_fiq_enable();
	local_irq_enable();
}

static int omap2_pm_prepare(void)
{
	/* We cannot sleep in idle until we have resumed */
	disable_hlt();
	return 0;
}

static int omap2_pm_suspend(void)
{
	u32 wken_wkup, mir1;

	wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
	wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
	prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);

	/* Mask GPT1 */
	mir1 = omap_readl(0x480fe0a4);
	omap_writel(1 << 5, 0x480fe0ac);

	omap_uart_prepare_suspend();
	omap2_enter_full_retention();

	omap_writel(mir1, 0x480fe0a4);
	prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);

	return 0;
}

static int omap2_pm_enter(suspend_state_t state)
{
	int ret = 0;

	switch (state) {
	case PM_SUSPEND_STANDBY:
	case PM_SUSPEND_MEM:
		ret = omap2_pm_suspend();
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static void omap2_pm_finish(void)
{
	enable_hlt();
}

static struct platform_suspend_ops omap_pm_ops = {
	.prepare	= omap2_pm_prepare,
	.enter		= omap2_pm_enter,
	.finish		= omap2_pm_finish,
	.valid		= suspend_valid_only_mem,
};

/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
{
	clkdm_clear_all_wkdeps(clkdm);
	clkdm_clear_all_sleepdeps(clkdm);

	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
		omap2_clkdm_allow_idle(clkdm);
	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
		 atomic_read(&clkdm->usecount) == 0)
		omap2_clkdm_sleep(clkdm);
	return 0;
}

static void __init prcm_setup_regs(void)
{
	int i, num_mem_banks;
	struct powerdomain *pwrdm;

	/* Enable autoidle */
	prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
			  OMAP2_PRCM_SYSCONFIG_OFFSET);

	/*
	 * Set CORE powerdomain memory banks to retain their contents
	 * during RETENTION
	 */
	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	for (i = 0; i < num_mem_banks; i++)
		pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);

	/* Set CORE powerdomain's next power state to RETENTION */
	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);

	/*
	 * Set MPU powerdomain's next power state to RETENTION;
	 * preserve logic state during retention
	 */
	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Force-power down DSP, GFX powerdomains */

	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	omap2_clkdm_sleep(dsp_clkdm);

	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	omap2_clkdm_sleep(gfx_clkdm);

	/*
	 * Clear clockdomain wakeup dependencies and enable
	 * hardware-supervised idle for all clkdms
	 */
	clkdm_for_each(clkdms_setup, NULL);
	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);

	/* Enable clock autoidle for all domains */
	cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
			 OMAP24XX_AUTO_MAILBOXES_MASK |
			 OMAP24XX_AUTO_WDT4_MASK |
			 OMAP2420_AUTO_WDT3_MASK |
			 OMAP24XX_AUTO_MSPRO_MASK |
			 OMAP2420_AUTO_MMC_MASK |
			 OMAP24XX_AUTO_FAC_MASK |
			 OMAP2420_AUTO_EAC_MASK |
			 OMAP24XX_AUTO_HDQ_MASK |
			 OMAP24XX_AUTO_UART2_MASK |
			 OMAP24XX_AUTO_UART1_MASK |
			 OMAP24XX_AUTO_I2C2_MASK |
			 OMAP24XX_AUTO_I2C1_MASK |
			 OMAP24XX_AUTO_MCSPI2_MASK |
			 OMAP24XX_AUTO_MCSPI1_MASK |
			 OMAP24XX_AUTO_MCBSP2_MASK |
			 OMAP24XX_AUTO_MCBSP1_MASK |
			 OMAP24XX_AUTO_GPT12_MASK |
			 OMAP24XX_AUTO_GPT11_MASK |
			 OMAP24XX_AUTO_GPT10_MASK |
			 OMAP24XX_AUTO_GPT9_MASK |
			 OMAP24XX_AUTO_GPT8_MASK |
			 OMAP24XX_AUTO_GPT7_MASK |
			 OMAP24XX_AUTO_GPT6_MASK |
			 OMAP24XX_AUTO_GPT5_MASK |
			 OMAP24XX_AUTO_GPT4_MASK |
			 OMAP24XX_AUTO_GPT3_MASK |
			 OMAP24XX_AUTO_GPT2_MASK |
			 OMAP2420_AUTO_VLYNQ_MASK |
			 OMAP24XX_AUTO_DSS_MASK,
			 CORE_MOD, CM_AUTOIDLE1);
	cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
			 OMAP24XX_AUTO_SSI_MASK |
			 OMAP24XX_AUTO_USB_MASK,
			 CORE_MOD, CM_AUTOIDLE2);
	cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
			 OMAP24XX_AUTO_GPMC_MASK |
			 OMAP24XX_AUTO_SDMA_MASK,
			 CORE_MOD, CM_AUTOIDLE3);
	cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
			 OMAP24XX_AUTO_AES_MASK |
			 OMAP24XX_AUTO_RNG_MASK |
			 OMAP24XX_AUTO_SHA_MASK |
			 OMAP24XX_AUTO_DES_MASK,
			 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);

	cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
			 CM_AUTOIDLE);

	/* Put DPLL and both APLLs into autoidle mode */
	cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
			 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
			 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
			 PLL_MOD, CM_AUTOIDLE);

	cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
			 OMAP24XX_AUTO_WDT1_MASK |
			 OMAP24XX_AUTO_MPU_WDT_MASK |
			 OMAP24XX_AUTO_GPIOS_MASK |
			 OMAP24XX_AUTO_32KSYNC_MASK |
			 OMAP24XX_AUTO_GPT1_MASK,
			 WKUP_MOD, CM_AUTOIDLE);

	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
	 * stabilisation */
	prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
			  OMAP2_PRCM_CLKSSETUP_OFFSET);

	/* Configure automatic voltage transition */
	prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
			  OMAP2_PRCM_VOLTSETUP_OFFSET);
	prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
			  (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
			  OMAP24XX_MEMRETCTRL_MASK |
			  (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
			  (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
			  OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);

	/* Enable wake-up events */
	prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
			  WKUP_MOD, PM_WKEN);
}

static int __init omap2_pm_init(void)
{
	u32 l;

	if (!cpu_is_omap24xx())
		return -ENODEV;

	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
	l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);

	/* Look up important powerdomains */

	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	if (!mpu_pwrdm)
		pr_err("PM: mpu_pwrdm not found\n");

	core_pwrdm = pwrdm_lookup("core_pwrdm");
	if (!core_pwrdm)
		pr_err("PM: core_pwrdm not found\n");

	/* Look up important clockdomains */

	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	if (!mpu_clkdm)
		pr_err("PM: mpu_clkdm not found\n");

	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	if (!wkup_clkdm)
		pr_err("PM: wkup_clkdm not found\n");

	dsp_clkdm = clkdm_lookup("dsp_clkdm");
	if (!dsp_clkdm)
		pr_err("PM: dsp_clkdm not found\n");

	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	if (!gfx_clkdm)
		pr_err("PM: gfx_clkdm not found\n");


	osc_ck = clk_get(NULL, "osc_ck");
	if (IS_ERR(osc_ck)) {
		printk(KERN_ERR "could not get osc_ck\n");
		return -ENODEV;
	}

	if (cpu_is_omap242x()) {
		emul_ck = clk_get(NULL, "emul_ck");
		if (IS_ERR(emul_ck)) {
			printk(KERN_ERR "could not get emul_ck\n");
			clk_put(osc_ck);
			return -ENODEV;
		}
	}

	prcm_setup_regs();

	/* Hack to prevent MPU retention when STI console is enabled. */
	{
		const struct omap_sti_console_config *sti;

		sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
				      struct omap_sti_console_config);
		if (sti != NULL && sti->enable)
			sti_console_enabled = 1;
	}

	/*
	 * We copy the assembler sleep/wakeup routines to SRAM.
	 * These routines need to be in SRAM as that's the only
	 * memory the MPU can see when it wakes up.
	 */
	if (cpu_is_omap24xx()) {
		omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
						 omap24xx_idle_loop_suspend_sz);

		omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
						    omap24xx_cpu_suspend_sz);
	}

	suspend_set_ops(&omap_pm_ops);
	pm_idle = omap2_pm_idle;

	return 0;
}

late_initcall(omap2_pm_init);
Commit	Line	Data
8bd22949 KH	1	/*
	2	* OMAP2 Power Management Routines
	3	*
	4	* Copyright (C) 2005 Texas Instruments, Inc.
	5	* Copyright (C) 2006-2008 Nokia Corporation
	6	*
	7	* Written by:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Tony Lindgren
	10	* Juha Yrjola
	11	* Amit Kucheria <amit.kucheria@nokia.com>
	12	* Igor Stoppa <igor.stoppa@nokia.com>
	13	*
	14	* Based on pm.c for omap1
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of the GNU General Public License version 2 as
	18	* published by the Free Software Foundation.
	19	*/
	20
	21	#include <linux/suspend.h>
	22	#include <linux/sched.h>
	23	#include <linux/proc_fs.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/sysfs.h>
	26	#include <linux/module.h>
	27	#include <linux/delay.h>
	28	#include <linux/clk.h>
	29	#include <linux/io.h>
	30	#include <linux/irq.h>
	31	#include <linux/time.h>
	32	#include <linux/gpio.h>
0d8e2d0d	33	#include <linux/console.h>
8bd22949 KH	34
	35	#include <asm/mach/time.h>
	36	#include <asm/mach/irq.h>
	37	#include <asm/mach-types.h>
	38
	39	#include <mach/irqs.h>
ce491cf8 TL	40	#include <plat/clock.h>
ce491cf8 TL	41	#include <plat/sram.h>
ce491cf8 TL	42	#include <plat/dma.h>
ce491cf8 TL	43	#include <plat/board.h>
8bd22949 KH	44
	45	#include "prm.h"
	46	#include "prm-regbits-24xx.h"
	47	#include "cm.h"
	48	#include "cm-regbits-24xx.h"
	49	#include "sdrc.h"
	50	#include "pm.h"
4814ced5	51	#include "control.h"
8bd22949	52
ce491cf8 TL	53	#include <plat/powerdomain.h>
ce491cf8 TL	54	#include <plat/clockdomain.h>
8bd22949 KH	55
	56	static void (*omap2_sram_idle)(void);
	57	static void (omap2_sram_suspend)(u32 dllctrl, void __iomem sdrc_dlla_ctrl,
	58	void __iomem *sdrc_power);
	59
369d5614 PW	60	static struct powerdomain mpu_pwrdm, core_pwrdm;
369d5614 PW	61	static struct clockdomain dsp_clkdm, mpu_clkdm, wkup_clkdm, gfx_clkdm;
8bd22949 KH	62
	63	static struct clk osc_ck, emul_ck;
	64
	65	static int omap2_fclks_active(void)
	66	{
	67	u32 f1, f2;
	68
	69	f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	70	f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
4af4016c KH	71
4af4016c KH	72	/* Ignore UART clocks. These are handled by UART core (serial.c) */
2fd0f75c PW	73	f1 &= ~(OMAP24XX_EN_UART1_MASK \| OMAP24XX_EN_UART2_MASK);
2fd0f75c PW	74	f2 &= ~OMAP24XX_EN_UART3_MASK;
4af4016c	75
8bd22949 KH	76	if (f1 \| f2)
	77	return 1;
	78	return 0;
	79	}
	80
8bd22949 KH	81	static void omap2_enter_full_retention(void)
	82	{
	83	u32 l;
	84	struct timespec ts_preidle, ts_postidle, ts_idle;
	85
	86	/* There is 1 reference hold for all children of the oscillator
	87	* clock, the following will remove it. If no one else uses the
	88	* oscillator itself it will be disabled if/when we enter retention
	89	* mode.
	90	*/
	91	clk_disable(osc_ck);
	92
	93	/* Clear old wake-up events */
	94	/* REVISIT: These write to reserved bits? */
	95	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	96	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	97	prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
	98
	99	/*
	100	* Set MPU powerdomain's next power state to RETENTION;
	101	* preserve logic state during retention
	102	*/
	103	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	104	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	105
	106	/* Workaround to kill USB */
	107	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) \| OMAP24XX_USBSTANDBYCTRL;
	108	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
	109
43ffcd9a	110	omap2_gpio_prepare_for_idle(PWRDM_POWER_RET);
8bd22949 KH	111
	112	if (omap2_pm_debug) {
	113	omap2_pm_dump(0, 0, 0);
	114	getnstimeofday(&ts_preidle);
	115	}
	116
	117	/* One last check for pending IRQs to avoid extra latency due
	118	* to sleeping unnecessarily. */
94434535	119	if (omap_irq_pending())
8bd22949 KH	120	goto no_sleep;
8bd22949 KH	121
0d8e2d0d PW	122	/* Block console output in case it is on one of the OMAP UARTs */
	123	if (try_acquire_console_sem())
	124	goto no_sleep;
	125
4af4016c KH	126	omap_uart_prepare_idle(0);
	127	omap_uart_prepare_idle(1);
	128	omap_uart_prepare_idle(2);
	129
8bd22949 KH	130	/* Jump to SRAM suspend code */
	131	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
	132	OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
	133	OMAP_SDRC_REGADDR(SDRC_POWER));
8bd22949	134
4af4016c KH	135	omap_uart_resume_idle(2);
	136	omap_uart_resume_idle(1);
	137	omap_uart_resume_idle(0);
	138
0d8e2d0d PW	139	release_console_sem();
0d8e2d0d PW	140
4af4016c	141	no_sleep:
8bd22949 KH	142	if (omap2_pm_debug) {
	143	unsigned long long tmp;
	144
	145	getnstimeofday(&ts_postidle);
	146	ts_idle = timespec_sub(ts_postidle, ts_preidle);
	147	tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
	148	omap2_pm_dump(0, 1, tmp);
	149	}
43ffcd9a	150	omap2_gpio_resume_after_idle();
8bd22949 KH	151
	152	clk_enable(osc_ck);
	153
	154	/* clear CORE wake-up events */
	155	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	156	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	157
	158	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
	159	prm_clear_mod_reg_bits(0x4 \| 0x1, WKUP_MOD, PM_WKST);
	160
	161	/* MPU domain wake events */
	162	l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	163	if (l & 0x01)
	164	prm_write_mod_reg(0x01, OCP_MOD,
	165	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	166	if (l & 0x20)
	167	prm_write_mod_reg(0x20, OCP_MOD,
	168	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	169
	170	/* Mask future PRCM-to-MPU interrupts */
	171	prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	172	}
	173
	174	static int omap2_i2c_active(void)
	175	{
	176	u32 l;
	177
	178	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
f38ca10a	179	return l & (OMAP2420_EN_I2C2_MASK \| OMAP2420_EN_I2C1_MASK);
8bd22949 KH	180	}
	181
	182	static int sti_console_enabled;
	183
	184	static int omap2_allow_mpu_retention(void)
	185	{
	186	u32 l;
	187
	188	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
	189	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
2fd0f75c PW	190	if (l & (OMAP2420_EN_MMC_MASK \| OMAP24XX_EN_UART2_MASK \|
	191	OMAP24XX_EN_UART1_MASK \| OMAP24XX_EN_MCSPI2_MASK \|
	192	OMAP24XX_EN_MCSPI1_MASK \| OMAP24XX_EN_DSS1_MASK))
8bd22949 KH	193	return 0;
	194	/* Check for UART3. */
	195	l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
2fd0f75c	196	if (l & OMAP24XX_EN_UART3_MASK)
8bd22949 KH	197	return 0;
	198	if (sti_console_enabled)
	199	return 0;
	200
	201	return 1;
	202	}
	203
	204	static void omap2_enter_mpu_retention(void)
	205	{
	206	int only_idle = 0;
	207	struct timespec ts_preidle, ts_postidle, ts_idle;
	208
	209	/* Putting MPU into the WFI state while a transfer is active
	210	* seems to cause the I2C block to timeout. Why? Good question. */
	211	if (omap2_i2c_active())
	212	return;
	213
	214	/* The peripherals seem not to be able to wake up the MPU when
	215	* it is in retention mode. */
	216	if (omap2_allow_mpu_retention()) {
	217	/* REVISIT: These write to reserved bits? */
	218	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	219	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	220	prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
	221
	222	/* Try to enter MPU retention */
	223	prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) \|
2fd0f75c	224	OMAP_LOGICRETSTATE_MASK,
37903009	225	MPU_MOD, OMAP2_PM_PWSTCTRL);
8bd22949 KH	226	} else {
	227	/* Block MPU retention */
	228
2fd0f75c	229	prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
37903009	230	OMAP2_PM_PWSTCTRL);
8bd22949 KH	231	only_idle = 1;
	232	}
	233
	234	if (omap2_pm_debug) {
	235	omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
	236	getnstimeofday(&ts_preidle);
	237	}
	238
	239	omap2_sram_idle();
	240
	241	if (omap2_pm_debug) {
	242	unsigned long long tmp;
	243
	244	getnstimeofday(&ts_postidle);
	245	ts_idle = timespec_sub(ts_postidle, ts_preidle);
	246	tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
	247	omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
	248	}
	249	}
	250
	251	static int omap2_can_sleep(void)
	252	{
	253	if (omap2_fclks_active())
	254	return 0;
503923ee KH	255	if (!omap_uart_can_sleep())
503923ee KH	256	return 0;
8bd22949 KH	257	if (osc_ck->usecount > 1)
	258	return 0;
	259	if (omap_dma_running())
	260	return 0;
	261
	262	return 1;
	263	}
	264
	265	static void omap2_pm_idle(void)
	266	{
	267	local_irq_disable();
	268	local_fiq_disable();
	269
	270	if (!omap2_can_sleep()) {
94434535	271	if (omap_irq_pending())
8bd22949 KH	272	goto out;
	273	omap2_enter_mpu_retention();
	274	goto out;
	275	}
	276
94434535	277	if (omap_irq_pending())
8bd22949 KH	278	goto out;
	279
	280	omap2_enter_full_retention();
	281
	282	out:
	283	local_fiq_enable();
	284	local_irq_enable();
	285	}
	286
	287	static int omap2_pm_prepare(void)
	288	{
	289	/* We cannot sleep in idle until we have resumed */
	290	disable_hlt();
	291	return 0;
	292	}
	293
	294	static int omap2_pm_suspend(void)
	295	{
	296	u32 wken_wkup, mir1;
	297
	298	wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
2fd0f75c PW	299	wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
2fd0f75c PW	300	prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
8bd22949 KH	301
	302	/* Mask GPT1 */
	303	mir1 = omap_readl(0x480fe0a4);
	304	omap_writel(1 << 5, 0x480fe0ac);
	305
4af4016c	306	omap_uart_prepare_suspend();
8bd22949 KH	307	omap2_enter_full_retention();
	308
	309	omap_writel(mir1, 0x480fe0a4);
	310	prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
	311
	312	return 0;
	313	}
	314
	315	static int omap2_pm_enter(suspend_state_t state)
	316	{
	317	int ret = 0;
	318
	319	switch (state) {
	320	case PM_SUSPEND_STANDBY:
	321	case PM_SUSPEND_MEM:
	322	ret = omap2_pm_suspend();
	323	break;
	324	default:
	325	ret = -EINVAL;
	326	}
	327
	328	return ret;
	329	}
	330
	331	static void omap2_pm_finish(void)
	332	{
	333	enable_hlt();
	334	}
	335
	336	static struct platform_suspend_ops omap_pm_ops = {
	337	.prepare = omap2_pm_prepare,
	338	.enter = omap2_pm_enter,
	339	.finish = omap2_pm_finish,
	340	.valid = suspend_valid_only_mem,
	341	};
	342
369d5614 PW	343	/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
369d5614 PW	344	static int __init clkdms_setup(struct clockdomain clkdm, void unused)
8bd22949	345	{
369d5614 PW	346	clkdm_clear_all_wkdeps(clkdm);
	347	clkdm_clear_all_sleepdeps(clkdm);
	348
	349	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
	350	omap2_clkdm_allow_idle(clkdm);
	351	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
	352	atomic_read(&clkdm->usecount) == 0)
	353	omap2_clkdm_sleep(clkdm);
8bd22949 KH	354	return 0;
	355	}
	356
	357	static void __init prcm_setup_regs(void)
	358	{
	359	int i, num_mem_banks;
	360	struct powerdomain *pwrdm;
	361
	362	/* Enable autoidle */
f38ca10a	363	prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
8bd22949 KH	364	OMAP2_PRCM_SYSCONFIG_OFFSET);
8bd22949 KH	365
8bd22949 KH	366	/*
	367	* Set CORE powerdomain memory banks to retain their contents
	368	* during RETENTION
	369	*/
	370	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	371	for (i = 0; i < num_mem_banks; i++)
	372	pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
	373
	374	/* Set CORE powerdomain's next power state to RETENTION */
	375	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
	376
	377	/*
	378	* Set MPU powerdomain's next power state to RETENTION;
	379	* preserve logic state during retention
	380	*/
	381	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	382	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	383
	384	/* Force-power down DSP, GFX powerdomains */
	385
	386	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	387	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	388	omap2_clkdm_sleep(dsp_clkdm);
	389
	390	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	391	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	392	omap2_clkdm_sleep(gfx_clkdm);
	393
369d5614 PW	394	/*
	395	* Clear clockdomain wakeup dependencies and enable
	396	* hardware-supervised idle for all clkdms
	397	*/
	398	clkdm_for_each(clkdms_setup, NULL);
	399	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
8bd22949 KH	400
8bd22949 KH	401	/* Enable clock autoidle for all domains */
f38ca10a PW	402	cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK \|
	403	OMAP24XX_AUTO_MAILBOXES_MASK \|
	404	OMAP24XX_AUTO_WDT4_MASK \|
	405	OMAP2420_AUTO_WDT3_MASK \|
	406	OMAP24XX_AUTO_MSPRO_MASK \|
	407	OMAP2420_AUTO_MMC_MASK \|
	408	OMAP24XX_AUTO_FAC_MASK \|
	409	OMAP2420_AUTO_EAC_MASK \|
	410	OMAP24XX_AUTO_HDQ_MASK \|
	411	OMAP24XX_AUTO_UART2_MASK \|
	412	OMAP24XX_AUTO_UART1_MASK \|
	413	OMAP24XX_AUTO_I2C2_MASK \|
	414	OMAP24XX_AUTO_I2C1_MASK \|
	415	OMAP24XX_AUTO_MCSPI2_MASK \|
	416	OMAP24XX_AUTO_MCSPI1_MASK \|
	417	OMAP24XX_AUTO_MCBSP2_MASK \|
	418	OMAP24XX_AUTO_MCBSP1_MASK \|
	419	OMAP24XX_AUTO_GPT12_MASK \|
	420	OMAP24XX_AUTO_GPT11_MASK \|
	421	OMAP24XX_AUTO_GPT10_MASK \|
	422	OMAP24XX_AUTO_GPT9_MASK \|
	423	OMAP24XX_AUTO_GPT8_MASK \|
	424	OMAP24XX_AUTO_GPT7_MASK \|
	425	OMAP24XX_AUTO_GPT6_MASK \|
	426	OMAP24XX_AUTO_GPT5_MASK \|
	427	OMAP24XX_AUTO_GPT4_MASK \|
	428	OMAP24XX_AUTO_GPT3_MASK \|
	429	OMAP24XX_AUTO_GPT2_MASK \|
	430	OMAP2420_AUTO_VLYNQ_MASK \|
	431	OMAP24XX_AUTO_DSS_MASK,
8bd22949	432	CORE_MOD, CM_AUTOIDLE1);
f38ca10a PW	433	cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK \|
	434	OMAP24XX_AUTO_SSI_MASK \|
	435	OMAP24XX_AUTO_USB_MASK,
8bd22949	436	CORE_MOD, CM_AUTOIDLE2);
f38ca10a PW	437	cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK \|
	438	OMAP24XX_AUTO_GPMC_MASK \|
	439	OMAP24XX_AUTO_SDMA_MASK,
8bd22949	440	CORE_MOD, CM_AUTOIDLE3);
f38ca10a PW	441	cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK \|
	442	OMAP24XX_AUTO_AES_MASK \|
	443	OMAP24XX_AUTO_RNG_MASK \|
	444	OMAP24XX_AUTO_SHA_MASK \|
	445	OMAP24XX_AUTO_DES_MASK,
8bd22949 KH	446	CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
8bd22949 KH	447
f38ca10a PW	448	cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
f38ca10a PW	449	CM_AUTOIDLE);
8bd22949 KH	450
	451	/* Put DPLL and both APLLs into autoidle mode */
	452	cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) \|
	453	(0x03 << OMAP24XX_AUTO_96M_SHIFT) \|
	454	(0x03 << OMAP24XX_AUTO_54M_SHIFT),
	455	PLL_MOD, CM_AUTOIDLE);
	456
f38ca10a PW	457	cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK \|
	458	OMAP24XX_AUTO_WDT1_MASK \|
	459	OMAP24XX_AUTO_MPU_WDT_MASK \|
	460	OMAP24XX_AUTO_GPIOS_MASK \|
	461	OMAP24XX_AUTO_32KSYNC_MASK \|
	462	OMAP24XX_AUTO_GPT1_MASK,
8bd22949 KH	463	WKUP_MOD, CM_AUTOIDLE);
	464
	465	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
	466	* stabilisation */
	467	prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
	468	OMAP2_PRCM_CLKSSETUP_OFFSET);
	469
	470	/* Configure automatic voltage transition */
	471	prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
	472	OMAP2_PRCM_VOLTSETUP_OFFSET);
f38ca10a	473	prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK \|
8bd22949	474	(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) \|
f38ca10a	475	OMAP24XX_MEMRETCTRL_MASK \|
8bd22949 KH	476	(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) \|
	477	(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
	478	OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
	479
	480	/* Enable wake-up events */
2fd0f75c	481	prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK \| OMAP24XX_EN_GPT1_MASK,
8bd22949 KH	482	WKUP_MOD, PM_WKEN);
	483	}
	484
7cc515f7	485	static int __init omap2_pm_init(void)
8bd22949 KH	486	{
	487	u32 l;
	488
	489	if (!cpu_is_omap24xx())
	490	return -ENODEV;
	491
	492	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
	493	l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
	494	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
	495
369d5614	496	/* Look up important powerdomains */
8bd22949 KH	497
	498	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	499	if (!mpu_pwrdm)
	500	pr_err("PM: mpu_pwrdm not found\n");
	501
	502	core_pwrdm = pwrdm_lookup("core_pwrdm");
	503	if (!core_pwrdm)
	504	pr_err("PM: core_pwrdm not found\n");
	505
369d5614 PW	506	/* Look up important clockdomains */
	507
	508	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	509	if (!mpu_clkdm)
	510	pr_err("PM: mpu_clkdm not found\n");
	511
	512	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	513	if (!wkup_clkdm)
	514	pr_err("PM: wkup_clkdm not found\n");
	515
8bd22949 KH	516	dsp_clkdm = clkdm_lookup("dsp_clkdm");
8bd22949 KH	517	if (!dsp_clkdm)
369d5614	518	pr_err("PM: dsp_clkdm not found\n");
8bd22949 KH	519
	520	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	521	if (!gfx_clkdm)
	522	pr_err("PM: gfx_clkdm not found\n");
	523
	524
	525	osc_ck = clk_get(NULL, "osc_ck");
	526	if (IS_ERR(osc_ck)) {
	527	printk(KERN_ERR "could not get osc_ck\n");
	528	return -ENODEV;
	529	}
	530
	531	if (cpu_is_omap242x()) {
	532	emul_ck = clk_get(NULL, "emul_ck");
	533	if (IS_ERR(emul_ck)) {
	534	printk(KERN_ERR "could not get emul_ck\n");
	535	clk_put(osc_ck);
	536	return -ENODEV;
	537	}
	538	}
	539
	540	prcm_setup_regs();
	541
	542	/* Hack to prevent MPU retention when STI console is enabled. */
	543	{
	544	const struct omap_sti_console_config *sti;
	545
	546	sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
	547	struct omap_sti_console_config);
	548	if (sti != NULL && sti->enable)
	549	sti_console_enabled = 1;
	550	}
	551
	552	/*
	553	* We copy the assembler sleep/wakeup routines to SRAM.
	554	* These routines need to be in SRAM as that's the only
	555	* memory the MPU can see when it wakes up.
	556	*/
	557	if (cpu_is_omap24xx()) {
	558	omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
	559	omap24xx_idle_loop_suspend_sz);
	560
	561	omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
	562	omap24xx_cpu_suspend_sz);
	563	}
	564
	565	suspend_set_ops(&omap_pm_ops);
	566	pm_idle = omap2_pm_idle;
	567
	568	return 0;
	569	}
	570
	571	late_initcall(omap2_pm_init);