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Commit | Line | Data |
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8bd22949 KH |
1 | /* |
2 | * OMAP3 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2006-2008 Nokia Corporation | |
5 | * Tony Lindgren <tony@atomide.com> | |
6 | * Jouni Hogander | |
7 | * | |
2f5939c3 RN |
8 | * Copyright (C) 2007 Texas Instruments, Inc. |
9 | * Rajendra Nayak <rnayak@ti.com> | |
10 | * | |
8bd22949 KH |
11 | * Copyright (C) 2005 Texas Instruments, Inc. |
12 | * Richard Woodruff <r-woodruff2@ti.com> | |
13 | * | |
14 | * Based on pm.c for omap1 | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/pm.h> | |
22 | #include <linux/suspend.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/gpio.h> | |
c40552bc | 28 | #include <linux/clk.h> |
dccaad89 | 29 | #include <linux/delay.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
45c3eb7d | 31 | #include <linux/omap-dma.h> |
4b25408f TL |
32 | #include <linux/platform_data/gpio-omap.h> |
33 | ||
5e7c58dc | 34 | #include <trace/events/power.h> |
8bd22949 | 35 | |
bf027ca1 | 36 | #include <asm/fncpy.h> |
2c74a0ce | 37 | #include <asm/suspend.h> |
9f97da78 | 38 | #include <asm/system_misc.h> |
2c74a0ce | 39 | |
1540f214 | 40 | #include "clockdomain.h" |
72e06d08 | 41 | #include "powerdomain.h" |
e4c060db | 42 | #include "soc.h" |
4e65331c | 43 | #include "common.h" |
ff4ae5d9 | 44 | #include "cm3xxx.h" |
8bd22949 | 45 | #include "cm-regbits-34xx.h" |
99f0b8d6 | 46 | #include "gpmc.h" |
8bd22949 | 47 | #include "prm-regbits-34xx.h" |
139563ad | 48 | #include "prm3xxx.h" |
8bd22949 | 49 | #include "pm.h" |
13a6fe0f | 50 | #include "sdrc.h" |
bf027ca1 | 51 | #include "sram.h" |
4814ced5 | 52 | #include "control.h" |
3b8c4ebb | 53 | #include "vc.h" |
13a6fe0f | 54 | |
8cdfd834 NM |
55 | /* pm34xx errata defined in pm.h */ |
56 | u16 pm34xx_errata; | |
57 | ||
8bd22949 KH |
58 | struct power_state { |
59 | struct powerdomain *pwrdm; | |
60 | u32 next_state; | |
10f90ed2 | 61 | #ifdef CONFIG_SUSPEND |
8bd22949 | 62 | u32 saved_state; |
10f90ed2 | 63 | #endif |
8bd22949 KH |
64 | struct list_head node; |
65 | }; | |
66 | ||
67 | static LIST_HEAD(pwrst_list); | |
68 | ||
27d59a4a | 69 | static int (*_omap_save_secure_sram)(u32 *addr); |
46e130d2 | 70 | void (*omap3_do_wfi_sram)(void); |
27d59a4a | 71 | |
fa3c2a4f RN |
72 | static struct powerdomain *mpu_pwrdm, *neon_pwrdm; |
73 | static struct powerdomain *core_pwrdm, *per_pwrdm; | |
3a7ec26b | 74 | |
2f5939c3 RN |
75 | static void omap3_core_save_context(void) |
76 | { | |
596efe47 | 77 | omap3_ctrl_save_padconf(); |
dccaad89 TK |
78 | |
79 | /* | |
80 | * Force write last pad into memory, as this can fail in some | |
83521291 | 81 | * cases according to errata 1.157, 1.185 |
dccaad89 TK |
82 | */ |
83 | omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), | |
84 | OMAP343X_CONTROL_MEM_WKUP + 0x2a0); | |
85 | ||
2f5939c3 RN |
86 | /* Save the Interrupt controller context */ |
87 | omap_intc_save_context(); | |
88 | /* Save the GPMC context */ | |
89 | omap3_gpmc_save_context(); | |
90 | /* Save the system control module context, padconf already save above*/ | |
91 | omap3_control_save_context(); | |
f2d11858 | 92 | omap_dma_global_context_save(); |
2f5939c3 RN |
93 | } |
94 | ||
95 | static void omap3_core_restore_context(void) | |
96 | { | |
97 | /* Restore the control module context, padconf restored by h/w */ | |
98 | omap3_control_restore_context(); | |
99 | /* Restore the GPMC context */ | |
100 | omap3_gpmc_restore_context(); | |
101 | /* Restore the interrupt controller context */ | |
102 | omap_intc_restore_context(); | |
f2d11858 | 103 | omap_dma_global_context_restore(); |
2f5939c3 RN |
104 | } |
105 | ||
9d97140b TK |
106 | /* |
107 | * FIXME: This function should be called before entering off-mode after | |
108 | * OMAP3 secure services have been accessed. Currently it is only called | |
109 | * once during boot sequence, but this works as we are not using secure | |
110 | * services. | |
111 | */ | |
617fcc98 | 112 | static void omap3_save_secure_ram_context(void) |
27d59a4a TK |
113 | { |
114 | u32 ret; | |
617fcc98 | 115 | int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
27d59a4a TK |
116 | |
117 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | |
27d59a4a TK |
118 | /* |
119 | * MPU next state must be set to POWER_ON temporarily, | |
120 | * otherwise the WFI executed inside the ROM code | |
121 | * will hang the system. | |
122 | */ | |
123 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | |
6dd1e357 | 124 | ret = _omap_save_secure_sram((u32 *)(unsigned long) |
27d59a4a | 125 | __pa(omap3_secure_ram_storage)); |
617fcc98 | 126 | pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); |
27d59a4a TK |
127 | /* Following is for error tracking, it should not happen */ |
128 | if (ret) { | |
98179856 | 129 | pr_err("save_secure_sram() returns %08x\n", ret); |
27d59a4a TK |
130 | while (1) |
131 | ; | |
132 | } | |
133 | } | |
134 | } | |
135 | ||
22f51371 | 136 | static irqreturn_t _prcm_int_handle_io(int irq, void *unused) |
8cb0ac99 PW |
137 | { |
138 | int c; | |
139 | ||
0efc0f6e TK |
140 | c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1, |
141 | ~(OMAP3430_ST_IO_MASK | | |
142 | OMAP3430_ST_IO_CHAIN_MASK)); | |
8cb0ac99 | 143 | |
22f51371 | 144 | return c ? IRQ_HANDLED : IRQ_NONE; |
77da2d91 | 145 | } |
8bd22949 | 146 | |
22f51371 | 147 | static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) |
77da2d91 | 148 | { |
22f51371 | 149 | int c; |
d6290a3e | 150 | |
22f51371 TK |
151 | /* |
152 | * Clear all except ST_IO and ST_IO_CHAIN for wkup module, | |
153 | * these are handled in a separate handler to avoid acking | |
154 | * IO events before parsing in mux code | |
155 | */ | |
0efc0f6e TK |
156 | c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1, |
157 | OMAP3430_ST_IO_MASK | | |
158 | OMAP3430_ST_IO_CHAIN_MASK); | |
159 | c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0); | |
160 | c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); | |
22f51371 | 161 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
0efc0f6e TK |
162 | c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0); |
163 | c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); | |
22f51371 | 164 | } |
8bd22949 | 165 | |
22f51371 | 166 | return c ? IRQ_HANDLED : IRQ_NONE; |
8bd22949 KH |
167 | } |
168 | ||
cbe26349 RK |
169 | static void omap34xx_save_context(u32 *save) |
170 | { | |
171 | u32 val; | |
172 | ||
173 | /* Read Auxiliary Control Register */ | |
174 | asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); | |
175 | *save++ = 1; | |
176 | *save++ = val; | |
177 | ||
178 | /* Read L2 AUX ctrl register */ | |
179 | asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); | |
180 | *save++ = 1; | |
181 | *save++ = val; | |
182 | } | |
183 | ||
29cb3cd2 | 184 | static int omap34xx_do_sram_idle(unsigned long save_state) |
57f277b0 | 185 | { |
cbe26349 | 186 | omap34xx_cpu_suspend(save_state); |
29cb3cd2 | 187 | return 0; |
57f277b0 RN |
188 | } |
189 | ||
99e6a4d2 | 190 | void omap_sram_idle(void) |
8bd22949 KH |
191 | { |
192 | /* Variable to tell what needs to be saved and restored | |
193 | * in omap_sram_idle*/ | |
194 | /* save_state = 0 => Nothing to save and restored */ | |
195 | /* save_state = 1 => Only L1 and logic lost */ | |
196 | /* save_state = 2 => Only L2 lost */ | |
197 | /* save_state = 3 => L1, L2 and logic lost */ | |
fa3c2a4f RN |
198 | int save_state = 0; |
199 | int mpu_next_state = PWRDM_POWER_ON; | |
200 | int per_next_state = PWRDM_POWER_ON; | |
201 | int core_next_state = PWRDM_POWER_ON; | |
72e06d08 | 202 | int per_going_off; |
eeb3711b | 203 | int core_prev_state; |
13a6fe0f | 204 | u32 sdrc_pwr = 0; |
8bd22949 | 205 | |
8bd22949 KH |
206 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
207 | switch (mpu_next_state) { | |
fa3c2a4f | 208 | case PWRDM_POWER_ON: |
8bd22949 KH |
209 | case PWRDM_POWER_RET: |
210 | /* No need to save context */ | |
211 | save_state = 0; | |
212 | break; | |
61255ab9 RN |
213 | case PWRDM_POWER_OFF: |
214 | save_state = 3; | |
215 | break; | |
8bd22949 KH |
216 | default: |
217 | /* Invalid state */ | |
98179856 | 218 | pr_err("Invalid mpu state in sram_idle\n"); |
8bd22949 KH |
219 | return; |
220 | } | |
fe617af7 | 221 | |
fa3c2a4f RN |
222 | /* NEON control */ |
223 | if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) | |
7139178e | 224 | pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); |
fa3c2a4f | 225 | |
40742fa8 | 226 | /* Enable IO-PAD and IO-CHAIN wakeups */ |
658ce97e | 227 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
ecf157d0 | 228 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
40742fa8 | 229 | |
e0e29fd7 | 230 | pwrdm_pre_transition(NULL); |
ff2f8e5f | 231 | |
40742fa8 | 232 | /* PER */ |
658ce97e | 233 | if (per_next_state < PWRDM_POWER_ON) { |
72e06d08 | 234 | per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; |
72e06d08 | 235 | omap2_gpio_prepare_for_idle(per_going_off); |
658ce97e KH |
236 | } |
237 | ||
238 | /* CORE */ | |
fa3c2a4f | 239 | if (core_next_state < PWRDM_POWER_ON) { |
2f5939c3 RN |
240 | if (core_next_state == PWRDM_POWER_OFF) { |
241 | omap3_core_save_context(); | |
f0611a5c | 242 | omap3_cm_save_context(); |
2f5939c3 | 243 | } |
fa3c2a4f | 244 | } |
40742fa8 | 245 | |
3b8c4ebb TL |
246 | /* Configure PMIC signaling for I2C4 or sys_off_mode */ |
247 | omap3_vc_set_pmic_signaling(core_next_state); | |
248 | ||
f18cc2ff | 249 | omap3_intc_prepare_idle(); |
8bd22949 | 250 | |
13a6fe0f | 251 | /* |
30474544 PW |
252 | * On EMU/HS devices ROM code restores a SRDC value |
253 | * from scratchpad which has automatic self refresh on timeout | |
254 | * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. | |
255 | * Hence store/restore the SDRC_POWER register here. | |
256 | */ | |
257 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && | |
258 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || | |
259 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && | |
f265dc4c | 260 | core_next_state == PWRDM_POWER_OFF) |
13a6fe0f | 261 | sdrc_pwr = sdrc_read_reg(SDRC_POWER); |
13a6fe0f | 262 | |
61255ab9 | 263 | /* |
076f2cc4 RK |
264 | * omap3_arm_context is the location where some ARM context |
265 | * get saved. The rest is placed on the stack, and restored | |
266 | * from there before resuming. | |
61255ab9 | 267 | */ |
cbe26349 RK |
268 | if (save_state) |
269 | omap34xx_save_context(omap3_arm_context); | |
076f2cc4 | 270 | if (save_state == 1 || save_state == 3) |
2c74a0ce | 271 | cpu_suspend(save_state, omap34xx_do_sram_idle); |
076f2cc4 RK |
272 | else |
273 | omap34xx_do_sram_idle(save_state); | |
8bd22949 | 274 | |
f265dc4c | 275 | /* Restore normal SDRC POWER settings */ |
30474544 PW |
276 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && |
277 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || | |
278 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && | |
13a6fe0f TK |
279 | core_next_state == PWRDM_POWER_OFF) |
280 | sdrc_write_reg(sdrc_pwr, SDRC_POWER); | |
281 | ||
658ce97e | 282 | /* CORE */ |
fa3c2a4f | 283 | if (core_next_state < PWRDM_POWER_ON) { |
2f5939c3 RN |
284 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); |
285 | if (core_prev_state == PWRDM_POWER_OFF) { | |
286 | omap3_core_restore_context(); | |
f0611a5c | 287 | omap3_cm_restore_context(); |
2f5939c3 | 288 | omap3_sram_restore_context(); |
8a917d2f | 289 | omap2_sms_restore_context(); |
2f5939c3 | 290 | } |
658ce97e | 291 | } |
f18cc2ff | 292 | omap3_intc_resume_idle(); |
658ce97e | 293 | |
e0e29fd7 KH |
294 | pwrdm_post_transition(NULL); |
295 | ||
658ce97e | 296 | /* PER */ |
e0e29fd7 | 297 | if (per_next_state < PWRDM_POWER_ON) |
43ffcd9a | 298 | omap2_gpio_resume_after_idle(); |
8bd22949 KH |
299 | } |
300 | ||
8bd22949 KH |
301 | static void omap3_pm_idle(void) |
302 | { | |
0bcd24b0 | 303 | if (omap_irq_pending()) |
6b85638b | 304 | return; |
8bd22949 | 305 | |
5e7c58dc JP |
306 | trace_cpu_idle(1, smp_processor_id()); |
307 | ||
8bd22949 KH |
308 | omap_sram_idle(); |
309 | ||
5e7c58dc | 310 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); |
8bd22949 KH |
311 | } |
312 | ||
10f90ed2 | 313 | #ifdef CONFIG_SUSPEND |
8bd22949 KH |
314 | static int omap3_pm_suspend(void) |
315 | { | |
316 | struct power_state *pwrst; | |
317 | int state, ret = 0; | |
318 | ||
319 | /* Read current next_pwrsts */ | |
320 | list_for_each_entry(pwrst, &pwrst_list, node) | |
321 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | |
322 | /* Set ones wanted by suspend */ | |
323 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
eb6a2c75 | 324 | if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) |
8bd22949 KH |
325 | goto restore; |
326 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) | |
327 | goto restore; | |
328 | } | |
329 | ||
2bbe3af3 TK |
330 | omap3_intc_suspend(); |
331 | ||
8bd22949 KH |
332 | omap_sram_idle(); |
333 | ||
334 | restore: | |
335 | /* Restore next_pwrsts */ | |
336 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
8bd22949 KH |
337 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
338 | if (state > pwrst->next_state) { | |
7852ec05 PW |
339 | pr_info("Powerdomain (%s) didn't enter target state %d\n", |
340 | pwrst->pwrdm->name, pwrst->next_state); | |
8bd22949 KH |
341 | ret = -1; |
342 | } | |
eb6a2c75 | 343 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
8bd22949 KH |
344 | } |
345 | if (ret) | |
98179856 | 346 | pr_err("Could not enter target state in pm_suspend\n"); |
8bd22949 | 347 | else |
98179856 | 348 | pr_info("Successfully put all powerdomains to target state\n"); |
8bd22949 KH |
349 | |
350 | return ret; | |
351 | } | |
2e4b62dc DG |
352 | #else |
353 | #define omap3_pm_suspend NULL | |
10f90ed2 | 354 | #endif /* CONFIG_SUSPEND */ |
8bd22949 | 355 | |
8111b221 KH |
356 | static void __init prcm_setup_regs(void) |
357 | { | |
ba12c242 | 358 | omap3_ctrl_init(); |
b296c811 | 359 | |
c5180a2b | 360 | omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva()); |
8bd22949 KH |
361 | } |
362 | ||
c40552bc KH |
363 | void omap3_pm_off_mode_enable(int enable) |
364 | { | |
365 | struct power_state *pwrst; | |
366 | u32 state; | |
367 | ||
368 | if (enable) | |
369 | state = PWRDM_POWER_OFF; | |
370 | else | |
371 | state = PWRDM_POWER_RET; | |
372 | ||
373 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
cc1b6028 EV |
374 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && |
375 | pwrst->pwrdm == core_pwrdm && | |
376 | state == PWRDM_POWER_OFF) { | |
377 | pwrst->next_state = PWRDM_POWER_RET; | |
e16b41bf | 378 | pr_warn("%s: Core OFF disabled due to errata i583\n", |
cc1b6028 EV |
379 | __func__); |
380 | } else { | |
381 | pwrst->next_state = state; | |
382 | } | |
383 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); | |
c40552bc KH |
384 | } |
385 | } | |
386 | ||
68d4778c TK |
387 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
388 | { | |
389 | struct power_state *pwrst; | |
390 | ||
391 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
392 | if (pwrst->pwrdm == pwrdm) | |
393 | return pwrst->next_state; | |
394 | } | |
395 | return -EINVAL; | |
396 | } | |
397 | ||
398 | int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) | |
399 | { | |
400 | struct power_state *pwrst; | |
401 | ||
402 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
403 | if (pwrst->pwrdm == pwrdm) { | |
404 | pwrst->next_state = state; | |
405 | return 0; | |
406 | } | |
407 | } | |
408 | return -EINVAL; | |
409 | } | |
410 | ||
a23456e9 | 411 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
8bd22949 KH |
412 | { |
413 | struct power_state *pwrst; | |
414 | ||
415 | if (!pwrdm->pwrsts) | |
416 | return 0; | |
417 | ||
d3d381c6 | 418 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
8bd22949 KH |
419 | if (!pwrst) |
420 | return -ENOMEM; | |
421 | pwrst->pwrdm = pwrdm; | |
422 | pwrst->next_state = PWRDM_POWER_RET; | |
423 | list_add(&pwrst->node, &pwrst_list); | |
424 | ||
425 | if (pwrdm_has_hdwr_sar(pwrdm)) | |
426 | pwrdm_enable_hdwr_sar(pwrdm); | |
427 | ||
eb6a2c75 | 428 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
8bd22949 KH |
429 | } |
430 | ||
46e130d2 JP |
431 | /* |
432 | * Push functions to SRAM | |
433 | * | |
434 | * The minimum set of functions is pushed to SRAM for execution: | |
435 | * - omap3_do_wfi for erratum i581 WA, | |
436 | * - save_secure_ram_context for security extensions. | |
437 | */ | |
3231fc88 RN |
438 | void omap_push_sram_idle(void) |
439 | { | |
46e130d2 JP |
440 | omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); |
441 | ||
27d59a4a TK |
442 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) |
443 | _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, | |
444 | save_secure_ram_context_sz); | |
3231fc88 RN |
445 | } |
446 | ||
8cdfd834 NM |
447 | static void __init pm_errata_configure(void) |
448 | { | |
c4236d2e | 449 | if (cpu_is_omap3630()) { |
458e999e | 450 | pm34xx_errata |= PM_RTA_ERRATUM_i608; |
c4236d2e PDS |
451 | /* Enable the l2 cache toggling in sleep logic */ |
452 | enable_omap3630_toggle_l2_on_restore(); | |
cc1b6028 | 453 | if (omap_rev() < OMAP3630_REV_ES1_2) |
856c3c5b PW |
454 | pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 | |
455 | PM_PER_MEMORIES_ERRATUM_i582); | |
456 | } else if (cpu_is_omap34xx()) { | |
457 | pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582; | |
c4236d2e | 458 | } |
8cdfd834 NM |
459 | } |
460 | ||
bbd707ac | 461 | int __init omap3_pm_init(void) |
8bd22949 KH |
462 | { |
463 | struct power_state *pwrst, *tmp; | |
856c3c5b | 464 | struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm; |
8bd22949 KH |
465 | int ret; |
466 | ||
b02b9172 PW |
467 | if (!omap3_has_io_chain_ctrl()) |
468 | pr_warning("PM: no software I/O chain control; some wakeups may be lost\n"); | |
469 | ||
8cdfd834 NM |
470 | pm_errata_configure(); |
471 | ||
8bd22949 KH |
472 | /* XXX prcm_setup_regs needs to be before enabling hw |
473 | * supervised mode for powerdomains */ | |
474 | prcm_setup_regs(); | |
475 | ||
22f51371 TK |
476 | ret = request_irq(omap_prcm_event_to_irq("wkup"), |
477 | _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); | |
478 | ||
479 | if (ret) { | |
480 | pr_err("pm: Failed to request pm_wkup irq\n"); | |
481 | goto err1; | |
482 | } | |
483 | ||
484 | /* IO interrupt is shared with mux code */ | |
485 | ret = request_irq(omap_prcm_event_to_irq("io"), | |
486 | _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", | |
487 | omap3_pm_init); | |
99b59df0 | 488 | enable_irq(omap_prcm_event_to_irq("io")); |
22f51371 | 489 | |
8bd22949 | 490 | if (ret) { |
22f51371 | 491 | pr_err("pm: Failed to request pm_io irq\n"); |
ce229c5d | 492 | goto err2; |
8bd22949 KH |
493 | } |
494 | ||
a23456e9 | 495 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
8bd22949 | 496 | if (ret) { |
98179856 | 497 | pr_err("Failed to setup powerdomains\n"); |
ce229c5d | 498 | goto err3; |
8bd22949 KH |
499 | } |
500 | ||
92206fd2 | 501 | (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); |
8bd22949 KH |
502 | |
503 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
504 | if (mpu_pwrdm == NULL) { | |
98179856 | 505 | pr_err("Failed to get mpu_pwrdm\n"); |
ce229c5d MG |
506 | ret = -EINVAL; |
507 | goto err3; | |
8bd22949 KH |
508 | } |
509 | ||
fa3c2a4f RN |
510 | neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
511 | per_pwrdm = pwrdm_lookup("per_pwrdm"); | |
512 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
513 | ||
55ed9694 PW |
514 | neon_clkdm = clkdm_lookup("neon_clkdm"); |
515 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | |
856c3c5b PW |
516 | per_clkdm = clkdm_lookup("per_clkdm"); |
517 | wkup_clkdm = clkdm_lookup("wkup_clkdm"); | |
55ed9694 | 518 | |
2e4b62dc | 519 | omap_common_suspend_init(omap3_pm_suspend); |
8bd22949 | 520 | |
0bcd24b0 | 521 | arm_pm_idle = omap3_pm_idle; |
0343371e | 522 | omap3_idle_init(); |
8bd22949 | 523 | |
458e999e NM |
524 | /* |
525 | * RTA is disabled during initialization as per erratum i608 | |
526 | * it is safer to disable RTA by the bootloader, but we would like | |
527 | * to be doubly sure here and prevent any mishaps. | |
528 | */ | |
529 | if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) | |
530 | omap3630_ctrl_disable_rta(); | |
531 | ||
856c3c5b PW |
532 | /* |
533 | * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are | |
534 | * not correctly reset when the PER powerdomain comes back | |
535 | * from OFF or OSWR when the CORE powerdomain is kept active. | |
536 | * See OMAP36xx Erratum i582 "PER Domain reset issue after | |
537 | * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a | |
538 | * complete workaround. The kernel must also prevent the PER | |
539 | * powerdomain from going to OSWR/OFF while the CORE | |
540 | * powerdomain is not going to OSWR/OFF. And if PER last | |
541 | * power state was off while CORE last power state was ON, the | |
542 | * UART3/4 and McBSP2/3 SIDETONE devices need to run a | |
543 | * self-test using their loopback tests; if that fails, those | |
544 | * devices are unusable until the PER/CORE can complete a transition | |
545 | * from ON to OSWR/OFF and then back to ON. | |
546 | * | |
547 | * XXX Technically this workaround is only needed if off-mode | |
548 | * or OSWR is enabled. | |
549 | */ | |
550 | if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582)) | |
551 | clkdm_add_wkdep(per_clkdm, wkup_clkdm); | |
552 | ||
55ed9694 | 553 | clkdm_add_wkdep(neon_clkdm, mpu_clkdm); |
27d59a4a TK |
554 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
555 | omap3_secure_ram_storage = | |
556 | kmalloc(0x803F, GFP_KERNEL); | |
557 | if (!omap3_secure_ram_storage) | |
7852ec05 | 558 | pr_err("Memory allocation failed when allocating for secure sram context\n"); |
9d97140b TK |
559 | |
560 | local_irq_disable(); | |
9d97140b TK |
561 | |
562 | omap_dma_global_context_save(); | |
617fcc98 | 563 | omap3_save_secure_ram_context(); |
9d97140b TK |
564 | omap_dma_global_context_restore(); |
565 | ||
566 | local_irq_enable(); | |
27d59a4a | 567 | } |
27d59a4a | 568 | |
9d97140b | 569 | omap3_save_scratchpad_contents(); |
8bd22949 | 570 | return ret; |
ce229c5d MG |
571 | |
572 | err3: | |
8bd22949 KH |
573 | list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { |
574 | list_del(&pwrst->node); | |
575 | kfree(pwrst); | |
576 | } | |
ce229c5d MG |
577 | free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init); |
578 | err2: | |
579 | free_irq(omap_prcm_event_to_irq("wkup"), NULL); | |
580 | err1: | |
8bd22949 KH |
581 | return ret; |
582 | } |