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8bd22949 KH |
1 | /* |
2 | * OMAP3 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2006-2008 Nokia Corporation | |
5 | * Tony Lindgren <tony@atomide.com> | |
6 | * Jouni Hogander | |
7 | * | |
2f5939c3 RN |
8 | * Copyright (C) 2007 Texas Instruments, Inc. |
9 | * Rajendra Nayak <rnayak@ti.com> | |
10 | * | |
8bd22949 KH |
11 | * Copyright (C) 2005 Texas Instruments, Inc. |
12 | * Richard Woodruff <r-woodruff2@ti.com> | |
13 | * | |
14 | * Based on pm.c for omap1 | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/pm.h> | |
22 | #include <linux/suspend.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/gpio.h> | |
c40552bc | 28 | #include <linux/clk.h> |
8bd22949 | 29 | |
ce491cf8 TL |
30 | #include <plat/sram.h> |
31 | #include <plat/clockdomain.h> | |
32 | #include <plat/powerdomain.h> | |
33 | #include <plat/control.h> | |
34 | #include <plat/serial.h> | |
61255ab9 | 35 | #include <plat/sdrc.h> |
2f5939c3 RN |
36 | #include <plat/prcm.h> |
37 | #include <plat/gpmc.h> | |
f2d11858 | 38 | #include <plat/dma.h> |
d7814e4d | 39 | #include <plat/dmtimer.h> |
8bd22949 | 40 | |
57f277b0 RN |
41 | #include <asm/tlbflush.h> |
42 | ||
8bd22949 KH |
43 | #include "cm.h" |
44 | #include "cm-regbits-34xx.h" | |
45 | #include "prm-regbits-34xx.h" | |
46 | ||
47 | #include "prm.h" | |
48 | #include "pm.h" | |
13a6fe0f TK |
49 | #include "sdrc.h" |
50 | ||
2f5939c3 RN |
51 | /* Scratchpad offsets */ |
52 | #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31 | |
53 | #define OMAP343X_TABLE_VALUE_OFFSET 0x30 | |
54 | #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 | |
55 | ||
c40552bc KH |
56 | u32 enable_off_mode; |
57 | u32 sleep_while_idle; | |
d7814e4d | 58 | u32 wakeup_timer_seconds; |
c40552bc | 59 | |
8bd22949 KH |
60 | struct power_state { |
61 | struct powerdomain *pwrdm; | |
62 | u32 next_state; | |
10f90ed2 | 63 | #ifdef CONFIG_SUSPEND |
8bd22949 | 64 | u32 saved_state; |
10f90ed2 | 65 | #endif |
8bd22949 KH |
66 | struct list_head node; |
67 | }; | |
68 | ||
69 | static LIST_HEAD(pwrst_list); | |
70 | ||
71 | static void (*_omap_sram_idle)(u32 *addr, int save_state); | |
72 | ||
27d59a4a TK |
73 | static int (*_omap_save_secure_sram)(u32 *addr); |
74 | ||
fa3c2a4f RN |
75 | static struct powerdomain *mpu_pwrdm, *neon_pwrdm; |
76 | static struct powerdomain *core_pwrdm, *per_pwrdm; | |
c16c3f67 | 77 | static struct powerdomain *cam_pwrdm; |
fa3c2a4f | 78 | |
2f5939c3 RN |
79 | static inline void omap3_per_save_context(void) |
80 | { | |
81 | omap_gpio_save_context(); | |
82 | } | |
83 | ||
84 | static inline void omap3_per_restore_context(void) | |
85 | { | |
86 | omap_gpio_restore_context(); | |
87 | } | |
88 | ||
3a7ec26b KJ |
89 | static void omap3_enable_io_chain(void) |
90 | { | |
91 | int timeout = 0; | |
92 | ||
93 | if (omap_rev() >= OMAP3430_REV_ES3_1) { | |
94 | prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); | |
95 | /* Do a readback to assure write has been done */ | |
96 | prm_read_mod_reg(WKUP_MOD, PM_WKEN); | |
97 | ||
98 | while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) & | |
99 | OMAP3430_ST_IO_CHAIN)) { | |
100 | timeout++; | |
101 | if (timeout > 1000) { | |
102 | printk(KERN_ERR "Wake up daisy chain " | |
103 | "activation failed.\n"); | |
104 | return; | |
105 | } | |
106 | prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN, | |
107 | WKUP_MOD, PM_WKST); | |
108 | } | |
109 | } | |
110 | } | |
111 | ||
112 | static void omap3_disable_io_chain(void) | |
113 | { | |
114 | if (omap_rev() >= OMAP3430_REV_ES3_1) | |
115 | prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN); | |
116 | } | |
117 | ||
2f5939c3 RN |
118 | static void omap3_core_save_context(void) |
119 | { | |
120 | u32 control_padconf_off; | |
121 | ||
122 | /* Save the padconf registers */ | |
123 | control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); | |
124 | control_padconf_off |= START_PADCONF_SAVE; | |
125 | omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); | |
126 | /* wait for the save to complete */ | |
1b6e821f RK |
127 | while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) |
128 | & PADCONF_SAVE_DONE)) | |
2f5939c3 RN |
129 | ; |
130 | /* Save the Interrupt controller context */ | |
131 | omap_intc_save_context(); | |
132 | /* Save the GPMC context */ | |
133 | omap3_gpmc_save_context(); | |
134 | /* Save the system control module context, padconf already save above*/ | |
135 | omap3_control_save_context(); | |
f2d11858 | 136 | omap_dma_global_context_save(); |
2f5939c3 RN |
137 | } |
138 | ||
139 | static void omap3_core_restore_context(void) | |
140 | { | |
141 | /* Restore the control module context, padconf restored by h/w */ | |
142 | omap3_control_restore_context(); | |
143 | /* Restore the GPMC context */ | |
144 | omap3_gpmc_restore_context(); | |
145 | /* Restore the interrupt controller context */ | |
146 | omap_intc_restore_context(); | |
f2d11858 | 147 | omap_dma_global_context_restore(); |
2f5939c3 RN |
148 | } |
149 | ||
9d97140b TK |
150 | /* |
151 | * FIXME: This function should be called before entering off-mode after | |
152 | * OMAP3 secure services have been accessed. Currently it is only called | |
153 | * once during boot sequence, but this works as we are not using secure | |
154 | * services. | |
155 | */ | |
27d59a4a TK |
156 | static void omap3_save_secure_ram_context(u32 target_mpu_state) |
157 | { | |
158 | u32 ret; | |
159 | ||
160 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | |
27d59a4a TK |
161 | /* |
162 | * MPU next state must be set to POWER_ON temporarily, | |
163 | * otherwise the WFI executed inside the ROM code | |
164 | * will hang the system. | |
165 | */ | |
166 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | |
167 | ret = _omap_save_secure_sram((u32 *) | |
168 | __pa(omap3_secure_ram_storage)); | |
169 | pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); | |
170 | /* Following is for error tracking, it should not happen */ | |
171 | if (ret) { | |
172 | printk(KERN_ERR "save_secure_sram() returns %08x\n", | |
173 | ret); | |
174 | while (1) | |
175 | ; | |
176 | } | |
177 | } | |
178 | } | |
179 | ||
77da2d91 JH |
180 | /* |
181 | * PRCM Interrupt Handler Helper Function | |
182 | * | |
183 | * The purpose of this function is to clear any wake-up events latched | |
184 | * in the PRCM PM_WKST_x registers. It is possible that a wake-up event | |
185 | * may occur whilst attempting to clear a PM_WKST_x register and thus | |
186 | * set another bit in this register. A while loop is used to ensure | |
187 | * that any peripheral wake-up events occurring while attempting to | |
188 | * clear the PM_WKST_x are detected and cleared. | |
189 | */ | |
8cb0ac99 | 190 | static int prcm_clear_mod_irqs(s16 module, u8 regs) |
8bd22949 | 191 | { |
71a80775 | 192 | u32 wkst, fclk, iclk, clken; |
77da2d91 JH |
193 | u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; |
194 | u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; | |
195 | u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; | |
5d805978 PW |
196 | u16 grpsel_off = (regs == 3) ? |
197 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; | |
8cb0ac99 | 198 | int c = 0; |
8bd22949 | 199 | |
77da2d91 | 200 | wkst = prm_read_mod_reg(module, wkst_off); |
5d805978 | 201 | wkst &= prm_read_mod_reg(module, grpsel_off); |
8bd22949 | 202 | if (wkst) { |
77da2d91 JH |
203 | iclk = cm_read_mod_reg(module, iclk_off); |
204 | fclk = cm_read_mod_reg(module, fclk_off); | |
205 | while (wkst) { | |
71a80775 VP |
206 | clken = wkst; |
207 | cm_set_mod_reg_bits(clken, module, iclk_off); | |
208 | /* | |
209 | * For USBHOST, we don't know whether HOST1 or | |
210 | * HOST2 woke us up, so enable both f-clocks | |
211 | */ | |
212 | if (module == OMAP3430ES2_USBHOST_MOD) | |
213 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; | |
214 | cm_set_mod_reg_bits(clken, module, fclk_off); | |
77da2d91 JH |
215 | prm_write_mod_reg(wkst, module, wkst_off); |
216 | wkst = prm_read_mod_reg(module, wkst_off); | |
8cb0ac99 | 217 | c++; |
77da2d91 JH |
218 | } |
219 | cm_write_mod_reg(iclk, module, iclk_off); | |
220 | cm_write_mod_reg(fclk, module, fclk_off); | |
8bd22949 | 221 | } |
8cb0ac99 PW |
222 | |
223 | return c; | |
224 | } | |
225 | ||
226 | static int _prcm_int_handle_wakeup(void) | |
227 | { | |
228 | int c; | |
229 | ||
230 | c = prcm_clear_mod_irqs(WKUP_MOD, 1); | |
231 | c += prcm_clear_mod_irqs(CORE_MOD, 1); | |
232 | c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); | |
233 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
234 | c += prcm_clear_mod_irqs(CORE_MOD, 3); | |
235 | c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); | |
236 | } | |
237 | ||
238 | return c; | |
77da2d91 | 239 | } |
8bd22949 | 240 | |
77da2d91 JH |
241 | /* |
242 | * PRCM Interrupt Handler | |
243 | * | |
244 | * The PRM_IRQSTATUS_MPU register indicates if there are any pending | |
245 | * interrupts from the PRCM for the MPU. These bits must be cleared in | |
246 | * order to clear the PRCM interrupt. The PRCM interrupt handler is | |
247 | * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear | |
248 | * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU | |
249 | * register indicates that a wake-up event is pending for the MPU and | |
250 | * this bit can only be cleared if the all the wake-up events latched | |
251 | * in the various PM_WKST_x registers have been cleared. The interrupt | |
252 | * handler is implemented using a do-while loop so that if a wake-up | |
253 | * event occurred during the processing of the prcm interrupt handler | |
254 | * (setting a bit in the corresponding PM_WKST_x register and thus | |
255 | * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) | |
256 | * this would be handled. | |
257 | */ | |
258 | static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) | |
259 | { | |
260 | u32 irqstatus_mpu; | |
8cb0ac99 | 261 | int c = 0; |
77da2d91 JH |
262 | |
263 | do { | |
77da2d91 JH |
264 | irqstatus_mpu = prm_read_mod_reg(OCP_MOD, |
265 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | |
8cb0ac99 PW |
266 | |
267 | if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) { | |
268 | c = _prcm_int_handle_wakeup(); | |
269 | ||
270 | /* | |
271 | * Is the MPU PRCM interrupt handler racing with the | |
272 | * IVA2 PRCM interrupt handler ? | |
273 | */ | |
274 | WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " | |
275 | "but no wakeup sources are marked\n"); | |
276 | } else { | |
277 | /* XXX we need to expand our PRCM interrupt handler */ | |
278 | WARN(1, "prcm: WARNING: PRCM interrupt received, but " | |
279 | "no code to handle it (%08x)\n", irqstatus_mpu); | |
280 | } | |
281 | ||
77da2d91 JH |
282 | prm_write_mod_reg(irqstatus_mpu, OCP_MOD, |
283 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | |
8bd22949 | 284 | |
77da2d91 | 285 | } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); |
8bd22949 KH |
286 | |
287 | return IRQ_HANDLED; | |
288 | } | |
289 | ||
57f277b0 RN |
290 | static void restore_control_register(u32 val) |
291 | { | |
292 | __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); | |
293 | } | |
294 | ||
295 | /* Function to restore the table entry that was modified for enabling MMU */ | |
296 | static void restore_table_entry(void) | |
297 | { | |
298 | u32 *scratchpad_address; | |
299 | u32 previous_value, control_reg_value; | |
300 | u32 *address; | |
301 | ||
302 | scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); | |
303 | ||
304 | /* Get address of entry that was modified */ | |
305 | address = (u32 *)__raw_readl(scratchpad_address + | |
306 | OMAP343X_TABLE_ADDRESS_OFFSET); | |
307 | /* Get the previous value which needs to be restored */ | |
308 | previous_value = __raw_readl(scratchpad_address + | |
309 | OMAP343X_TABLE_VALUE_OFFSET); | |
310 | address = __va(address); | |
311 | *address = previous_value; | |
312 | flush_tlb_all(); | |
313 | control_reg_value = __raw_readl(scratchpad_address | |
314 | + OMAP343X_CONTROL_REG_VALUE_OFFSET); | |
315 | /* This will enable caches and prediction */ | |
316 | restore_control_register(control_reg_value); | |
317 | } | |
318 | ||
99e6a4d2 | 319 | void omap_sram_idle(void) |
8bd22949 KH |
320 | { |
321 | /* Variable to tell what needs to be saved and restored | |
322 | * in omap_sram_idle*/ | |
323 | /* save_state = 0 => Nothing to save and restored */ | |
324 | /* save_state = 1 => Only L1 and logic lost */ | |
325 | /* save_state = 2 => Only L2 lost */ | |
326 | /* save_state = 3 => L1, L2 and logic lost */ | |
fa3c2a4f RN |
327 | int save_state = 0; |
328 | int mpu_next_state = PWRDM_POWER_ON; | |
329 | int per_next_state = PWRDM_POWER_ON; | |
330 | int core_next_state = PWRDM_POWER_ON; | |
2f5939c3 | 331 | int core_prev_state, per_prev_state; |
13a6fe0f | 332 | u32 sdrc_pwr = 0; |
ecf157d0 | 333 | int per_state_modified = 0; |
8bd22949 KH |
334 | |
335 | if (!_omap_sram_idle) | |
336 | return; | |
337 | ||
fa3c2a4f RN |
338 | pwrdm_clear_all_prev_pwrst(mpu_pwrdm); |
339 | pwrdm_clear_all_prev_pwrst(neon_pwrdm); | |
340 | pwrdm_clear_all_prev_pwrst(core_pwrdm); | |
341 | pwrdm_clear_all_prev_pwrst(per_pwrdm); | |
342 | ||
8bd22949 KH |
343 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
344 | switch (mpu_next_state) { | |
fa3c2a4f | 345 | case PWRDM_POWER_ON: |
8bd22949 KH |
346 | case PWRDM_POWER_RET: |
347 | /* No need to save context */ | |
348 | save_state = 0; | |
349 | break; | |
61255ab9 RN |
350 | case PWRDM_POWER_OFF: |
351 | save_state = 3; | |
352 | break; | |
8bd22949 KH |
353 | default: |
354 | /* Invalid state */ | |
355 | printk(KERN_ERR "Invalid mpu state in sram_idle\n"); | |
356 | return; | |
357 | } | |
fe617af7 PDS |
358 | pwrdm_pre_transition(); |
359 | ||
fa3c2a4f RN |
360 | /* NEON control */ |
361 | if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) | |
7139178e | 362 | pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); |
fa3c2a4f | 363 | |
658ce97e KH |
364 | /* PER */ |
365 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); | |
ecf157d0 | 366 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
658ce97e | 367 | if (per_next_state < PWRDM_POWER_ON) { |
658ce97e | 368 | omap_uart_prepare_idle(2); |
ecf157d0 TK |
369 | omap2_gpio_prepare_for_retention(); |
370 | if (per_next_state == PWRDM_POWER_OFF) { | |
371 | if (core_next_state == PWRDM_POWER_ON) { | |
372 | per_next_state = PWRDM_POWER_RET; | |
373 | pwrdm_set_next_pwrst(per_pwrdm, per_next_state); | |
374 | per_state_modified = 1; | |
375 | } else | |
376 | omap3_per_save_context(); | |
377 | } | |
658ce97e KH |
378 | } |
379 | ||
c16c3f67 TK |
380 | if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) |
381 | omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]); | |
382 | ||
658ce97e | 383 | /* CORE */ |
fa3c2a4f | 384 | if (core_next_state < PWRDM_POWER_ON) { |
fa3c2a4f RN |
385 | omap_uart_prepare_idle(0); |
386 | omap_uart_prepare_idle(1); | |
2f5939c3 RN |
387 | if (core_next_state == PWRDM_POWER_OFF) { |
388 | omap3_core_save_context(); | |
389 | omap3_prcm_save_context(); | |
390 | } | |
3a7ec26b | 391 | /* Enable IO-PAD and IO-CHAIN wakeups */ |
fa3c2a4f | 392 | prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); |
3a7ec26b | 393 | omap3_enable_io_chain(); |
fa3c2a4f | 394 | } |
f18cc2ff | 395 | omap3_intc_prepare_idle(); |
8bd22949 | 396 | |
13a6fe0f | 397 | /* |
f265dc4c RN |
398 | * On EMU/HS devices ROM code restores a SRDC value |
399 | * from scratchpad which has automatic self refresh on timeout | |
400 | * of AUTO_CNT = 1 enabled. This takes care of errata 1.142. | |
401 | * Hence store/restore the SDRC_POWER register here. | |
402 | */ | |
13a6fe0f TK |
403 | if (omap_rev() >= OMAP3430_REV_ES3_0 && |
404 | omap_type() != OMAP2_DEVICE_TYPE_GP && | |
f265dc4c | 405 | core_next_state == PWRDM_POWER_OFF) |
13a6fe0f | 406 | sdrc_pwr = sdrc_read_reg(SDRC_POWER); |
13a6fe0f | 407 | |
61255ab9 RN |
408 | /* |
409 | * omap3_arm_context is the location where ARM registers | |
410 | * get saved. The restore path then reads from this | |
411 | * location and restores them back. | |
412 | */ | |
413 | _omap_sram_idle(omap3_arm_context, save_state); | |
8bd22949 KH |
414 | cpu_init(); |
415 | ||
f265dc4c | 416 | /* Restore normal SDRC POWER settings */ |
13a6fe0f TK |
417 | if (omap_rev() >= OMAP3430_REV_ES3_0 && |
418 | omap_type() != OMAP2_DEVICE_TYPE_GP && | |
419 | core_next_state == PWRDM_POWER_OFF) | |
420 | sdrc_write_reg(sdrc_pwr, SDRC_POWER); | |
421 | ||
57f277b0 RN |
422 | /* Restore table entry modified during MMU restoration */ |
423 | if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) | |
424 | restore_table_entry(); | |
425 | ||
658ce97e | 426 | /* CORE */ |
fa3c2a4f | 427 | if (core_next_state < PWRDM_POWER_ON) { |
2f5939c3 RN |
428 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); |
429 | if (core_prev_state == PWRDM_POWER_OFF) { | |
430 | omap3_core_restore_context(); | |
431 | omap3_prcm_restore_context(); | |
432 | omap3_sram_restore_context(); | |
8a917d2f | 433 | omap2_sms_restore_context(); |
2f5939c3 | 434 | } |
658ce97e KH |
435 | omap_uart_resume_idle(0); |
436 | omap_uart_resume_idle(1); | |
437 | if (core_next_state == PWRDM_POWER_OFF) | |
438 | prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF, | |
439 | OMAP3430_GR_MOD, | |
440 | OMAP3_PRM_VOLTCTRL_OFFSET); | |
441 | } | |
f18cc2ff | 442 | omap3_intc_resume_idle(); |
658ce97e KH |
443 | |
444 | /* PER */ | |
445 | if (per_next_state < PWRDM_POWER_ON) { | |
446 | per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); | |
658ce97e KH |
447 | if (per_prev_state == PWRDM_POWER_OFF) |
448 | omap3_per_restore_context(); | |
fa3c2a4f | 449 | omap2_gpio_resume_after_retention(); |
ecf157d0 TK |
450 | omap_uart_resume_idle(2); |
451 | if (per_state_modified) | |
452 | pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); | |
fa3c2a4f | 453 | } |
fe617af7 | 454 | |
3a7ec26b KJ |
455 | /* Disable IO-PAD and IO-CHAIN wakeup */ |
456 | if (core_next_state < PWRDM_POWER_ON) { | |
658ce97e | 457 | prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); |
3a7ec26b KJ |
458 | omap3_disable_io_chain(); |
459 | } | |
658ce97e | 460 | |
fe617af7 PDS |
461 | pwrdm_post_transition(); |
462 | ||
c16c3f67 | 463 | omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); |
8bd22949 KH |
464 | } |
465 | ||
20b01669 | 466 | int omap3_can_sleep(void) |
8bd22949 | 467 | { |
c40552bc KH |
468 | if (!sleep_while_idle) |
469 | return 0; | |
4af4016c KH |
470 | if (!omap_uart_can_sleep()) |
471 | return 0; | |
8bd22949 KH |
472 | return 1; |
473 | } | |
474 | ||
475 | /* This sets pwrdm state (other than mpu & core. Currently only ON & | |
476 | * RET are supported. Function is assuming that clkdm doesn't have | |
477 | * hw_sup mode enabled. */ | |
20b01669 | 478 | int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) |
8bd22949 KH |
479 | { |
480 | u32 cur_state; | |
481 | int sleep_switch = 0; | |
482 | int ret = 0; | |
483 | ||
484 | if (pwrdm == NULL || IS_ERR(pwrdm)) | |
485 | return -EINVAL; | |
486 | ||
487 | while (!(pwrdm->pwrsts & (1 << state))) { | |
488 | if (state == PWRDM_POWER_OFF) | |
489 | return ret; | |
490 | state--; | |
491 | } | |
492 | ||
493 | cur_state = pwrdm_read_next_pwrst(pwrdm); | |
494 | if (cur_state == state) | |
495 | return ret; | |
496 | ||
497 | if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { | |
498 | omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); | |
499 | sleep_switch = 1; | |
500 | pwrdm_wait_transition(pwrdm); | |
501 | } | |
502 | ||
503 | ret = pwrdm_set_next_pwrst(pwrdm, state); | |
504 | if (ret) { | |
505 | printk(KERN_ERR "Unable to set state of powerdomain: %s\n", | |
506 | pwrdm->name); | |
507 | goto err; | |
508 | } | |
509 | ||
510 | if (sleep_switch) { | |
511 | omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); | |
512 | pwrdm_wait_transition(pwrdm); | |
fe617af7 | 513 | pwrdm_state_switch(pwrdm); |
8bd22949 KH |
514 | } |
515 | ||
516 | err: | |
517 | return ret; | |
518 | } | |
519 | ||
520 | static void omap3_pm_idle(void) | |
521 | { | |
522 | local_irq_disable(); | |
523 | local_fiq_disable(); | |
524 | ||
525 | if (!omap3_can_sleep()) | |
526 | goto out; | |
527 | ||
cf22854c | 528 | if (omap_irq_pending() || need_resched()) |
8bd22949 KH |
529 | goto out; |
530 | ||
531 | omap_sram_idle(); | |
532 | ||
533 | out: | |
534 | local_fiq_enable(); | |
535 | local_irq_enable(); | |
536 | } | |
537 | ||
10f90ed2 | 538 | #ifdef CONFIG_SUSPEND |
2466211e TK |
539 | static suspend_state_t suspend_state; |
540 | ||
d7814e4d KH |
541 | static void omap2_pm_wakeup_on_timer(u32 seconds) |
542 | { | |
543 | u32 tick_rate, cycles; | |
544 | ||
545 | if (!seconds) | |
546 | return; | |
547 | ||
548 | tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); | |
549 | cycles = tick_rate * seconds; | |
550 | omap_dm_timer_stop(gptimer_wakeup); | |
551 | omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); | |
552 | ||
553 | pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n", | |
554 | seconds, cycles, tick_rate); | |
555 | } | |
556 | ||
8bd22949 KH |
557 | static int omap3_pm_prepare(void) |
558 | { | |
559 | disable_hlt(); | |
560 | return 0; | |
561 | } | |
562 | ||
563 | static int omap3_pm_suspend(void) | |
564 | { | |
565 | struct power_state *pwrst; | |
566 | int state, ret = 0; | |
567 | ||
d7814e4d KH |
568 | if (wakeup_timer_seconds) |
569 | omap2_pm_wakeup_on_timer(wakeup_timer_seconds); | |
570 | ||
8bd22949 KH |
571 | /* Read current next_pwrsts */ |
572 | list_for_each_entry(pwrst, &pwrst_list, node) | |
573 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | |
574 | /* Set ones wanted by suspend */ | |
575 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
576 | if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) | |
577 | goto restore; | |
578 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) | |
579 | goto restore; | |
580 | } | |
581 | ||
4af4016c | 582 | omap_uart_prepare_suspend(); |
2bbe3af3 TK |
583 | omap3_intc_suspend(); |
584 | ||
8bd22949 KH |
585 | omap_sram_idle(); |
586 | ||
587 | restore: | |
588 | /* Restore next_pwrsts */ | |
589 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
8bd22949 KH |
590 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
591 | if (state > pwrst->next_state) { | |
592 | printk(KERN_INFO "Powerdomain (%s) didn't enter " | |
593 | "target state %d\n", | |
594 | pwrst->pwrdm->name, pwrst->next_state); | |
595 | ret = -1; | |
596 | } | |
6c5f8039 | 597 | set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
8bd22949 KH |
598 | } |
599 | if (ret) | |
600 | printk(KERN_ERR "Could not enter target state in pm_suspend\n"); | |
601 | else | |
602 | printk(KERN_INFO "Successfully put all powerdomains " | |
603 | "to target state\n"); | |
604 | ||
605 | return ret; | |
606 | } | |
607 | ||
2466211e | 608 | static int omap3_pm_enter(suspend_state_t unused) |
8bd22949 KH |
609 | { |
610 | int ret = 0; | |
611 | ||
2466211e | 612 | switch (suspend_state) { |
8bd22949 KH |
613 | case PM_SUSPEND_STANDBY: |
614 | case PM_SUSPEND_MEM: | |
615 | ret = omap3_pm_suspend(); | |
616 | break; | |
617 | default: | |
618 | ret = -EINVAL; | |
619 | } | |
620 | ||
621 | return ret; | |
622 | } | |
623 | ||
624 | static void omap3_pm_finish(void) | |
625 | { | |
626 | enable_hlt(); | |
627 | } | |
628 | ||
2466211e TK |
629 | /* Hooks to enable / disable UART interrupts during suspend */ |
630 | static int omap3_pm_begin(suspend_state_t state) | |
631 | { | |
632 | suspend_state = state; | |
633 | omap_uart_enable_irqs(0); | |
634 | return 0; | |
635 | } | |
636 | ||
637 | static void omap3_pm_end(void) | |
638 | { | |
639 | suspend_state = PM_SUSPEND_ON; | |
640 | omap_uart_enable_irqs(1); | |
641 | return; | |
642 | } | |
643 | ||
8bd22949 | 644 | static struct platform_suspend_ops omap_pm_ops = { |
2466211e TK |
645 | .begin = omap3_pm_begin, |
646 | .end = omap3_pm_end, | |
8bd22949 KH |
647 | .prepare = omap3_pm_prepare, |
648 | .enter = omap3_pm_enter, | |
649 | .finish = omap3_pm_finish, | |
650 | .valid = suspend_valid_only_mem, | |
651 | }; | |
10f90ed2 | 652 | #endif /* CONFIG_SUSPEND */ |
8bd22949 | 653 | |
1155e426 KH |
654 | |
655 | /** | |
656 | * omap3_iva_idle(): ensure IVA is in idle so it can be put into | |
657 | * retention | |
658 | * | |
659 | * In cases where IVA2 is activated by bootcode, it may prevent | |
660 | * full-chip retention or off-mode because it is not idle. This | |
661 | * function forces the IVA2 into idle state so it can go | |
662 | * into retention/off and thus allow full-chip retention/off. | |
663 | * | |
664 | **/ | |
665 | static void __init omap3_iva_idle(void) | |
666 | { | |
667 | /* ensure IVA2 clock is disabled */ | |
668 | cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); | |
669 | ||
670 | /* if no clock activity, nothing else to do */ | |
671 | if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & | |
672 | OMAP3430_CLKACTIVITY_IVA2_MASK)) | |
673 | return; | |
674 | ||
675 | /* Reset IVA2 */ | |
676 | prm_write_mod_reg(OMAP3430_RST1_IVA2 | | |
677 | OMAP3430_RST2_IVA2 | | |
678 | OMAP3430_RST3_IVA2, | |
679 | OMAP3430_IVA2_MOD, RM_RSTCTRL); | |
680 | ||
681 | /* Enable IVA2 clock */ | |
682 | cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, | |
683 | OMAP3430_IVA2_MOD, CM_FCLKEN); | |
684 | ||
685 | /* Set IVA2 boot mode to 'idle' */ | |
686 | omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, | |
687 | OMAP343X_CONTROL_IVA2_BOOTMOD); | |
688 | ||
689 | /* Un-reset IVA2 */ | |
690 | prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); | |
691 | ||
692 | /* Disable IVA2 clock */ | |
693 | cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); | |
694 | ||
695 | /* Reset IVA2 */ | |
696 | prm_write_mod_reg(OMAP3430_RST1_IVA2 | | |
697 | OMAP3430_RST2_IVA2 | | |
698 | OMAP3430_RST3_IVA2, | |
699 | OMAP3430_IVA2_MOD, RM_RSTCTRL); | |
700 | } | |
701 | ||
8111b221 | 702 | static void __init omap3_d2d_idle(void) |
8bd22949 | 703 | { |
8111b221 KH |
704 | u16 mask, padconf; |
705 | ||
706 | /* In a stand alone OMAP3430 where there is not a stacked | |
707 | * modem for the D2D Idle Ack and D2D MStandby must be pulled | |
708 | * high. S CONTROL_PADCONF_SAD2D_IDLEACK and | |
709 | * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ | |
710 | mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ | |
711 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); | |
712 | padconf |= mask; | |
713 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); | |
714 | ||
715 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); | |
716 | padconf |= mask; | |
717 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); | |
718 | ||
8bd22949 KH |
719 | /* reset modem */ |
720 | prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | | |
721 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, | |
722 | CORE_MOD, RM_RSTCTRL); | |
723 | prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); | |
8111b221 | 724 | } |
8bd22949 | 725 | |
8111b221 KH |
726 | static void __init prcm_setup_regs(void) |
727 | { | |
8bd22949 KH |
728 | /* XXX Reset all wkdeps. This should be done when initializing |
729 | * powerdomains */ | |
730 | prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); | |
731 | prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); | |
732 | prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); | |
733 | prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); | |
734 | prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); | |
735 | prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); | |
736 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
737 | prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); | |
738 | prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); | |
739 | } else | |
740 | prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); | |
741 | ||
742 | /* | |
743 | * Enable interface clock autoidle for all modules. | |
744 | * Note that in the long run this should be done by clockfw | |
745 | */ | |
746 | cm_write_mod_reg( | |
8111b221 | 747 | OMAP3430_AUTO_MODEM | |
8bd22949 KH |
748 | OMAP3430ES2_AUTO_MMC3 | |
749 | OMAP3430ES2_AUTO_ICR | | |
750 | OMAP3430_AUTO_AES2 | | |
751 | OMAP3430_AUTO_SHA12 | | |
752 | OMAP3430_AUTO_DES2 | | |
753 | OMAP3430_AUTO_MMC2 | | |
754 | OMAP3430_AUTO_MMC1 | | |
755 | OMAP3430_AUTO_MSPRO | | |
756 | OMAP3430_AUTO_HDQ | | |
757 | OMAP3430_AUTO_MCSPI4 | | |
758 | OMAP3430_AUTO_MCSPI3 | | |
759 | OMAP3430_AUTO_MCSPI2 | | |
760 | OMAP3430_AUTO_MCSPI1 | | |
761 | OMAP3430_AUTO_I2C3 | | |
762 | OMAP3430_AUTO_I2C2 | | |
763 | OMAP3430_AUTO_I2C1 | | |
764 | OMAP3430_AUTO_UART2 | | |
765 | OMAP3430_AUTO_UART1 | | |
766 | OMAP3430_AUTO_GPT11 | | |
767 | OMAP3430_AUTO_GPT10 | | |
768 | OMAP3430_AUTO_MCBSP5 | | |
769 | OMAP3430_AUTO_MCBSP1 | | |
770 | OMAP3430ES1_AUTO_FAC | /* This is es1 only */ | |
771 | OMAP3430_AUTO_MAILBOXES | | |
772 | OMAP3430_AUTO_OMAPCTRL | | |
773 | OMAP3430ES1_AUTO_FSHOSTUSB | | |
774 | OMAP3430_AUTO_HSOTGUSB | | |
8111b221 | 775 | OMAP3430_AUTO_SAD2D | |
8bd22949 KH |
776 | OMAP3430_AUTO_SSI, |
777 | CORE_MOD, CM_AUTOIDLE1); | |
778 | ||
779 | cm_write_mod_reg( | |
780 | OMAP3430_AUTO_PKA | | |
781 | OMAP3430_AUTO_AES1 | | |
782 | OMAP3430_AUTO_RNG | | |
783 | OMAP3430_AUTO_SHA11 | | |
784 | OMAP3430_AUTO_DES1, | |
785 | CORE_MOD, CM_AUTOIDLE2); | |
786 | ||
787 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
788 | cm_write_mod_reg( | |
8111b221 | 789 | OMAP3430_AUTO_MAD2D | |
8bd22949 KH |
790 | OMAP3430ES2_AUTO_USBTLL, |
791 | CORE_MOD, CM_AUTOIDLE3); | |
792 | } | |
793 | ||
794 | cm_write_mod_reg( | |
795 | OMAP3430_AUTO_WDT2 | | |
796 | OMAP3430_AUTO_WDT1 | | |
797 | OMAP3430_AUTO_GPIO1 | | |
798 | OMAP3430_AUTO_32KSYNC | | |
799 | OMAP3430_AUTO_GPT12 | | |
800 | OMAP3430_AUTO_GPT1 , | |
801 | WKUP_MOD, CM_AUTOIDLE); | |
802 | ||
803 | cm_write_mod_reg( | |
804 | OMAP3430_AUTO_DSS, | |
805 | OMAP3430_DSS_MOD, | |
806 | CM_AUTOIDLE); | |
807 | ||
808 | cm_write_mod_reg( | |
809 | OMAP3430_AUTO_CAM, | |
810 | OMAP3430_CAM_MOD, | |
811 | CM_AUTOIDLE); | |
812 | ||
813 | cm_write_mod_reg( | |
814 | OMAP3430_AUTO_GPIO6 | | |
815 | OMAP3430_AUTO_GPIO5 | | |
816 | OMAP3430_AUTO_GPIO4 | | |
817 | OMAP3430_AUTO_GPIO3 | | |
818 | OMAP3430_AUTO_GPIO2 | | |
819 | OMAP3430_AUTO_WDT3 | | |
820 | OMAP3430_AUTO_UART3 | | |
821 | OMAP3430_AUTO_GPT9 | | |
822 | OMAP3430_AUTO_GPT8 | | |
823 | OMAP3430_AUTO_GPT7 | | |
824 | OMAP3430_AUTO_GPT6 | | |
825 | OMAP3430_AUTO_GPT5 | | |
826 | OMAP3430_AUTO_GPT4 | | |
827 | OMAP3430_AUTO_GPT3 | | |
828 | OMAP3430_AUTO_GPT2 | | |
829 | OMAP3430_AUTO_MCBSP4 | | |
830 | OMAP3430_AUTO_MCBSP3 | | |
831 | OMAP3430_AUTO_MCBSP2, | |
832 | OMAP3430_PER_MOD, | |
833 | CM_AUTOIDLE); | |
834 | ||
835 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
836 | cm_write_mod_reg( | |
837 | OMAP3430ES2_AUTO_USBHOST, | |
838 | OMAP3430ES2_USBHOST_MOD, | |
839 | CM_AUTOIDLE); | |
840 | } | |
841 | ||
b296c811 TK |
842 | omap_ctrl_writel(OMAP3430_AUTOIDLE, OMAP2_CONTROL_SYSCONFIG); |
843 | ||
8bd22949 KH |
844 | /* |
845 | * Set all plls to autoidle. This is needed until autoidle is | |
846 | * enabled by clockfw | |
847 | */ | |
848 | cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, | |
849 | OMAP3430_IVA2_MOD, CM_AUTOIDLE2); | |
850 | cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, | |
851 | MPU_MOD, | |
852 | CM_AUTOIDLE2); | |
853 | cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | | |
854 | (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), | |
855 | PLL_MOD, | |
856 | CM_AUTOIDLE); | |
857 | cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, | |
858 | PLL_MOD, | |
859 | CM_AUTOIDLE2); | |
860 | ||
861 | /* | |
862 | * Enable control of expternal oscillator through | |
863 | * sys_clkreq. In the long run clock framework should | |
864 | * take care of this. | |
865 | */ | |
866 | prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, | |
867 | 1 << OMAP_AUTOEXTCLKMODE_SHIFT, | |
868 | OMAP3430_GR_MOD, | |
869 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | |
870 | ||
871 | /* setup wakup source */ | |
872 | prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | | |
873 | OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, | |
874 | WKUP_MOD, PM_WKEN); | |
875 | /* No need to write EN_IO, that is always enabled */ | |
876 | prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | | |
877 | OMAP3430_EN_GPT12, | |
878 | WKUP_MOD, OMAP3430_PM_MPUGRPSEL); | |
879 | /* For some reason IO doesn't generate wakeup event even if | |
880 | * it is selected to mpu wakeup goup */ | |
881 | prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, | |
882 | OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); | |
1155e426 | 883 | |
b427f92f | 884 | /* Enable wakeups in PER */ |
eb350f74 KH |
885 | prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | |
886 | OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | | |
e3d93296 PU |
887 | OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3 | |
888 | OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | | |
889 | OMAP3430_EN_MCBSP4, | |
b427f92f | 890 | OMAP3430_PER_MOD, PM_WKEN); |
eb350f74 KH |
891 | /* and allow them to wake up MPU */ |
892 | prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | | |
893 | OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | | |
e3d93296 PU |
894 | OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3 | |
895 | OMAP3430_EN_MCBSP2 | OMAP3430_EN_MCBSP3 | | |
896 | OMAP3430_EN_MCBSP4, | |
eb350f74 KH |
897 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); |
898 | ||
d3fd3290 KH |
899 | /* Don't attach IVA interrupts */ |
900 | prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); | |
901 | prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); | |
902 | prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | |
903 | prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | |
904 | ||
b1340d17 KH |
905 | /* Clear any pending 'reset' flags */ |
906 | prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); | |
907 | prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); | |
908 | prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); | |
909 | prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); | |
910 | prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); | |
911 | prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); | |
912 | prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); | |
913 | ||
014c46db KH |
914 | /* Clear any pending PRCM interrupts */ |
915 | prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | |
916 | ||
1155e426 | 917 | omap3_iva_idle(); |
8111b221 | 918 | omap3_d2d_idle(); |
8bd22949 KH |
919 | } |
920 | ||
c40552bc KH |
921 | void omap3_pm_off_mode_enable(int enable) |
922 | { | |
923 | struct power_state *pwrst; | |
924 | u32 state; | |
925 | ||
926 | if (enable) | |
927 | state = PWRDM_POWER_OFF; | |
928 | else | |
929 | state = PWRDM_POWER_RET; | |
930 | ||
931 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
932 | pwrst->next_state = state; | |
933 | set_pwrdm_state(pwrst->pwrdm, state); | |
934 | } | |
935 | } | |
936 | ||
68d4778c TK |
937 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
938 | { | |
939 | struct power_state *pwrst; | |
940 | ||
941 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
942 | if (pwrst->pwrdm == pwrdm) | |
943 | return pwrst->next_state; | |
944 | } | |
945 | return -EINVAL; | |
946 | } | |
947 | ||
948 | int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) | |
949 | { | |
950 | struct power_state *pwrst; | |
951 | ||
952 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
953 | if (pwrst->pwrdm == pwrdm) { | |
954 | pwrst->next_state = state; | |
955 | return 0; | |
956 | } | |
957 | } | |
958 | return -EINVAL; | |
959 | } | |
960 | ||
a23456e9 | 961 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
8bd22949 KH |
962 | { |
963 | struct power_state *pwrst; | |
964 | ||
965 | if (!pwrdm->pwrsts) | |
966 | return 0; | |
967 | ||
d3d381c6 | 968 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
8bd22949 KH |
969 | if (!pwrst) |
970 | return -ENOMEM; | |
971 | pwrst->pwrdm = pwrdm; | |
972 | pwrst->next_state = PWRDM_POWER_RET; | |
973 | list_add(&pwrst->node, &pwrst_list); | |
974 | ||
975 | if (pwrdm_has_hdwr_sar(pwrdm)) | |
976 | pwrdm_enable_hdwr_sar(pwrdm); | |
977 | ||
978 | return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); | |
979 | } | |
980 | ||
981 | /* | |
982 | * Enable hw supervised mode for all clockdomains if it's | |
983 | * supported. Initiate sleep transition for other clockdomains, if | |
984 | * they are not used | |
985 | */ | |
a23456e9 | 986 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) |
8bd22949 KH |
987 | { |
988 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) | |
989 | omap2_clkdm_allow_idle(clkdm); | |
990 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && | |
991 | atomic_read(&clkdm->usecount) == 0) | |
992 | omap2_clkdm_sleep(clkdm); | |
993 | return 0; | |
994 | } | |
995 | ||
3231fc88 RN |
996 | void omap_push_sram_idle(void) |
997 | { | |
998 | _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, | |
999 | omap34xx_cpu_suspend_sz); | |
27d59a4a TK |
1000 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) |
1001 | _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, | |
1002 | save_secure_ram_context_sz); | |
3231fc88 RN |
1003 | } |
1004 | ||
7cc515f7 | 1005 | static int __init omap3_pm_init(void) |
8bd22949 KH |
1006 | { |
1007 | struct power_state *pwrst, *tmp; | |
1008 | int ret; | |
1009 | ||
1010 | if (!cpu_is_omap34xx()) | |
1011 | return -ENODEV; | |
1012 | ||
1013 | printk(KERN_ERR "Power Management for TI OMAP3.\n"); | |
1014 | ||
1015 | /* XXX prcm_setup_regs needs to be before enabling hw | |
1016 | * supervised mode for powerdomains */ | |
1017 | prcm_setup_regs(); | |
1018 | ||
1019 | ret = request_irq(INT_34XX_PRCM_MPU_IRQ, | |
1020 | (irq_handler_t)prcm_interrupt_handler, | |
1021 | IRQF_DISABLED, "prcm", NULL); | |
1022 | if (ret) { | |
1023 | printk(KERN_ERR "request_irq failed to register for 0x%x\n", | |
1024 | INT_34XX_PRCM_MPU_IRQ); | |
1025 | goto err1; | |
1026 | } | |
1027 | ||
a23456e9 | 1028 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
8bd22949 KH |
1029 | if (ret) { |
1030 | printk(KERN_ERR "Failed to setup powerdomains\n"); | |
1031 | goto err2; | |
1032 | } | |
1033 | ||
a23456e9 | 1034 | (void) clkdm_for_each(clkdms_setup, NULL); |
8bd22949 KH |
1035 | |
1036 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
1037 | if (mpu_pwrdm == NULL) { | |
1038 | printk(KERN_ERR "Failed to get mpu_pwrdm\n"); | |
1039 | goto err2; | |
1040 | } | |
1041 | ||
fa3c2a4f RN |
1042 | neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
1043 | per_pwrdm = pwrdm_lookup("per_pwrdm"); | |
1044 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
c16c3f67 | 1045 | cam_pwrdm = pwrdm_lookup("cam_pwrdm"); |
fa3c2a4f | 1046 | |
3231fc88 | 1047 | omap_push_sram_idle(); |
10f90ed2 | 1048 | #ifdef CONFIG_SUSPEND |
8bd22949 | 1049 | suspend_set_ops(&omap_pm_ops); |
10f90ed2 | 1050 | #endif /* CONFIG_SUSPEND */ |
8bd22949 KH |
1051 | |
1052 | pm_idle = omap3_pm_idle; | |
0343371e | 1053 | omap3_idle_init(); |
8bd22949 | 1054 | |
fa3c2a4f RN |
1055 | pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm); |
1056 | /* | |
1057 | * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for | |
1058 | * IO-pad wakeup. Otherwise it will unnecessarily waste power | |
1059 | * waking up PER with every CORE wakeup - see | |
1060 | * http://marc.info/?l=linux-omap&m=121852150710062&w=2 | |
1061 | */ | |
1062 | pwrdm_add_wkdep(per_pwrdm, core_pwrdm); | |
1063 | ||
27d59a4a TK |
1064 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
1065 | omap3_secure_ram_storage = | |
1066 | kmalloc(0x803F, GFP_KERNEL); | |
1067 | if (!omap3_secure_ram_storage) | |
1068 | printk(KERN_ERR "Memory allocation failed when" | |
1069 | "allocating for secure sram context\n"); | |
9d97140b TK |
1070 | |
1071 | local_irq_disable(); | |
1072 | local_fiq_disable(); | |
1073 | ||
1074 | omap_dma_global_context_save(); | |
1075 | omap3_save_secure_ram_context(PWRDM_POWER_ON); | |
1076 | omap_dma_global_context_restore(); | |
1077 | ||
1078 | local_irq_enable(); | |
1079 | local_fiq_enable(); | |
27d59a4a | 1080 | } |
27d59a4a | 1081 | |
9d97140b | 1082 | omap3_save_scratchpad_contents(); |
8bd22949 KH |
1083 | err1: |
1084 | return ret; | |
1085 | err2: | |
1086 | free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); | |
1087 | list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { | |
1088 | list_del(&pwrst->node); | |
1089 | kfree(pwrst); | |
1090 | } | |
1091 | return ret; | |
1092 | } | |
1093 | ||
1094 | late_initcall(omap3_pm_init); |