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OMAP3: PM: save secure RAM only during init
[mirror_ubuntu-artful-kernel.git] / arch / arm / mach-omap2 / pm34xx.c
CommitLineData
8bd22949
KH		 1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
2f5939c3
RN		 8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
8bd22949
KH		 11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/pm.h>
22#include <linux/suspend.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
28
ce491cf8
TL		 29#include <plat/sram.h>
30#include <plat/clockdomain.h>
31#include <plat/powerdomain.h>
32#include <plat/control.h>
33#include <plat/serial.h>
61255ab9 34#include <plat/sdrc.h>
2f5939c3
RN		 35#include <plat/prcm.h>
36#include <plat/gpmc.h>
f2d11858 37#include <plat/dma.h>
8bd22949 38
57f277b0
RN		 39#include <asm/tlbflush.h>
40
8bd22949
KH		 41#include "cm.h"
42#include "cm-regbits-34xx.h"
43#include "prm-regbits-34xx.h"
44
45#include "prm.h"
46#include "pm.h"
47
2f5939c3
RN		 48/* Scratchpad offsets */
49#define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
50#define OMAP343X_TABLE_VALUE_OFFSET 0x30
51#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
52
8bd22949
KH		 53struct power_state {
54 struct powerdomain *pwrdm;
55 u32 next_state;
10f90ed2 56#ifdef CONFIG_SUSPEND
8bd22949 57 u32 saved_state;
10f90ed2 58#endif
8bd22949
KH		 59 struct list_head node;
60};
61
62static LIST_HEAD(pwrst_list);
63
64static void (*_omap_sram_idle)(u32 *addr, int save_state);
65
27d59a4a
TK		 66static int (*_omap_save_secure_sram)(u32 *addr);
67
fa3c2a4f
RN		 68static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
69static struct powerdomain *core_pwrdm, *per_pwrdm;
70
71static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
8bd22949 72
2f5939c3
RN		 73static inline void omap3_per_save_context(void)
74{
75 omap_gpio_save_context();
76}
77
78static inline void omap3_per_restore_context(void)
79{
80 omap_gpio_restore_context();
81}
82
83static void omap3_core_save_context(void)
84{
85 u32 control_padconf_off;
86
87 /* Save the padconf registers */
88 control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
89 control_padconf_off |= START_PADCONF_SAVE;
90 omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
91 /* wait for the save to complete */
92 while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
93 & PADCONF_SAVE_DONE)
94 ;
95 /* Save the Interrupt controller context */
96 omap_intc_save_context();
97 /* Save the GPMC context */
98 omap3_gpmc_save_context();
99 /* Save the system control module context, padconf already save above*/
100 omap3_control_save_context();
f2d11858 101 omap_dma_global_context_save();
2f5939c3
RN		 102}
103
104static void omap3_core_restore_context(void)
105{
106 /* Restore the control module context, padconf restored by h/w */
107 omap3_control_restore_context();
108 /* Restore the GPMC context */
109 omap3_gpmc_restore_context();
110 /* Restore the interrupt controller context */
111 omap_intc_restore_context();
f2d11858 112 omap_dma_global_context_restore();
2f5939c3
RN		 113}
114
9d97140b
TK		 115/*
116 * FIXME: This function should be called before entering off-mode after
117 * OMAP3 secure services have been accessed. Currently it is only called
118 * once during boot sequence, but this works as we are not using secure
119 * services.
120 */
27d59a4a
TK		 121static void omap3_save_secure_ram_context(u32 target_mpu_state)
122{
123 u32 ret;
124
125 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
126 /* Disable dma irq before calling secure rom code API */
127 omap_dma_disable_irq(0);
128 omap_dma_disable_irq(1);
129 /*
130 * MPU next state must be set to POWER_ON temporarily,
131 * otherwise the WFI executed inside the ROM code
132 * will hang the system.
133 */
134 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
135 ret = _omap_save_secure_sram((u32 *)
136 __pa(omap3_secure_ram_storage));
137 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
138 /* Following is for error tracking, it should not happen */
139 if (ret) {
140 printk(KERN_ERR "save_secure_sram() returns %08x\n",
141 ret);
142 while (1)
143 ;
144 }
145 }
146}
147
77da2d91
JH		 148/*
149 * PRCM Interrupt Handler Helper Function
150 *
151 * The purpose of this function is to clear any wake-up events latched
152 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
153 * may occur whilst attempting to clear a PM_WKST_x register and thus
154 * set another bit in this register. A while loop is used to ensure
155 * that any peripheral wake-up events occurring while attempting to
156 * clear the PM_WKST_x are detected and cleared.
157 */
8cb0ac99 158static int prcm_clear_mod_irqs(s16 module, u8 regs)
8bd22949 159{
71a80775 160 u32 wkst, fclk, iclk, clken;
77da2d91
JH		 161 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
162 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
163 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
5d805978
PW		 164 u16 grpsel_off = (regs == 3) ?
165 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
8cb0ac99 166 int c = 0;
8bd22949 167
77da2d91 168 wkst = prm_read_mod_reg(module, wkst_off);
5d805978 169 wkst &= prm_read_mod_reg(module, grpsel_off);
8bd22949 170 if (wkst) {
77da2d91
JH		 171 iclk = cm_read_mod_reg(module, iclk_off);
172 fclk = cm_read_mod_reg(module, fclk_off);
173 while (wkst) {
71a80775
VP		 174 clken = wkst;
175 cm_set_mod_reg_bits(clken, module, iclk_off);
176 /*
177 * For USBHOST, we don't know whether HOST1 or
178 * HOST2 woke us up, so enable both f-clocks
179 */
180 if (module == OMAP3430ES2_USBHOST_MOD)
181 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
182 cm_set_mod_reg_bits(clken, module, fclk_off);
77da2d91
JH		 183 prm_write_mod_reg(wkst, module, wkst_off);
184 wkst = prm_read_mod_reg(module, wkst_off);
8cb0ac99 185 c++;
77da2d91
JH		 186 }
187 cm_write_mod_reg(iclk, module, iclk_off);
188 cm_write_mod_reg(fclk, module, fclk_off);
8bd22949 189 }
8cb0ac99
PW		 190
191 return c;
192}
193
194static int _prcm_int_handle_wakeup(void)
195{
196 int c;
197
198 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
199 c += prcm_clear_mod_irqs(CORE_MOD, 1);
200 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
201 if (omap_rev() > OMAP3430_REV_ES1_0) {
202 c += prcm_clear_mod_irqs(CORE_MOD, 3);
203 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
204 }
205
206 return c;
77da2d91 207}
8bd22949 208
77da2d91
JH		 209/*
210 * PRCM Interrupt Handler
211 *
212 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
213 * interrupts from the PRCM for the MPU. These bits must be cleared in
214 * order to clear the PRCM interrupt. The PRCM interrupt handler is
215 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
216 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
217 * register indicates that a wake-up event is pending for the MPU and
218 * this bit can only be cleared if the all the wake-up events latched
219 * in the various PM_WKST_x registers have been cleared. The interrupt
220 * handler is implemented using a do-while loop so that if a wake-up
221 * event occurred during the processing of the prcm interrupt handler
222 * (setting a bit in the corresponding PM_WKST_x register and thus
223 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
224 * this would be handled.
225 */
226static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
227{
228 u32 irqstatus_mpu;
8cb0ac99 229 int c = 0;
77da2d91
JH		 230
231 do {
77da2d91
JH		 232 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
233 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
8cb0ac99
PW		 234
235 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
236 c = _prcm_int_handle_wakeup();
237
238 /*
239 * Is the MPU PRCM interrupt handler racing with the
240 * IVA2 PRCM interrupt handler ?
241 */
242 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
243 "but no wakeup sources are marked\n");
244 } else {
245 /* XXX we need to expand our PRCM interrupt handler */
246 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
247 "no code to handle it (%08x)\n", irqstatus_mpu);
248 }
249
77da2d91
JH		 250 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
251 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
8bd22949 252
77da2d91 253 } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
8bd22949
KH		 254
255 return IRQ_HANDLED;
256}
257
57f277b0
RN		 258static void restore_control_register(u32 val)
259{
260 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
261}
262
263/* Function to restore the table entry that was modified for enabling MMU */
264static void restore_table_entry(void)
265{
266 u32 *scratchpad_address;
267 u32 previous_value, control_reg_value;
268 u32 *address;
269
270 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
271
272 /* Get address of entry that was modified */
273 address = (u32 *)__raw_readl(scratchpad_address +
274 OMAP343X_TABLE_ADDRESS_OFFSET);
275 /* Get the previous value which needs to be restored */
276 previous_value = __raw_readl(scratchpad_address +
277 OMAP343X_TABLE_VALUE_OFFSET);
278 address = __va(address);
279 *address = previous_value;
280 flush_tlb_all();
281 control_reg_value = __raw_readl(scratchpad_address
282 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
283 /* This will enable caches and prediction */
284 restore_control_register(control_reg_value);
285}
286
8bd22949
KH		 287static void omap_sram_idle(void)
288{
289 /* Variable to tell what needs to be saved and restored
290 * in omap_sram_idle*/
291 /* save_state = 0 => Nothing to save and restored */
292 /* save_state = 1 => Only L1 and logic lost */
293 /* save_state = 2 => Only L2 lost */
294 /* save_state = 3 => L1, L2 and logic lost */
fa3c2a4f
RN		 295 int save_state = 0;
296 int mpu_next_state = PWRDM_POWER_ON;
297 int per_next_state = PWRDM_POWER_ON;
298 int core_next_state = PWRDM_POWER_ON;
2f5939c3 299 int core_prev_state, per_prev_state;
8bd22949
KH		 300
301 if (!_omap_sram_idle)
302 return;
303
fa3c2a4f
RN		 304 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
305 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
306 pwrdm_clear_all_prev_pwrst(core_pwrdm);
307 pwrdm_clear_all_prev_pwrst(per_pwrdm);
308
8bd22949
KH		 309 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
310 switch (mpu_next_state) {
fa3c2a4f 311 case PWRDM_POWER_ON:
8bd22949
KH		 312 case PWRDM_POWER_RET:
313 /* No need to save context */
314 save_state = 0;
315 break;
61255ab9
RN		 316 case PWRDM_POWER_OFF:
317 save_state = 3;
318 break;
8bd22949
KH		 319 default:
320 /* Invalid state */
321 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
322 return;
323 }
fe617af7
PDS		 324 pwrdm_pre_transition();
325
fa3c2a4f
RN		 326 /* NEON control */
327 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
328 set_pwrdm_state(neon_pwrdm, mpu_next_state);
329
330 /* CORE & PER */
331 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
332 if (core_next_state < PWRDM_POWER_ON) {
333 omap2_gpio_prepare_for_retention();
334 omap_uart_prepare_idle(0);
335 omap_uart_prepare_idle(1);
336 /* PER changes only with core */
337 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
2f5939c3 338 if (per_next_state < PWRDM_POWER_ON) {
fa3c2a4f 339 omap_uart_prepare_idle(2);
2f5939c3
RN		 340 if (per_next_state == PWRDM_POWER_OFF)
341 omap3_per_save_context();
342 }
343 if (core_next_state == PWRDM_POWER_OFF) {
344 omap3_core_save_context();
345 omap3_prcm_save_context();
346 }
fa3c2a4f
RN		 347 /* Enable IO-PAD wakeup */
348 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
349 }
8bd22949 350
61255ab9
RN		 351 /*
352 * omap3_arm_context is the location where ARM registers
353 * get saved. The restore path then reads from this
354 * location and restores them back.
355 */
356 _omap_sram_idle(omap3_arm_context, save_state);
8bd22949
KH		 357 cpu_init();
358
57f277b0
RN		 359 /* Restore table entry modified during MMU restoration */
360 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
361 restore_table_entry();
362
fa3c2a4f
RN		 363 if (core_next_state < PWRDM_POWER_ON) {
364 if (per_next_state < PWRDM_POWER_ON)
365 omap_uart_resume_idle(2);
366 omap_uart_resume_idle(1);
367 omap_uart_resume_idle(0);
368
369 /* Disable IO-PAD wakeup */
370 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
2f5939c3
RN		 371 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
372 if (core_prev_state == PWRDM_POWER_OFF) {
373 omap3_core_restore_context();
374 omap3_prcm_restore_context();
375 omap3_sram_restore_context();
376 }
377 if (per_next_state < PWRDM_POWER_ON) {
378 per_prev_state =
379 pwrdm_read_prev_pwrst(per_pwrdm);
380 if (per_prev_state == PWRDM_POWER_OFF)
381 omap3_per_restore_context();
382 }
fa3c2a4f
RN		 383 omap2_gpio_resume_after_retention();
384 }
fe617af7
PDS		 385
386 pwrdm_post_transition();
387
8bd22949
KH		 388}
389
390/*
391 * Check if functional clocks are enabled before entering
392 * sleep. This function could be behind CONFIG_PM_DEBUG
393 * when all drivers are configuring their sysconfig registers
394 * properly and using their clocks properly.
395 */
396static int omap3_fclks_active(void)
397{
398 u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
399 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
400
401 fck_core1 = cm_read_mod_reg(CORE_MOD,
402 CM_FCLKEN1);
403 if (omap_rev() > OMAP3430_REV_ES1_0) {
404 fck_core3 = cm_read_mod_reg(CORE_MOD,
405 OMAP3430ES2_CM_FCLKEN3);
406 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
407 CM_FCLKEN);
408 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
409 CM_FCLKEN);
410 } else
411 fck_sgx = cm_read_mod_reg(GFX_MOD,
412 OMAP3430ES2_CM_FCLKEN3);
413 fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
414 CM_FCLKEN);
415 fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
416 CM_FCLKEN);
417 fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
418 CM_FCLKEN);
4af4016c
KH		 419
420 /* Ignore UART clocks. These are handled by UART core (serial.c) */
421 fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
422 fck_per &= ~OMAP3430_EN_UART3;
423
8bd22949
KH		 424 if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
425 fck_cam | fck_per | fck_usbhost)
426 return 1;
427 return 0;
428}
429
430static int omap3_can_sleep(void)
431{
4af4016c
KH		 432 if (!omap_uart_can_sleep())
433 return 0;
8bd22949
KH		 434 if (omap3_fclks_active())
435 return 0;
436 return 1;
437}
438
439/* This sets pwrdm state (other than mpu & core. Currently only ON &
440 * RET are supported. Function is assuming that clkdm doesn't have
441 * hw_sup mode enabled. */
442static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
443{
444 u32 cur_state;
445 int sleep_switch = 0;
446 int ret = 0;
447
448 if (pwrdm == NULL || IS_ERR(pwrdm))
449 return -EINVAL;
450
451 while (!(pwrdm->pwrsts & (1 << state))) {
452 if (state == PWRDM_POWER_OFF)
453 return ret;
454 state--;
455 }
456
457 cur_state = pwrdm_read_next_pwrst(pwrdm);
458 if (cur_state == state)
459 return ret;
460
461 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
462 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
463 sleep_switch = 1;
464 pwrdm_wait_transition(pwrdm);
465 }
466
467 ret = pwrdm_set_next_pwrst(pwrdm, state);
468 if (ret) {
469 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
470 pwrdm->name);
471 goto err;
472 }
473
474 if (sleep_switch) {
475 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
476 pwrdm_wait_transition(pwrdm);
fe617af7 477 pwrdm_state_switch(pwrdm);
8bd22949
KH		 478 }
479
480err:
481 return ret;
482}
483
484static void omap3_pm_idle(void)
485{
486 local_irq_disable();
487 local_fiq_disable();
488
489 if (!omap3_can_sleep())
490 goto out;
491
492 if (omap_irq_pending())
493 goto out;
494
495 omap_sram_idle();
496
497out:
498 local_fiq_enable();
499 local_irq_enable();
500}
501
10f90ed2 502#ifdef CONFIG_SUSPEND
2466211e
TK		 503static suspend_state_t suspend_state;
504
8bd22949
KH		 505static int omap3_pm_prepare(void)
506{
507 disable_hlt();
508 return 0;
509}
510
511static int omap3_pm_suspend(void)
512{
513 struct power_state *pwrst;
514 int state, ret = 0;
515
516 /* Read current next_pwrsts */
517 list_for_each_entry(pwrst, &pwrst_list, node)
518 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
519 /* Set ones wanted by suspend */
520 list_for_each_entry(pwrst, &pwrst_list, node) {
521 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
522 goto restore;
523 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
524 goto restore;
525 }
526
4af4016c 527 omap_uart_prepare_suspend();
8bd22949
KH		 528 omap_sram_idle();
529
530restore:
531 /* Restore next_pwrsts */
532 list_for_each_entry(pwrst, &pwrst_list, node) {
8bd22949
KH		 533 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
534 if (state > pwrst->next_state) {
535 printk(KERN_INFO "Powerdomain (%s) didn't enter "
536 "target state %d\n",
537 pwrst->pwrdm->name, pwrst->next_state);
538 ret = -1;
539 }
6c5f8039 540 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
8bd22949
KH		 541 }
542 if (ret)
543 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
544 else
545 printk(KERN_INFO "Successfully put all powerdomains "
546 "to target state\n");
547
548 return ret;
549}
550
2466211e 551static int omap3_pm_enter(suspend_state_t unused)
8bd22949
KH		 552{
553 int ret = 0;
554
2466211e 555 switch (suspend_state) {
8bd22949
KH		 556 case PM_SUSPEND_STANDBY:
557 case PM_SUSPEND_MEM:
558 ret = omap3_pm_suspend();
559 break;
560 default:
561 ret = -EINVAL;
562 }
563
564 return ret;
565}
566
567static void omap3_pm_finish(void)
568{
569 enable_hlt();
570}
571
2466211e
TK		 572/* Hooks to enable / disable UART interrupts during suspend */
573static int omap3_pm_begin(suspend_state_t state)
574{
575 suspend_state = state;
576 omap_uart_enable_irqs(0);
577 return 0;
578}
579
580static void omap3_pm_end(void)
581{
582 suspend_state = PM_SUSPEND_ON;
583 omap_uart_enable_irqs(1);
584 return;
585}
586
8bd22949 587static struct platform_suspend_ops omap_pm_ops = {
2466211e
TK		 588 .begin = omap3_pm_begin,
589 .end = omap3_pm_end,
8bd22949
KH		 590 .prepare = omap3_pm_prepare,
591 .enter = omap3_pm_enter,
592 .finish = omap3_pm_finish,
593 .valid = suspend_valid_only_mem,
594};
10f90ed2 595#endif /* CONFIG_SUSPEND */
8bd22949 596
1155e426
KH		 597
598/**
599 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
600 * retention
601 *
602 * In cases where IVA2 is activated by bootcode, it may prevent
603 * full-chip retention or off-mode because it is not idle. This
604 * function forces the IVA2 into idle state so it can go
605 * into retention/off and thus allow full-chip retention/off.
606 *
607 **/
608static void __init omap3_iva_idle(void)
609{
610 /* ensure IVA2 clock is disabled */
611 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
612
613 /* if no clock activity, nothing else to do */
614 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
615 OMAP3430_CLKACTIVITY_IVA2_MASK))
616 return;
617
618 /* Reset IVA2 */
619 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
620 OMAP3430_RST2_IVA2 |
621 OMAP3430_RST3_IVA2,
622 OMAP3430_IVA2_MOD, RM_RSTCTRL);
623
624 /* Enable IVA2 clock */
625 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
626 OMAP3430_IVA2_MOD, CM_FCLKEN);
627
628 /* Set IVA2 boot mode to 'idle' */
629 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
630 OMAP343X_CONTROL_IVA2_BOOTMOD);
631
632 /* Un-reset IVA2 */
633 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
634
635 /* Disable IVA2 clock */
636 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
637
638 /* Reset IVA2 */
639 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
640 OMAP3430_RST2_IVA2 |
641 OMAP3430_RST3_IVA2,
642 OMAP3430_IVA2_MOD, RM_RSTCTRL);
643}
644
8111b221 645static void __init omap3_d2d_idle(void)
8bd22949 646{
8111b221
KH		 647 u16 mask, padconf;
648
649 /* In a stand alone OMAP3430 where there is not a stacked
650 * modem for the D2D Idle Ack and D2D MStandby must be pulled
651 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
652 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
653 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
654 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
655 padconf |= mask;
656 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
657
658 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
659 padconf |= mask;
660 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
661
8bd22949
KH		 662 /* reset modem */
663 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
664 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
665 CORE_MOD, RM_RSTCTRL);
666 prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
8111b221 667}
8bd22949 668
8111b221
KH		 669static void __init prcm_setup_regs(void)
670{
8bd22949
KH		 671 /* XXX Reset all wkdeps. This should be done when initializing
672 * powerdomains */
673 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
674 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
675 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
676 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
677 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
678 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
679 if (omap_rev() > OMAP3430_REV_ES1_0) {
680 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
681 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
682 } else
683 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
684
685 /*
686 * Enable interface clock autoidle for all modules.
687 * Note that in the long run this should be done by clockfw
688 */
689 cm_write_mod_reg(
8111b221 690 OMAP3430_AUTO_MODEM |
8bd22949
KH		 691 OMAP3430ES2_AUTO_MMC3 |
692 OMAP3430ES2_AUTO_ICR |
693 OMAP3430_AUTO_AES2 |
694 OMAP3430_AUTO_SHA12 |
695 OMAP3430_AUTO_DES2 |
696 OMAP3430_AUTO_MMC2 |
697 OMAP3430_AUTO_MMC1 |
698 OMAP3430_AUTO_MSPRO |
699 OMAP3430_AUTO_HDQ |
700 OMAP3430_AUTO_MCSPI4 |
701 OMAP3430_AUTO_MCSPI3 |
702 OMAP3430_AUTO_MCSPI2 |
703 OMAP3430_AUTO_MCSPI1 |
704 OMAP3430_AUTO_I2C3 |
705 OMAP3430_AUTO_I2C2 |
706 OMAP3430_AUTO_I2C1 |
707 OMAP3430_AUTO_UART2 |
708 OMAP3430_AUTO_UART1 |
709 OMAP3430_AUTO_GPT11 |
710 OMAP3430_AUTO_GPT10 |
711 OMAP3430_AUTO_MCBSP5 |
712 OMAP3430_AUTO_MCBSP1 |
713 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
714 OMAP3430_AUTO_MAILBOXES |
715 OMAP3430_AUTO_OMAPCTRL |
716 OMAP3430ES1_AUTO_FSHOSTUSB |
717 OMAP3430_AUTO_HSOTGUSB |
8111b221 718 OMAP3430_AUTO_SAD2D |
8bd22949
KH		 719 OMAP3430_AUTO_SSI,
720 CORE_MOD, CM_AUTOIDLE1);
721
722 cm_write_mod_reg(
723 OMAP3430_AUTO_PKA |
724 OMAP3430_AUTO_AES1 |
725 OMAP3430_AUTO_RNG |
726 OMAP3430_AUTO_SHA11 |
727 OMAP3430_AUTO_DES1,
728 CORE_MOD, CM_AUTOIDLE2);
729
730 if (omap_rev() > OMAP3430_REV_ES1_0) {
731 cm_write_mod_reg(
8111b221 732 OMAP3430_AUTO_MAD2D |
8bd22949
KH		 733 OMAP3430ES2_AUTO_USBTLL,
734 CORE_MOD, CM_AUTOIDLE3);
735 }
736
737 cm_write_mod_reg(
738 OMAP3430_AUTO_WDT2 |
739 OMAP3430_AUTO_WDT1 |
740 OMAP3430_AUTO_GPIO1 |
741 OMAP3430_AUTO_32KSYNC |
742 OMAP3430_AUTO_GPT12 |
743 OMAP3430_AUTO_GPT1 ,
744 WKUP_MOD, CM_AUTOIDLE);
745
746 cm_write_mod_reg(
747 OMAP3430_AUTO_DSS,
748 OMAP3430_DSS_MOD,
749 CM_AUTOIDLE);
750
751 cm_write_mod_reg(
752 OMAP3430_AUTO_CAM,
753 OMAP3430_CAM_MOD,
754 CM_AUTOIDLE);
755
756 cm_write_mod_reg(
757 OMAP3430_AUTO_GPIO6 |
758 OMAP3430_AUTO_GPIO5 |
759 OMAP3430_AUTO_GPIO4 |
760 OMAP3430_AUTO_GPIO3 |
761 OMAP3430_AUTO_GPIO2 |
762 OMAP3430_AUTO_WDT3 |
763 OMAP3430_AUTO_UART3 |
764 OMAP3430_AUTO_GPT9 |
765 OMAP3430_AUTO_GPT8 |
766 OMAP3430_AUTO_GPT7 |
767 OMAP3430_AUTO_GPT6 |
768 OMAP3430_AUTO_GPT5 |
769 OMAP3430_AUTO_GPT4 |
770 OMAP3430_AUTO_GPT3 |
771 OMAP3430_AUTO_GPT2 |
772 OMAP3430_AUTO_MCBSP4 |
773 OMAP3430_AUTO_MCBSP3 |
774 OMAP3430_AUTO_MCBSP2,
775 OMAP3430_PER_MOD,
776 CM_AUTOIDLE);
777
778 if (omap_rev() > OMAP3430_REV_ES1_0) {
779 cm_write_mod_reg(
780 OMAP3430ES2_AUTO_USBHOST,
781 OMAP3430ES2_USBHOST_MOD,
782 CM_AUTOIDLE);
783 }
784
785 /*
786 * Set all plls to autoidle. This is needed until autoidle is
787 * enabled by clockfw
788 */
789 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
790 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
791 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
792 MPU_MOD,
793 CM_AUTOIDLE2);
794 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
795 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
796 PLL_MOD,
797 CM_AUTOIDLE);
798 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
799 PLL_MOD,
800 CM_AUTOIDLE2);
801
802 /*
803 * Enable control of expternal oscillator through
804 * sys_clkreq. In the long run clock framework should
805 * take care of this.
806 */
807 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
808 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
809 OMAP3430_GR_MOD,
810 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
811
812 /* setup wakup source */
813 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
814 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
815 WKUP_MOD, PM_WKEN);
816 /* No need to write EN_IO, that is always enabled */
817 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
818 OMAP3430_EN_GPT12,
819 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
820 /* For some reason IO doesn't generate wakeup event even if
821 * it is selected to mpu wakeup goup */
822 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
823 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
1155e426 824
b427f92f 825 /* Enable wakeups in PER */
eb350f74
KH		 826 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
827 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
b427f92f
KH		 828 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
829 OMAP3430_PER_MOD, PM_WKEN);
eb350f74
KH		 830 /* and allow them to wake up MPU */
831 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
832 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
b427f92f 833 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
eb350f74
KH		 834 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
835
d3fd3290
KH		 836 /* Don't attach IVA interrupts */
837 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
838 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
839 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
840 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
841
b1340d17
KH		 842 /* Clear any pending 'reset' flags */
843 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
844 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
845 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
846 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
847 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
848 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
849 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
850
014c46db
KH		 851 /* Clear any pending PRCM interrupts */
852 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
853
040fed05
KH		 854 /* Don't attach IVA interrupts */
855 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
856 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
857 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
858 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
859
3a07ae30
KH		 860 /* Clear any pending 'reset' flags */
861 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
862 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
863 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
864 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
865 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
866 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
867 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
868
3a6667ac
KH		 869 /* Clear any pending PRCM interrupts */
870 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
871
1155e426 872 omap3_iva_idle();
8111b221 873 omap3_d2d_idle();
8bd22949
KH		 874}
875
68d4778c
TK		 876int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
877{
878 struct power_state *pwrst;
879
880 list_for_each_entry(pwrst, &pwrst_list, node) {
881 if (pwrst->pwrdm == pwrdm)
882 return pwrst->next_state;
883 }
884 return -EINVAL;
885}
886
887int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
888{
889 struct power_state *pwrst;
890
891 list_for_each_entry(pwrst, &pwrst_list, node) {
892 if (pwrst->pwrdm == pwrdm) {
893 pwrst->next_state = state;
894 return 0;
895 }
896 }
897 return -EINVAL;
898}
899
a23456e9 900static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
8bd22949
KH		 901{
902 struct power_state *pwrst;
903
904 if (!pwrdm->pwrsts)
905 return 0;
906
d3d381c6 907 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
8bd22949
KH		 908 if (!pwrst)
909 return -ENOMEM;
910 pwrst->pwrdm = pwrdm;
911 pwrst->next_state = PWRDM_POWER_RET;
912 list_add(&pwrst->node, &pwrst_list);
913
914 if (pwrdm_has_hdwr_sar(pwrdm))
915 pwrdm_enable_hdwr_sar(pwrdm);
916
917 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
918}
919
920/*
921 * Enable hw supervised mode for all clockdomains if it's
922 * supported. Initiate sleep transition for other clockdomains, if
923 * they are not used
924 */
a23456e9 925static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
8bd22949
KH		 926{
927 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
928 omap2_clkdm_allow_idle(clkdm);
929 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
930 atomic_read(&clkdm->usecount) == 0)
931 omap2_clkdm_sleep(clkdm);
932 return 0;
933}
934
3231fc88
RN		 935void omap_push_sram_idle(void)
936{
937 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
938 omap34xx_cpu_suspend_sz);
27d59a4a
TK		 939 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
940 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
941 save_secure_ram_context_sz);
3231fc88
RN		 942}
943
7cc515f7 944static int __init omap3_pm_init(void)
8bd22949
KH		 945{
946 struct power_state *pwrst, *tmp;
947 int ret;
948
949 if (!cpu_is_omap34xx())
950 return -ENODEV;
951
952 printk(KERN_ERR "Power Management for TI OMAP3.\n");
953
954 /* XXX prcm_setup_regs needs to be before enabling hw
955 * supervised mode for powerdomains */
956 prcm_setup_regs();
957
958 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
959 (irq_handler_t)prcm_interrupt_handler,
960 IRQF_DISABLED, "prcm", NULL);
961 if (ret) {
962 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
963 INT_34XX_PRCM_MPU_IRQ);
964 goto err1;
965 }
966
a23456e9 967 ret = pwrdm_for_each(pwrdms_setup, NULL);
8bd22949
KH		 968 if (ret) {
969 printk(KERN_ERR "Failed to setup powerdomains\n");
970 goto err2;
971 }
972
a23456e9 973 (void) clkdm_for_each(clkdms_setup, NULL);
8bd22949
KH		 974
975 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
976 if (mpu_pwrdm == NULL) {
977 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
978 goto err2;
979 }
980
fa3c2a4f
RN		 981 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
982 per_pwrdm = pwrdm_lookup("per_pwrdm");
983 core_pwrdm = pwrdm_lookup("core_pwrdm");
984
3231fc88 985 omap_push_sram_idle();
10f90ed2 986#ifdef CONFIG_SUSPEND
8bd22949 987 suspend_set_ops(&omap_pm_ops);
10f90ed2 988#endif /* CONFIG_SUSPEND */
8bd22949
KH		 989
990 pm_idle = omap3_pm_idle;
991
fa3c2a4f
RN		 992 pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
993 /*
994 * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
995 * IO-pad wakeup. Otherwise it will unnecessarily waste power
996 * waking up PER with every CORE wakeup - see
997 * http://marc.info/?l=linux-omap&m=121852150710062&w=2
998 */
999 pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
1000
27d59a4a
TK		 1001 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1002 omap3_secure_ram_storage =
1003 kmalloc(0x803F, GFP_KERNEL);
1004 if (!omap3_secure_ram_storage)
1005 printk(KERN_ERR "Memory allocation failed when"
1006 "allocating for secure sram context\n");
9d97140b
TK		 1007
1008 local_irq_disable();
1009 local_fiq_disable();
1010
1011 omap_dma_global_context_save();
1012 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1013 omap_dma_global_context_restore();
1014
1015 local_irq_enable();
1016 local_fiq_enable();
27d59a4a 1017 }
27d59a4a 1018
9d97140b 1019 omap3_save_scratchpad_contents();
8bd22949
KH		 1020err1:
1021 return ret;
1022err2:
1023 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1024 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1025 list_del(&pwrst->node);
1026 kfree(pwrst);
1027 }
1028 return ret;
1029}
1030
1031late_initcall(omap3_pm_init);
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