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0a84a91c TK |
1 | /* |
2 | * OMAP2+ common Power & Reset Management (PRM) IP block functions | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments, Inc. | |
5 | * Tero Kristo <t-kristo@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * | |
12 | * For historical purposes, the API used to configure the PRM | |
13 | * interrupt handler refers to it as the "PRCM interrupt." The | |
14 | * underlying registers are located in the PRM on OMAP3/4. | |
15 | * | |
16 | * XXX This code should eventually be moved to a PRM driver. | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/slab.h> | |
26 | ||
0a84a91c TK |
27 | #include <plat/common.h> |
28 | #include <plat/prcm.h> | |
29 | #include <plat/irqs.h> | |
30 | ||
31 | #include "prm2xxx_3xxx.h" | |
32 | #include "prm44xx.h" | |
33 | ||
34 | /* | |
35 | * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs | |
36 | * XXX this is technically not needed, since | |
37 | * omap_prcm_register_chain_handler() could allocate this based on the | |
38 | * actual amount of memory needed for the SoC | |
39 | */ | |
40 | #define OMAP_PRCM_MAX_NR_PENDING_REG 2 | |
41 | ||
42 | /* | |
43 | * prcm_irq_chips: an array of all of the "generic IRQ chips" in use | |
44 | * by the PRCM interrupt handler code. There will be one 'chip' per | |
45 | * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have | |
46 | * one "chip" and OMAP4 will have two.) | |
47 | */ | |
48 | static struct irq_chip_generic **prcm_irq_chips; | |
49 | ||
50 | /* | |
51 | * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code | |
52 | * is currently running on. Defined and passed by initialization code | |
53 | * that calls omap_prcm_register_chain_handler(). | |
54 | */ | |
55 | static struct omap_prcm_irq_setup *prcm_irq_setup; | |
56 | ||
57 | /* Private functions */ | |
58 | ||
59 | /* | |
60 | * Move priority events from events to priority_events array | |
61 | */ | |
62 | static void omap_prcm_events_filter_priority(unsigned long *events, | |
63 | unsigned long *priority_events) | |
64 | { | |
65 | int i; | |
66 | ||
67 | for (i = 0; i < prcm_irq_setup->nr_regs; i++) { | |
68 | priority_events[i] = | |
69 | events[i] & prcm_irq_setup->priority_mask[i]; | |
70 | events[i] ^= priority_events[i]; | |
71 | } | |
72 | } | |
73 | ||
74 | /* | |
75 | * PRCM Interrupt Handler | |
76 | * | |
77 | * This is a common handler for the OMAP PRCM interrupts. Pending | |
78 | * interrupts are detected by a call to prcm_pending_events and | |
79 | * dispatched accordingly. Clearing of the wakeup events should be | |
80 | * done by the SoC specific individual handlers. | |
81 | */ | |
82 | static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc) | |
83 | { | |
84 | unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG]; | |
85 | unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG]; | |
86 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
87 | unsigned int virtirq; | |
88 | int nr_irqs = prcm_irq_setup->nr_regs * 32; | |
89 | ||
91285b6f TK |
90 | /* |
91 | * If we are suspended, mask all interrupts from PRCM level, | |
92 | * this does not ack them, and they will be pending until we | |
93 | * re-enable the interrupts, at which point the | |
94 | * omap_prcm_irq_handler will be executed again. The | |
95 | * _save_and_clear_irqen() function must ensure that the PRM | |
96 | * write to disable all IRQs has reached the PRM before | |
97 | * returning, or spurious PRCM interrupts may occur during | |
98 | * suspend. | |
99 | */ | |
100 | if (prcm_irq_setup->suspended) { | |
101 | prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask); | |
102 | prcm_irq_setup->suspend_save_flag = true; | |
103 | } | |
104 | ||
0a84a91c TK |
105 | /* |
106 | * Loop until all pending irqs are handled, since | |
107 | * generic_handle_irq() can cause new irqs to come | |
108 | */ | |
91285b6f | 109 | while (!prcm_irq_setup->suspended) { |
0a84a91c TK |
110 | prcm_irq_setup->read_pending_irqs(pending); |
111 | ||
112 | /* No bit set, then all IRQs are handled */ | |
113 | if (find_first_bit(pending, nr_irqs) >= nr_irqs) | |
114 | break; | |
115 | ||
116 | omap_prcm_events_filter_priority(pending, priority_pending); | |
117 | ||
118 | /* | |
119 | * Loop on all currently pending irqs so that new irqs | |
120 | * cannot starve previously pending irqs | |
121 | */ | |
122 | ||
123 | /* Serve priority events first */ | |
124 | for_each_set_bit(virtirq, priority_pending, nr_irqs) | |
125 | generic_handle_irq(prcm_irq_setup->base_irq + virtirq); | |
126 | ||
127 | /* Serve normal events next */ | |
128 | for_each_set_bit(virtirq, pending, nr_irqs) | |
129 | generic_handle_irq(prcm_irq_setup->base_irq + virtirq); | |
130 | } | |
131 | if (chip->irq_ack) | |
132 | chip->irq_ack(&desc->irq_data); | |
133 | if (chip->irq_eoi) | |
134 | chip->irq_eoi(&desc->irq_data); | |
135 | chip->irq_unmask(&desc->irq_data); | |
136 | ||
137 | prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */ | |
138 | } | |
139 | ||
140 | /* Public functions */ | |
141 | ||
142 | /** | |
143 | * omap_prcm_event_to_irq - given a PRCM event name, returns the | |
144 | * corresponding IRQ on which the handler should be registered | |
145 | * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq | |
146 | * | |
147 | * Returns the Linux internal IRQ ID corresponding to @name upon success, | |
148 | * or -ENOENT upon failure. | |
149 | */ | |
150 | int omap_prcm_event_to_irq(const char *name) | |
151 | { | |
152 | int i; | |
153 | ||
154 | if (!prcm_irq_setup || !name) | |
155 | return -ENOENT; | |
156 | ||
157 | for (i = 0; i < prcm_irq_setup->nr_irqs; i++) | |
158 | if (!strcmp(prcm_irq_setup->irqs[i].name, name)) | |
159 | return prcm_irq_setup->base_irq + | |
160 | prcm_irq_setup->irqs[i].offset; | |
161 | ||
162 | return -ENOENT; | |
163 | } | |
164 | ||
165 | /** | |
166 | * omap_prcm_irq_cleanup - reverses memory allocated and other steps | |
167 | * done by omap_prcm_register_chain_handler() | |
168 | * | |
169 | * No return value. | |
170 | */ | |
171 | void omap_prcm_irq_cleanup(void) | |
172 | { | |
173 | int i; | |
174 | ||
175 | if (!prcm_irq_setup) { | |
176 | pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n"); | |
177 | return; | |
178 | } | |
179 | ||
180 | if (prcm_irq_chips) { | |
181 | for (i = 0; i < prcm_irq_setup->nr_regs; i++) { | |
182 | if (prcm_irq_chips[i]) | |
183 | irq_remove_generic_chip(prcm_irq_chips[i], | |
184 | 0xffffffff, 0, 0); | |
185 | prcm_irq_chips[i] = NULL; | |
186 | } | |
187 | kfree(prcm_irq_chips); | |
188 | prcm_irq_chips = NULL; | |
189 | } | |
190 | ||
91285b6f TK |
191 | kfree(prcm_irq_setup->saved_mask); |
192 | prcm_irq_setup->saved_mask = NULL; | |
193 | ||
0a84a91c TK |
194 | kfree(prcm_irq_setup->priority_mask); |
195 | prcm_irq_setup->priority_mask = NULL; | |
196 | ||
197 | irq_set_chained_handler(prcm_irq_setup->irq, NULL); | |
198 | ||
199 | if (prcm_irq_setup->base_irq > 0) | |
200 | irq_free_descs(prcm_irq_setup->base_irq, | |
201 | prcm_irq_setup->nr_regs * 32); | |
202 | prcm_irq_setup->base_irq = 0; | |
203 | } | |
204 | ||
91285b6f TK |
205 | void omap_prcm_irq_prepare(void) |
206 | { | |
207 | prcm_irq_setup->suspended = true; | |
208 | } | |
209 | ||
210 | void omap_prcm_irq_complete(void) | |
211 | { | |
212 | prcm_irq_setup->suspended = false; | |
213 | ||
214 | /* If we have not saved the masks, do not attempt to restore */ | |
215 | if (!prcm_irq_setup->suspend_save_flag) | |
216 | return; | |
217 | ||
218 | prcm_irq_setup->suspend_save_flag = false; | |
219 | ||
220 | /* | |
221 | * Re-enable all masked PRCM irq sources, this causes the PRCM | |
222 | * interrupt to fire immediately if the events were masked | |
223 | * previously in the chain handler | |
224 | */ | |
225 | prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask); | |
226 | } | |
227 | ||
0a84a91c TK |
228 | /** |
229 | * omap_prcm_register_chain_handler - initializes the prcm chained interrupt | |
230 | * handler based on provided parameters | |
231 | * @irq_setup: hardware data about the underlying PRM/PRCM | |
232 | * | |
233 | * Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up | |
234 | * one generic IRQ chip per PRM interrupt status/enable register pair. | |
235 | * Returns 0 upon success, -EINVAL if called twice or if invalid | |
236 | * arguments are passed, or -ENOMEM on any other error. | |
237 | */ | |
238 | int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup) | |
239 | { | |
eeb3711b | 240 | int nr_regs; |
0a84a91c TK |
241 | u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG]; |
242 | int offset, i; | |
243 | struct irq_chip_generic *gc; | |
244 | struct irq_chip_type *ct; | |
245 | ||
246 | if (!irq_setup) | |
247 | return -EINVAL; | |
248 | ||
eeb3711b PW |
249 | nr_regs = irq_setup->nr_regs; |
250 | ||
0a84a91c TK |
251 | if (prcm_irq_setup) { |
252 | pr_err("PRCM: already initialized; won't reinitialize\n"); | |
253 | return -EINVAL; | |
254 | } | |
255 | ||
256 | if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) { | |
257 | pr_err("PRCM: nr_regs too large\n"); | |
258 | return -EINVAL; | |
259 | } | |
260 | ||
261 | prcm_irq_setup = irq_setup; | |
262 | ||
263 | prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL); | |
91285b6f | 264 | prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL); |
0a84a91c TK |
265 | prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs, |
266 | GFP_KERNEL); | |
267 | ||
91285b6f TK |
268 | if (!prcm_irq_chips || !prcm_irq_setup->saved_mask || |
269 | !prcm_irq_setup->priority_mask) { | |
0a84a91c TK |
270 | pr_err("PRCM: kzalloc failed\n"); |
271 | goto err; | |
272 | } | |
273 | ||
274 | memset(mask, 0, sizeof(mask)); | |
275 | ||
276 | for (i = 0; i < irq_setup->nr_irqs; i++) { | |
277 | offset = irq_setup->irqs[i].offset; | |
278 | mask[offset >> 5] |= 1 << (offset & 0x1f); | |
279 | if (irq_setup->irqs[i].priority) | |
280 | irq_setup->priority_mask[offset >> 5] |= | |
281 | 1 << (offset & 0x1f); | |
282 | } | |
283 | ||
284 | irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler); | |
285 | ||
286 | irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32, | |
287 | 0); | |
288 | ||
289 | if (irq_setup->base_irq < 0) { | |
290 | pr_err("PRCM: failed to allocate irq descs: %d\n", | |
291 | irq_setup->base_irq); | |
292 | goto err; | |
293 | } | |
294 | ||
4ba7c3c3 | 295 | for (i = 0; i < irq_setup->nr_regs; i++) { |
0a84a91c TK |
296 | gc = irq_alloc_generic_chip("PRCM", 1, |
297 | irq_setup->base_irq + i * 32, prm_base, | |
298 | handle_level_irq); | |
299 | ||
300 | if (!gc) { | |
301 | pr_err("PRCM: failed to allocate generic chip\n"); | |
302 | goto err; | |
303 | } | |
304 | ct = gc->chip_types; | |
305 | ct->chip.irq_ack = irq_gc_ack_set_bit; | |
306 | ct->chip.irq_mask = irq_gc_mask_clr_bit; | |
307 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
308 | ||
309 | ct->regs.ack = irq_setup->ack + i * 4; | |
310 | ct->regs.mask = irq_setup->mask + i * 4; | |
311 | ||
312 | irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0); | |
313 | prcm_irq_chips[i] = gc; | |
314 | } | |
315 | ||
316 | return 0; | |
317 | ||
318 | err: | |
319 | omap_prcm_irq_cleanup(); | |
320 | return -ENOMEM; | |
321 | } | |
3f4990f4 S |
322 | |
323 | /* | |
324 | * Stubbed functions so that common files continue to build when | |
325 | * custom builds are used | |
326 | * XXX These are temporary and should be removed at the earliest possible | |
327 | * opportunity | |
328 | */ | |
329 | u32 __weak omap2_prm_read_mod_reg(s16 module, u16 idx) | |
330 | { | |
331 | WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); | |
332 | return 0; | |
333 | } | |
334 | ||
335 | void __weak omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) | |
336 | { | |
337 | WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); | |
338 | } | |
339 | ||
340 | u32 __weak omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, | |
341 | s16 module, s16 idx) | |
342 | { | |
343 | WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); | |
344 | return 0; | |
345 | } | |
346 | ||
347 | u32 __weak omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) | |
348 | { | |
349 | WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); | |
350 | return 0; | |
351 | } | |
352 | ||
353 | u32 __weak omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) | |
354 | { | |
355 | WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); | |
356 | return 0; | |
357 | } | |
358 | ||
359 | u32 __weak omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) | |
360 | { | |
361 | WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); | |
362 | return 0; | |
363 | } | |
364 | ||
365 | int __weak omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) | |
366 | { | |
367 | WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); | |
368 | return 0; | |
369 | } | |
370 | ||
371 | int __weak omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) | |
372 | { | |
373 | WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); | |
374 | return 0; | |
375 | } | |
376 | ||
377 | int __weak omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, | |
378 | u8 st_shift) | |
379 | { | |
380 | WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n"); | |
381 | return 0; | |
382 | } | |
383 |