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3696a8a4 MR |
1 | /* |
2 | * linux/arch/arm/mach-pxa/cm-x270-pci.c | |
3 | * | |
4 | * PCI bios-type initialisation for PCI machines | |
5 | * | |
6 | * Bits taken from various places. | |
7 | * | |
2f01a973 | 8 | * Copyright (C) 2007, 2008 Compulab, Ltd. |
3696a8a4 MR |
9 | * Mike Rapoport <mike@compulab.co.il> |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/irq.h> | |
2f01a973 | 22 | #include <linux/gpio.h> |
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23 | |
24 | #include <asm/mach/pci.h> | |
a09e64fb | 25 | #include <mach/pxa-regs.h> |
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26 | #include <asm/mach-types.h> |
27 | ||
28 | #include <asm/hardware/it8152.h> | |
29 | ||
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30 | unsigned long it8152_base_address; |
31 | static int cmx270_it8152_irq_gpio; | |
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32 | |
33 | /* | |
34 | * Only first 64MB of memory can be accessed via PCI. | |
35 | * We use GFP_DMA to allocate safe buffers to do map/unmap. | |
36 | * This is really ugly and we need a better way of specifying | |
37 | * DMA-capable regions of memory. | |
38 | */ | |
39 | void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size, | |
40 | unsigned long *zhole_size) | |
41 | { | |
42 | unsigned int sz = SZ_64M >> PAGE_SHIFT; | |
43 | ||
5855a1e3 | 44 | if (machine_is_armcore()) { |
2f01a973 | 45 | pr_info("Adjusting zones for CM-X270\n"); |
5855a1e3 MR |
46 | |
47 | /* | |
48 | * Only adjust if > 64M on current system | |
49 | */ | |
50 | if (node || (zone_size[0] <= sz)) | |
51 | return; | |
52 | ||
53 | zone_size[1] = zone_size[0] - sz; | |
54 | zone_size[0] = sz; | |
55 | zhole_size[1] = zhole_size[0]; | |
56 | zhole_size[0] = 0; | |
57 | } | |
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58 | } |
59 | ||
60 | static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) | |
61 | { | |
62 | /* clear our parent irq */ | |
2f01a973 | 63 | GEDR(cmx270_it8152_irq_gpio) = GPIO_bit(cmx270_it8152_irq_gpio); |
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64 | |
65 | it8152_irq_demux(irq, desc); | |
66 | } | |
67 | ||
2f01a973 | 68 | void __cmx270_pci_init_irq(int irq_gpio) |
3696a8a4 MR |
69 | { |
70 | it8152_init_irq(); | |
3696a8a4 | 71 | |
2f01a973 MR |
72 | cmx270_it8152_irq_gpio = irq_gpio; |
73 | ||
6cab4860 | 74 | set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); |
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75 | |
76 | set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx270_it8152_irq_demux); | |
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77 | } |
78 | ||
79 | #ifdef CONFIG_PM | |
80 | static unsigned long sleep_save_ite[10]; | |
81 | ||
82 | void __cmx270_pci_suspend(void) | |
83 | { | |
84 | /* save ITE state */ | |
85 | sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR); | |
86 | sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR); | |
87 | sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR); | |
88 | ||
89 | /* Clear ITE IRQ's */ | |
90 | __raw_writel((0), IT8152_INTC_PDCNIRR); | |
91 | __raw_writel((0), IT8152_INTC_LPCNIRR); | |
92 | } | |
93 | ||
94 | void __cmx270_pci_resume(void) | |
95 | { | |
96 | /* restore IT8152 state */ | |
97 | __raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR); | |
98 | __raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR); | |
99 | __raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR); | |
100 | } | |
101 | #else | |
102 | void cmx270_pci_suspend(void) {} | |
103 | void cmx270_pci_resume(void) {} | |
104 | #endif | |
105 | ||
106 | /* PCI IRQ mapping*/ | |
107 | static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |
108 | { | |
109 | int irq; | |
110 | ||
8e86f427 | 111 | dev_dbg(&dev->dev, "%s: slot=%x, pin=%x\n", __func__, slot, pin); |
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112 | |
113 | irq = it8152_pci_map_irq(dev, slot, pin); | |
114 | if (irq) | |
115 | return irq; | |
116 | ||
117 | /* | |
118 | Here comes the ugly part. The routing is baseboard specific, | |
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119 | but defining a platform for each possible base of CM-X270 is |
120 | unrealistic. Here we keep mapping for ATXBase and SB-X270. | |
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121 | */ |
122 | /* ATXBASE PCI slot */ | |
123 | if (slot == 7) | |
124 | return IT8152_PCI_INTA; | |
125 | ||
126 | /* ATXBase/SB-x270 CardBus */ | |
127 | if (slot == 8 || slot == 0) | |
128 | return IT8152_PCI_INTB; | |
129 | ||
130 | /* ATXBase Ethernet */ | |
131 | if (slot == 9) | |
132 | return IT8152_PCI_INTA; | |
133 | ||
134 | /* SB-x270 Ethernet */ | |
135 | if (slot == 16) | |
136 | return IT8152_PCI_INTA; | |
137 | ||
138 | /* PC104+ interrupt routing */ | |
139 | if ((slot == 17) || (slot == 19)) | |
140 | return IT8152_PCI_INTA; | |
141 | if ((slot == 18) || (slot == 20)) | |
142 | return IT8152_PCI_INTB; | |
143 | ||
144 | return(0); | |
145 | } | |
146 | ||
a0113a99 | 147 | static void cmx270_pci_preinit(void) |
3696a8a4 | 148 | { |
a0113a99 | 149 | pr_info("Initializing CM-X270 PCI subsystem\n"); |
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150 | |
151 | __raw_writel(0x800, IT8152_PCI_CFG_ADDR); | |
152 | if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) { | |
a0113a99 | 153 | pr_info("PCI Bridge found.\n"); |
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154 | |
155 | /* set PCI I/O base at 0 */ | |
156 | writel(0x848, IT8152_PCI_CFG_ADDR); | |
157 | writel(0, IT8152_PCI_CFG_DATA); | |
158 | ||
159 | /* set PCI memory base at 0 */ | |
160 | writel(0x840, IT8152_PCI_CFG_ADDR); | |
161 | writel(0, IT8152_PCI_CFG_DATA); | |
162 | ||
163 | writel(0x20, IT8152_GPIO_GPDR); | |
164 | ||
165 | /* CardBus Controller on ATXbase baseboard */ | |
166 | writel(0x4000, IT8152_PCI_CFG_ADDR); | |
167 | if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) { | |
a0113a99 | 168 | pr_info("CardBus Bridge found.\n"); |
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169 | |
170 | /* Configure socket 0 */ | |
171 | writel(0x408C, IT8152_PCI_CFG_ADDR); | |
172 | writel(0x1022, IT8152_PCI_CFG_DATA); | |
173 | ||
174 | writel(0x4080, IT8152_PCI_CFG_ADDR); | |
175 | writel(0x3844d060, IT8152_PCI_CFG_DATA); | |
176 | ||
177 | writel(0x4090, IT8152_PCI_CFG_ADDR); | |
178 | writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) | | |
179 | 0x60440000), | |
180 | IT8152_PCI_CFG_DATA); | |
181 | ||
182 | writel(0x4018, IT8152_PCI_CFG_ADDR); | |
183 | writel(0xb0000000, IT8152_PCI_CFG_DATA); | |
184 | ||
185 | /* Configure socket 1 */ | |
186 | writel(0x418C, IT8152_PCI_CFG_ADDR); | |
187 | writel(0x1022, IT8152_PCI_CFG_DATA); | |
188 | ||
189 | writel(0x4180, IT8152_PCI_CFG_ADDR); | |
190 | writel(0x3844d060, IT8152_PCI_CFG_DATA); | |
191 | ||
192 | writel(0x4190, IT8152_PCI_CFG_ADDR); | |
193 | writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) | | |
194 | 0x60440000), | |
195 | IT8152_PCI_CFG_DATA); | |
196 | ||
197 | writel(0x4118, IT8152_PCI_CFG_ADDR); | |
198 | writel(0xb0000000, IT8152_PCI_CFG_DATA); | |
199 | } | |
200 | } | |
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201 | } |
202 | ||
203 | static struct hw_pci cmx270_pci __initdata = { | |
204 | .swizzle = pci_std_swizzle, | |
205 | .map_irq = cmx270_pci_map_irq, | |
206 | .nr_controllers = 1, | |
207 | .setup = it8152_pci_setup, | |
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208 | .scan = it8152_pci_scan_bus, |
209 | .preinit = cmx270_pci_preinit, | |
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210 | }; |
211 | ||
212 | static int __init cmx270_init_pci(void) | |
213 | { | |
214 | if (machine_is_armcore()) | |
215 | pci_common_init(&cmx270_pci); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
220 | subsys_initcall(cmx270_init_pci); |