[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-spear6xx / include / mach / misc_regs.h

/*
 * arch/arm/mach-spear6xx/include/mach/misc_regs.h
 *
 * Miscellaneous registers definitions for SPEAr6xx machine family
 *
 * Copyright (C) 2009 ST Microelectronics
 * Viresh Kumar<viresh.kumar@st.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef __MACH_MISC_REGS_H
#define __MACH_MISC_REGS_H

#include <mach/hardware.h>

#define MISC_BASE		IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)

#define SOC_CFG_CTR		(MISC_BASE + 0x000)
#define DIAG_CFG_CTR		(MISC_BASE + 0x004)
#define PLL1_CTR		(MISC_BASE + 0x008)
#define PLL1_FRQ		(MISC_BASE + 0x00C)
#define PLL1_MOD		(MISC_BASE + 0x010)
#define PLL2_CTR		(MISC_BASE + 0x014)
/* PLL_CTR register masks */
#define PLL_ENABLE		2
#define PLL_MODE_SHIFT		4
#define PLL_MODE_MASK		0x3
#define PLL_MODE_NORMAL		0
#define PLL_MODE_FRACTION	1
#define PLL_MODE_DITH_DSB	2
#define PLL_MODE_DITH_SSB	3

#define PLL2_FRQ		(MISC_BASE + 0x018)
/* PLL FRQ register masks */
#define PLL_DIV_N_SHIFT		0
#define PLL_DIV_N_MASK		0xFF
#define PLL_DIV_P_SHIFT		8
#define PLL_DIV_P_MASK		0x7
#define PLL_NORM_FDBK_M_SHIFT	24
#define PLL_NORM_FDBK_M_MASK	0xFF
#define PLL_DITH_FDBK_M_SHIFT	16
#define PLL_DITH_FDBK_M_MASK	0xFFFF

#define PLL2_MOD		(MISC_BASE + 0x01C)
#define PLL_CLK_CFG		(MISC_BASE + 0x020)
#define CORE_CLK_CFG		(MISC_BASE + 0x024)
/* CORE CLK CFG register masks */
#define PLL_HCLK_RATIO_SHIFT	10
#define PLL_HCLK_RATIO_MASK	0x3
#define HCLK_PCLK_RATIO_SHIFT	8
#define HCLK_PCLK_RATIO_MASK	0x3

#define PERIP_CLK_CFG		(MISC_BASE + 0x028)
/* PERIP_CLK_CFG register masks */
#define CLCD_CLK_SHIFT		2
#define CLCD_CLK_MASK		0x3
#define UART_CLK_SHIFT		4
#define UART_CLK_MASK		0x1
#define FIRDA_CLK_SHIFT		5
#define FIRDA_CLK_MASK		0x3
#define GPT0_CLK_SHIFT		8
#define GPT1_CLK_SHIFT		10
#define GPT2_CLK_SHIFT		11
#define GPT3_CLK_SHIFT		12
#define GPT_CLK_MASK		0x1
#define AUX_CLK_PLL3_VAL	0
#define AUX_CLK_PLL1_VAL	1

#define PERIP1_CLK_ENB		(MISC_BASE + 0x02C)
/* PERIP1_CLK_ENB register masks */
#define UART0_CLK_ENB		3
#define UART1_CLK_ENB		4
#define SSP0_CLK_ENB		5
#define SSP1_CLK_ENB		6
#define I2C_CLK_ENB		7
#define JPEG_CLK_ENB		8
#define FSMC_CLK_ENB		9
#define FIRDA_CLK_ENB		10
#define GPT2_CLK_ENB		11
#define GPT3_CLK_ENB		12
#define GPIO2_CLK_ENB		13
#define SSP2_CLK_ENB		14
#define ADC_CLK_ENB		15
#define GPT1_CLK_ENB		11
#define RTC_CLK_ENB		17
#define GPIO1_CLK_ENB		18
#define DMA_CLK_ENB		19
#define SMI_CLK_ENB		21
#define CLCD_CLK_ENB		22
#define GMAC_CLK_ENB		23
#define USBD_CLK_ENB		24
#define USBH0_CLK_ENB		25
#define USBH1_CLK_ENB		26

#define SOC_CORE_ID		(MISC_BASE + 0x030)
#define RAS_CLK_ENB		(MISC_BASE + 0x034)
#define PERIP1_SOF_RST		(MISC_BASE + 0x038)
/* PERIP1_SOF_RST register masks */
#define JPEG_SOF_RST		8

#define SOC_USER_ID		(MISC_BASE + 0x03C)
#define RAS_SOF_RST		(MISC_BASE + 0x040)
#define PRSC1_CLK_CFG		(MISC_BASE + 0x044)
#define PRSC2_CLK_CFG		(MISC_BASE + 0x048)
#define PRSC3_CLK_CFG		(MISC_BASE + 0x04C)
/* gpt synthesizer register masks */
#define GPT_MSCALE_SHIFT	0
#define GPT_MSCALE_MASK		0xFFF
#define GPT_NSCALE_SHIFT	12
#define GPT_NSCALE_MASK		0xF

#define AMEM_CLK_CFG		(MISC_BASE + 0x050)
#define EXPI_CLK_CFG		(MISC_BASE + 0x054)
#define CLCD_CLK_SYNT		(MISC_BASE + 0x05C)
#define FIRDA_CLK_SYNT		(MISC_BASE + 0x060)
#define UART_CLK_SYNT		(MISC_BASE + 0x064)
#define GMAC_CLK_SYNT		(MISC_BASE + 0x068)
#define RAS1_CLK_SYNT		(MISC_BASE + 0x06C)
#define RAS2_CLK_SYNT		(MISC_BASE + 0x070)
#define RAS3_CLK_SYNT		(MISC_BASE + 0x074)
#define RAS4_CLK_SYNT		(MISC_BASE + 0x078)
/* aux clk synthesiser register masks for irda to ras4 */
#define AUX_SYNT_ENB		31
#define AUX_EQ_SEL_SHIFT	30
#define AUX_EQ_SEL_MASK		1
#define AUX_EQ1_SEL		0
#define AUX_EQ2_SEL		1
#define AUX_XSCALE_SHIFT	16
#define AUX_XSCALE_MASK		0xFFF
#define AUX_YSCALE_SHIFT	0
#define AUX_YSCALE_MASK		0xFFF

#define ICM1_ARB_CFG		(MISC_BASE + 0x07C)
#define ICM2_ARB_CFG		(MISC_BASE + 0x080)
#define ICM3_ARB_CFG		(MISC_BASE + 0x084)
#define ICM4_ARB_CFG		(MISC_BASE + 0x088)
#define ICM5_ARB_CFG		(MISC_BASE + 0x08C)
#define ICM6_ARB_CFG		(MISC_BASE + 0x090)
#define ICM7_ARB_CFG		(MISC_BASE + 0x094)
#define ICM8_ARB_CFG		(MISC_BASE + 0x098)
#define ICM9_ARB_CFG		(MISC_BASE + 0x09C)
#define DMA_CHN_CFG		(MISC_BASE + 0x0A0)
#define USB2_PHY_CFG		(MISC_BASE + 0x0A4)
#define GMAC_CFG_CTR		(MISC_BASE + 0x0A8)
#define EXPI_CFG_CTR		(MISC_BASE + 0x0AC)
#define PRC1_LOCK_CTR		(MISC_BASE + 0x0C0)
#define PRC2_LOCK_CTR		(MISC_BASE + 0x0C4)
#define PRC3_LOCK_CTR		(MISC_BASE + 0x0C8)
#define PRC4_LOCK_CTR		(MISC_BASE + 0x0CC)
#define PRC1_IRQ_CTR		(MISC_BASE + 0x0D0)
#define PRC2_IRQ_CTR		(MISC_BASE + 0x0D4)
#define PRC3_IRQ_CTR		(MISC_BASE + 0x0D8)
#define PRC4_IRQ_CTR		(MISC_BASE + 0x0DC)
#define PWRDOWN_CFG_CTR		(MISC_BASE + 0x0E0)
#define COMPSSTL_1V8_CFG	(MISC_BASE + 0x0E4)
#define COMPSSTL_2V5_CFG	(MISC_BASE + 0x0E8)
#define COMPCOR_3V3_CFG		(MISC_BASE + 0x0EC)
#define SSTLPAD_CFG_CTR		(MISC_BASE + 0x0F0)
#define BIST1_CFG_CTR		(MISC_BASE + 0x0F4)
#define BIST2_CFG_CTR		(MISC_BASE + 0x0F8)
#define BIST3_CFG_CTR		(MISC_BASE + 0x0FC)
#define BIST4_CFG_CTR		(MISC_BASE + 0x100)
#define BIST5_CFG_CTR		(MISC_BASE + 0x104)
#define BIST1_STS_RES		(MISC_BASE + 0x108)
#define BIST2_STS_RES		(MISC_BASE + 0x10C)
#define BIST3_STS_RES		(MISC_BASE + 0x110)
#define BIST4_STS_RES		(MISC_BASE + 0x114)
#define BIST5_STS_RES		(MISC_BASE + 0x118)
#define SYSERR_CFG_CTR		(MISC_BASE + 0x11C)

#endif /* __MACH_MISC_REGS_H */
Commit	Line	Data
e024c3d5 VK	1	/*
	2	* arch/arm/mach-spear6xx/include/mach/misc_regs.h
	3	*
	4	* Miscellaneous registers definitions for SPEAr6xx machine family
	5	*
	6	* Copyright (C) 2009 ST Microelectronics
	7	* Viresh Kumar<viresh.kumar@st.com>
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#ifndef __MACH_MISC_REGS_H
	15	#define __MACH_MISC_REGS_H
	16
02aa06bc	17	#include <mach/hardware.h>
e024c3d5	18
f9324a85	19	#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
e024c3d5	20
f9324a85 VK	21	#define SOC_CFG_CTR (MISC_BASE + 0x000)
	22	#define DIAG_CFG_CTR (MISC_BASE + 0x004)
	23	#define PLL1_CTR (MISC_BASE + 0x008)
	24	#define PLL1_FRQ (MISC_BASE + 0x00C)
	25	#define PLL1_MOD (MISC_BASE + 0x010)
	26	#define PLL2_CTR (MISC_BASE + 0x014)
e024c3d5 VK	27	/* PLL_CTR register masks */
	28	#define PLL_ENABLE 2
	29	#define PLL_MODE_SHIFT 4
	30	#define PLL_MODE_MASK 0x3
	31	#define PLL_MODE_NORMAL 0
	32	#define PLL_MODE_FRACTION 1
	33	#define PLL_MODE_DITH_DSB 2
	34	#define PLL_MODE_DITH_SSB 3
	35
f9324a85	36	#define PLL2_FRQ (MISC_BASE + 0x018)
e024c3d5 VK	37	/* PLL FRQ register masks */
	38	#define PLL_DIV_N_SHIFT 0
	39	#define PLL_DIV_N_MASK 0xFF
	40	#define PLL_DIV_P_SHIFT 8
	41	#define PLL_DIV_P_MASK 0x7
	42	#define PLL_NORM_FDBK_M_SHIFT 24
	43	#define PLL_NORM_FDBK_M_MASK 0xFF
	44	#define PLL_DITH_FDBK_M_SHIFT 16
	45	#define PLL_DITH_FDBK_M_MASK 0xFFFF
	46
f9324a85 VK	47	#define PLL2_MOD (MISC_BASE + 0x01C)
	48	#define PLL_CLK_CFG (MISC_BASE + 0x020)
	49	#define CORE_CLK_CFG (MISC_BASE + 0x024)
e024c3d5 VK	50	/* CORE CLK CFG register masks */
	51	#define PLL_HCLK_RATIO_SHIFT 10
	52	#define PLL_HCLK_RATIO_MASK 0x3
	53	#define HCLK_PCLK_RATIO_SHIFT 8
	54	#define HCLK_PCLK_RATIO_MASK 0x3
	55
f9324a85	56	#define PERIP_CLK_CFG (MISC_BASE + 0x028)
e024c3d5 VK	57	/* PERIP_CLK_CFG register masks */
	58	#define CLCD_CLK_SHIFT 2
	59	#define CLCD_CLK_MASK 0x3
	60	#define UART_CLK_SHIFT 4
	61	#define UART_CLK_MASK 0x1
	62	#define FIRDA_CLK_SHIFT 5
	63	#define FIRDA_CLK_MASK 0x3
	64	#define GPT0_CLK_SHIFT 8
	65	#define GPT1_CLK_SHIFT 10
	66	#define GPT2_CLK_SHIFT 11
	67	#define GPT3_CLK_SHIFT 12
	68	#define GPT_CLK_MASK 0x1
af89fd81 VK	69	#define AUX_CLK_PLL3_VAL 0
af89fd81 VK	70	#define AUX_CLK_PLL1_VAL 1
e024c3d5	71
f9324a85	72	#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
e024c3d5 VK	73	/* PERIP1_CLK_ENB register masks */
	74	#define UART0_CLK_ENB 3
	75	#define UART1_CLK_ENB 4
	76	#define SSP0_CLK_ENB 5
	77	#define SSP1_CLK_ENB 6
	78	#define I2C_CLK_ENB 7
	79	#define JPEG_CLK_ENB 8
	80	#define FSMC_CLK_ENB 9
	81	#define FIRDA_CLK_ENB 10
	82	#define GPT2_CLK_ENB 11
	83	#define GPT3_CLK_ENB 12
	84	#define GPIO2_CLK_ENB 13
	85	#define SSP2_CLK_ENB 14
	86	#define ADC_CLK_ENB 15
	87	#define GPT1_CLK_ENB 11
	88	#define RTC_CLK_ENB 17
	89	#define GPIO1_CLK_ENB 18
	90	#define DMA_CLK_ENB 19
	91	#define SMI_CLK_ENB 21
	92	#define CLCD_CLK_ENB 22
	93	#define GMAC_CLK_ENB 23
	94	#define USBD_CLK_ENB 24
	95	#define USBH0_CLK_ENB 25
	96	#define USBH1_CLK_ENB 26
	97
f9324a85 VK	98	#define SOC_CORE_ID (MISC_BASE + 0x030)
	99	#define RAS_CLK_ENB (MISC_BASE + 0x034)
	100	#define PERIP1_SOF_RST (MISC_BASE + 0x038)
e024c3d5 VK	101	/* PERIP1_SOF_RST register masks */
	102	#define JPEG_SOF_RST 8
	103
f9324a85 VK	104	#define SOC_USER_ID (MISC_BASE + 0x03C)
	105	#define RAS_SOF_RST (MISC_BASE + 0x040)
	106	#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
	107	#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
	108	#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
e024c3d5 VK	109	/* gpt synthesizer register masks */
	110	#define GPT_MSCALE_SHIFT 0
	111	#define GPT_MSCALE_MASK 0xFFF
	112	#define GPT_NSCALE_SHIFT 12
	113	#define GPT_NSCALE_MASK 0xF
	114
f9324a85 VK	115	#define AMEM_CLK_CFG (MISC_BASE + 0x050)
	116	#define EXPI_CLK_CFG (MISC_BASE + 0x054)
	117	#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
	118	#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
	119	#define UART_CLK_SYNT (MISC_BASE + 0x064)
	120	#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
	121	#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
	122	#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
	123	#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
	124	#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
e024c3d5	125	/* aux clk synthesiser register masks for irda to ras4 */
af89fd81	126	#define AUX_SYNT_ENB 31
e024c3d5 VK	127	#define AUX_EQ_SEL_SHIFT 30
	128	#define AUX_EQ_SEL_MASK 1
	129	#define AUX_EQ1_SEL 0
	130	#define AUX_EQ2_SEL 1
	131	#define AUX_XSCALE_SHIFT 16
	132	#define AUX_XSCALE_MASK 0xFFF
	133	#define AUX_YSCALE_SHIFT 0
	134	#define AUX_YSCALE_MASK 0xFFF
	135
f9324a85 VK	136	#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
	137	#define ICM2_ARB_CFG (MISC_BASE + 0x080)
	138	#define ICM3_ARB_CFG (MISC_BASE + 0x084)
	139	#define ICM4_ARB_CFG (MISC_BASE + 0x088)
	140	#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
	141	#define ICM6_ARB_CFG (MISC_BASE + 0x090)
	142	#define ICM7_ARB_CFG (MISC_BASE + 0x094)
	143	#define ICM8_ARB_CFG (MISC_BASE + 0x098)
	144	#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
	145	#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
	146	#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
	147	#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
	148	#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
	149	#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
	150	#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
	151	#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
	152	#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
	153	#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
	154	#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
	155	#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
	156	#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
	157	#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
	158	#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
	159	#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
	160	#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
	161	#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
	162	#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
	163	#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
	164	#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
	165	#define BIST4_CFG_CTR (MISC_BASE + 0x100)
	166	#define BIST5_CFG_CTR (MISC_BASE + 0x104)
	167	#define BIST1_STS_RES (MISC_BASE + 0x108)
	168	#define BIST2_STS_RES (MISC_BASE + 0x10C)
	169	#define BIST3_STS_RES (MISC_BASE + 0x110)
	170	#define BIST4_STS_RES (MISC_BASE + 0x114)
	171	#define BIST5_STS_RES (MISC_BASE + 0x118)
	172	#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
e024c3d5 VK	173
e024c3d5 VK	174	#endif /* __MACH_MISC_REGS_H */