[mirror_ubuntu-bionic-kernel.git] / arch / arm / plat-iop / time.c

/*
 * arch/arm/plat-iop/time.c
 *
 * Timer code for IOP32x and IOP33x based systems
 *
 * Author: Deepak Saxena <dsaxena@mvista.com>
 *
 * Copyright 2002-2003 MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/init.h>
#include <linux/timex.h>
#include <linux/io.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <mach/time.h>

/*
 * IOP clocksource (free-running timer 1).
 */
static cycle_t iop_clocksource_read(struct clocksource *unused)
{
	return 0xffffffffu - read_tcr1();
}

static struct clocksource iop_clocksource = {
	.name 		= "iop_timer1",
	.rating		= 300,
	.read		= iop_clocksource_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz)
{
	u64 temp;
	u32 shift;

	/* Find shift and mult values for hz. */
	shift = 32;
	do {
		temp = (u64) NSEC_PER_SEC << shift;
		do_div(temp, hz);
		if ((temp >> 32) == 0)
			break;
	} while (--shift != 0);

	cs->shift = shift;
	cs->mult = (u32) temp;

	printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n",
	       cs->name, cs->shift, cs->mult);
}

/*
 * IOP clockevents (interrupting timer 0).
 */
static int iop_set_next_event(unsigned long delta,
			      struct clock_event_device *unused)
{
	u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;

	BUG_ON(delta == 0);
	write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
	write_tcr0(delta);
	write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);

	return 0;
}

static unsigned long ticks_per_jiffy;

static void iop_set_mode(enum clock_event_mode mode,
			 struct clock_event_device *unused)
{
	u32 tmr = read_tmr0();

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		write_tmr0(tmr & ~IOP_TMR_EN);
		write_tcr0(ticks_per_jiffy - 1);
		tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* ->set_next_event sets period and enables timer */
		tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
		break;
	case CLOCK_EVT_MODE_RESUME:
		tmr |= IOP_TMR_EN;
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
	default:
		tmr &= ~IOP_TMR_EN;
		break;
	}

	write_tmr0(tmr);
}

static struct clock_event_device iop_clockevent = {
	.name		= "iop_timer0",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.rating         = 300,
	.set_next_event	= iop_set_next_event,
	.set_mode	= iop_set_mode,
};

static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz)
{
	u64 temp;
	u32 shift;

	/* Find shift and mult values for hz. */
	shift = 32;
	do {
		temp = (u64) hz << shift;
		do_div(temp, NSEC_PER_SEC);
		if ((temp >> 32) == 0)
			break;
	} while (--shift != 0);

	ce->shift = shift;
	ce->mult = (u32) temp;

	printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n",
	       ce->name, ce->shift, ce->mult);
}

static irqreturn_t
iop_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	write_tisr(1);
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction iop_timer_irq = {
	.name		= "IOP Timer Tick",
	.handler	= iop_timer_interrupt,
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.dev_id		= &iop_clockevent,
};

static unsigned long iop_tick_rate;
unsigned long get_iop_tick_rate(void)
{
	return iop_tick_rate;
}
EXPORT_SYMBOL(get_iop_tick_rate);

void __init iop_init_time(unsigned long tick_rate)
{
	u32 timer_ctl;

	ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
	iop_tick_rate = tick_rate;

	timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
			IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;

	/*
	 * Set up interrupting clockevent timer 0.
	 */
	write_tmr0(timer_ctl & ~IOP_TMR_EN);
	setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
	iop_clockevent_set_hz(&iop_clockevent, tick_rate);
	iop_clockevent.max_delta_ns =
		clockevent_delta2ns(0xfffffffe, &iop_clockevent);
	iop_clockevent.min_delta_ns =
		clockevent_delta2ns(0xf, &iop_clockevent);
	iop_clockevent.cpumask = cpumask_of(0);
	clockevents_register_device(&iop_clockevent);
	write_trr0(ticks_per_jiffy - 1);
	write_tcr0(ticks_per_jiffy - 1);
	write_tmr0(timer_ctl);

	/*
	 * Set up free-running clocksource timer 1.
	 */
	write_trr1(0xffffffff);
	write_tcr1(0xffffffff);
	write_tmr1(timer_ctl);
	iop_clocksource_set_hz(&iop_clocksource, tick_rate);
	clocksource_register(&iop_clocksource);
}
Commit	Line	Data
48388b2a LB	1	/*
	2	* arch/arm/plat-iop/time.c
	3	*
	4	* Timer code for IOP32x and IOP33x based systems
	5	*
	6	* Author: Deepak Saxena <dsaxena@mvista.com>
	7	*
	8	* Copyright 2002-2003 MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/time.h>
	19	#include <linux/init.h>
	20	#include <linux/timex.h>
fced80c7	21	#include <linux/io.h>
a91549a8	22	#include <linux/clocksource.h>
469d3044	23	#include <linux/clockchips.h>
a09e64fb	24	#include <mach/hardware.h>
48388b2a LB	25	#include <asm/irq.h>
	26	#include <asm/uaccess.h>
	27	#include <asm/mach/irq.h>
	28	#include <asm/mach/time.h>
a09e64fb	29	#include <mach/time.h>
48388b2a	30
a91549a8 MP	31	/*
	32	* IOP clocksource (free-running timer 1).
	33	*/
	34	static cycle_t iop_clocksource_read(struct clocksource *unused)
	35	{
	36	return 0xffffffffu - read_tcr1();
	37	}
	38
	39	static struct clocksource iop_clocksource = {
	40	.name = "iop_timer1",
	41	.rating = 300,
	42	.read = iop_clocksource_read,
	43	.mask = CLOCKSOURCE_MASK(32),
	44	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	45	};
	46
	47	static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz)
	48	{
	49	u64 temp;
	50	u32 shift;
	51
	52	/* Find shift and mult values for hz. */
	53	shift = 32;
	54	do {
	55	temp = (u64) NSEC_PER_SEC << shift;
	56	do_div(temp, hz);
	57	if ((temp >> 32) == 0)
	58	break;
	59	} while (--shift != 0);
	60
	61	cs->shift = shift;
	62	cs->mult = (u32) temp;
	63
	64	printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n",
	65	cs->name, cs->shift, cs->mult);
	66	}
	67
469d3044 MP	68	/*
	69	* IOP clockevents (interrupting timer 0).
	70	*/
	71	static int iop_set_next_event(unsigned long delta,
	72	struct clock_event_device *unused)
	73	{
	74	u32 tmr = IOP_TMR_PRIVILEGED \| IOP_TMR_RATIO_1_1;
	75
	76	BUG_ON(delta == 0);
	77	write_tmr0(tmr & ~(IOP_TMR_EN \| IOP_TMR_RELOAD));
	78	write_tcr0(delta);
	79	write_tmr0((tmr & ~IOP_TMR_RELOAD) \| IOP_TMR_EN);
	80
	81	return 0;
	82	}
	83
48388b2a	84	static unsigned long ticks_per_jiffy;
469d3044 MP	85
	86	static void iop_set_mode(enum clock_event_mode mode,
	87	struct clock_event_device *unused)
	88	{
	89	u32 tmr = read_tmr0();
	90
	91	switch (mode) {
	92	case CLOCK_EVT_MODE_PERIODIC:
	93	write_tmr0(tmr & ~IOP_TMR_EN);
	94	write_tcr0(ticks_per_jiffy - 1);
	95	tmr \|= (IOP_TMR_RELOAD \| IOP_TMR_EN);
	96	break;
	97	case CLOCK_EVT_MODE_ONESHOT:
	98	/* ->set_next_event sets period and enables timer */
	99	tmr &= ~(IOP_TMR_RELOAD \| IOP_TMR_EN);
	100	break;
	101	case CLOCK_EVT_MODE_RESUME:
	102	tmr \|= IOP_TMR_EN;
	103	break;
	104	case CLOCK_EVT_MODE_SHUTDOWN:
	105	case CLOCK_EVT_MODE_UNUSED:
	106	default:
	107	tmr &= ~IOP_TMR_EN;
	108	break;
	109	}
	110
	111	write_tmr0(tmr);
	112	}
	113
	114	static struct clock_event_device iop_clockevent = {
	115	.name = "iop_timer0",
	116	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	117	.rating = 300,
	118	.set_next_event = iop_set_next_event,
	119	.set_mode = iop_set_mode,
	120	};
	121
	122	static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz)
	123	{
	124	u64 temp;
	125	u32 shift;
	126
	127	/* Find shift and mult values for hz. */
	128	shift = 32;
	129	do {
	130	temp = (u64) hz << shift;
	131	do_div(temp, NSEC_PER_SEC);
	132	if ((temp >> 32) == 0)
	133	break;
	134	} while (--shift != 0);
	135
	136	ce->shift = shift;
	137	ce->mult = (u32) temp;
	138
	139	printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n",
	140	ce->name, ce->shift, ce->mult);
	141	}
	142
48388b2a	143	static irqreturn_t
3668b45d	144	iop_timer_interrupt(int irq, void *dev_id)
48388b2a	145	{
469d3044	146	struct clock_event_device *evt = dev_id;
48388b2a	147
469d3044 MP	148	write_tisr(1);
469d3044 MP	149	evt->event_handler(evt);
48388b2a LB	150	return IRQ_HANDLED;
	151	}
	152
3668b45d DW	153	static struct irqaction iop_timer_irq = {
	154	.name = "IOP Timer Tick",
	155	.handler = iop_timer_interrupt,
b30fabad	156	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
469d3044	157	.dev_id = &iop_clockevent,
48388b2a LB	158	};
48388b2a LB	159
70c14ff0 DW	160	static unsigned long iop_tick_rate;
	161	unsigned long get_iop_tick_rate(void)
	162	{
	163	return iop_tick_rate;
	164	}
	165	EXPORT_SYMBOL(get_iop_tick_rate);
	166
3668b45d	167	void __init iop_init_time(unsigned long tick_rate)
48388b2a LB	168	{
	169	u32 timer_ctl;
	170
a692838d	171	ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
70c14ff0	172	iop_tick_rate = tick_rate;
48388b2a	173
3668b45d DW	174	timer_ctl = IOP_TMR_EN \| IOP_TMR_PRIVILEGED \|
3668b45d DW	175	IOP_TMR_RELOAD \| IOP_TMR_RATIO_1_1;
48388b2a LB	176
48388b2a LB	177	/*
469d3044	178	* Set up interrupting clockevent timer 0.
48388b2a	179	*/
469d3044 MP	180	write_tmr0(timer_ctl & ~IOP_TMR_EN);
	181	setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
	182	iop_clockevent_set_hz(&iop_clockevent, tick_rate);
	183	iop_clockevent.max_delta_ns =
	184	clockevent_delta2ns(0xfffffffe, &iop_clockevent);
	185	iop_clockevent.min_delta_ns =
	186	clockevent_delta2ns(0xf, &iop_clockevent);
	187	iop_clockevent.cpumask = cpumask_of(0);
	188	clockevents_register_device(&iop_clockevent);
3668b45d	189	write_trr0(ticks_per_jiffy - 1);
469d3044	190	write_tcr0(ticks_per_jiffy - 1);
3668b45d	191	write_tmr0(timer_ctl);
a91549a8 MP	192
	193	/*
	194	* Set up free-running clocksource timer 1.
	195	*/
3668b45d	196	write_trr1(0xffffffff);
a91549a8	197	write_tcr1(0xffffffff);
3668b45d	198	write_tmr1(timer_ctl);
a91549a8 MP	199	iop_clocksource_set_hz(&iop_clocksource, tick_rate);
a91549a8 MP	200	clocksource_register(&iop_clocksource);
48388b2a	201	}