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Commit | Line | Data |
---|---|---|
8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
b6197b93 | 3 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 4 | select ACPI_GENERIC_GSI if ACPI |
5f1ae4eb | 5 | select ACPI_GTDT if ACPI |
c6bb8f89 | 6 | select ACPI_IORT if ACPI |
6933de0c | 7 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
0cb0786b | 8 | select ACPI_MCFG if ACPI |
888125a7 | 9 | select ACPI_SPCR_TABLE if ACPI |
1d8f51d4 | 10 | select ARCH_CLOCKSOURCE_DATA |
ec6d06ef | 11 | select ARCH_HAS_DEBUG_VIRTUAL |
21266be9 | 12 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
38b04a74 | 13 | select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI |
2b68f6ca | 14 | select ARCH_HAS_ELF_RANDOMIZE |
6974f0c4 | 15 | select ARCH_HAS_FORTIFY_SOURCE |
957e3fac | 16 | select ARCH_HAS_GCOV_PROFILE_ALL |
e1073d1e | 17 | select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA |
5e4c7549 | 18 | select ARCH_HAS_KCOV |
d2852a22 | 19 | select ARCH_HAS_SET_MEMORY |
308c09f1 | 20 | select ARCH_HAS_SG_CHAIN |
ad21fc4f LA |
21 | select ARCH_HAS_STRICT_KERNEL_RWX |
22 | select ARCH_HAS_STRICT_MODULE_RWX | |
1f85008e | 23 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
7edda088 | 24 | select ARCH_HAVE_NMI_SAFE_CMPXCHG if ACPI_APEI_SEA |
92126689 WD |
25 | select ARCH_INLINE_READ_LOCK if !PREEMPT |
26 | select ARCH_INLINE_READ_LOCK_BH if !PREEMPT | |
27 | select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT | |
28 | select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT | |
29 | select ARCH_INLINE_READ_UNLOCK if !PREEMPT | |
30 | select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT | |
31 | select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT | |
32 | select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT | |
33 | select ARCH_INLINE_WRITE_LOCK if !PREEMPT | |
34 | select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT | |
35 | select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT | |
36 | select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT | |
37 | select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT | |
38 | select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT | |
39 | select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT | |
40 | select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT | |
c63c8700 | 41 | select ARCH_USE_CMPXCHG_LOCKREF |
92126689 | 42 | select ARCH_USE_QUEUED_RWLOCKS |
c484f256 | 43 | select ARCH_SUPPORTS_MEMORY_FAILURE |
4badad35 | 44 | select ARCH_SUPPORTS_ATOMIC_RMW |
56166230 | 45 | select ARCH_SUPPORTS_NUMA_BALANCING |
6212a512 | 46 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 47 | select ARCH_WANT_FRAME_POINTERS |
f0b7f8a4 | 48 | select ARCH_HAS_UBSAN_SANITIZE_ALL |
25c92a37 | 49 | select ARM_AMBA |
1aee5d7a | 50 | select ARM_ARCH_TIMER |
c4188edc | 51 | select ARM_GIC |
875cbf3e | 52 | select AUDIT_ARCH_COMPAT_GENERIC |
3ee80364 | 53 | select ARM_GIC_V2M if PCI |
021f6537 | 54 | select ARM_GIC_V3 |
3ee80364 | 55 | select ARM_GIC_V3_ITS if PCI |
bff60792 | 56 | select ARM_PSCI_FW |
adace895 | 57 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 58 | select CLONE_BACKWARDS |
7ca2ef33 | 59 | select COMMON_CLK |
166936ba | 60 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7bc13fd3 | 61 | select DCACHE_WORD_ACCESS |
ef37566c | 62 | select EDAC_SUPPORT |
2f34f173 | 63 | select FRAME_POINTER |
d4932f9e | 64 | select GENERIC_ALLOCATOR |
2ef7a295 | 65 | select GENERIC_ARCH_TOPOLOGY |
8c2c3df3 | 66 | select GENERIC_CLOCKEVENTS |
4b3dc967 | 67 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 68 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 69 | select GENERIC_EARLY_IOREMAP |
2314ee4d | 70 | select GENERIC_IDLE_POLL_SETUP |
8c2c3df3 CM |
71 | select GENERIC_IRQ_PROBE |
72 | select GENERIC_IRQ_SHOW | |
6544e67b | 73 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 74 | select GENERIC_PCI_IOMAP |
65cd4f6c | 75 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 76 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
77 | select GENERIC_STRNCPY_FROM_USER |
78 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 79 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 80 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 81 | select HARDIRQS_SW_RESEND |
9f9a35a7 | 82 | select HAVE_ACPI_APEI if (ACPI && EFI) |
5284e1b4 | 83 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 84 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 85 | select HAVE_ARCH_BITREVERSE |
324420bf | 86 | select HAVE_ARCH_HUGE_VMAP |
9732cafd | 87 | select HAVE_ARCH_JUMP_LABEL |
f1b9032f | 88 | select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) |
9529247d | 89 | select HAVE_ARCH_KGDB |
8f0d3aa9 DC |
90 | select HAVE_ARCH_MMAP_RND_BITS |
91 | select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT | |
a1ae65b2 | 92 | select HAVE_ARCH_SECCOMP_FILTER |
8c2c3df3 | 93 | select HAVE_ARCH_TRACEHOOK |
8ee70879 | 94 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE |
7d3b617f | 95 | select HAVE_ARCH_VMAP_STACK |
8ee70879 | 96 | select HAVE_ARM_SMCCC |
6077776b | 97 | select HAVE_EBPF_JIT |
af64d2aa | 98 | select HAVE_C_RECORDMCOUNT |
c0c264ae | 99 | select HAVE_CC_STACKPROTECTOR |
5284e1b4 | 100 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 101 | select HAVE_CMPXCHG_LOCAL |
8ee70879 | 102 | select HAVE_CONTEXT_TRACKING |
9b2a60c4 | 103 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 104 | select HAVE_DEBUG_KMEMLEAK |
8c2c3df3 | 105 | select HAVE_DMA_API_DEBUG |
6ac2104d | 106 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 107 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 108 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 109 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
110 | select HAVE_FUNCTION_TRACER |
111 | select HAVE_FUNCTION_GRAPH_TRACER | |
6b90bd4b | 112 | select HAVE_GCC_PLUGINS |
8c2c3df3 | 113 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 114 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
24da208d | 115 | select HAVE_IRQ_TIME_ACCOUNTING |
8c2c3df3 | 116 | select HAVE_MEMBLOCK |
1a2db300 | 117 | select HAVE_MEMBLOCK_NODE_MAP if NUMA |
7edda088 | 118 | select HAVE_NMI if ACPI_APEI_SEA |
55834a77 | 119 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 120 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
121 | select HAVE_PERF_REGS |
122 | select HAVE_PERF_USER_STACK_DUMP | |
0a8ea52c | 123 | select HAVE_REGS_AND_STACK_ACCESS_API |
5e5f6dc1 | 124 | select HAVE_RCU_TABLE_FREE |
055b1212 | 125 | select HAVE_SYSCALL_TRACEPOINTS |
2dd0e8d2 | 126 | select HAVE_KPROBES |
cd1ee3b1 | 127 | select HAVE_KRETPROBES |
876945db | 128 | select IOMMU_DMA if IOMMU_SUPPORT |
8c2c3df3 | 129 | select IRQ_DOMAIN |
e8557d1f | 130 | select IRQ_FORCED_THREADING |
fea2acaa | 131 | select MODULES_USE_ELF_RELA |
8c2c3df3 CM |
132 | select NO_BOOTMEM |
133 | select OF | |
134 | select OF_EARLY_FLATTREE | |
9bf14b7c | 135 | select OF_RESERVED_MEM |
0cb0786b | 136 | select PCI_ECAM if ACPI |
aa1e8ec1 CM |
137 | select POWER_RESET |
138 | select POWER_SUPPLY | |
8c2c3df3 | 139 | select SPARSE_IRQ |
7ac57a89 | 140 | select SYSCTL_EXCEPTION_TRACE |
c02433dd | 141 | select THREAD_INFO_IN_TASK |
8c2c3df3 CM |
142 | help |
143 | ARM 64-bit (AArch64) Linux support. | |
144 | ||
145 | config 64BIT | |
146 | def_bool y | |
147 | ||
148 | config ARCH_PHYS_ADDR_T_64BIT | |
149 | def_bool y | |
150 | ||
151 | config MMU | |
152 | def_bool y | |
153 | ||
030c4d24 MR |
154 | config ARM64_PAGE_SHIFT |
155 | int | |
156 | default 16 if ARM64_64K_PAGES | |
157 | default 14 if ARM64_16K_PAGES | |
158 | default 12 | |
159 | ||
160 | config ARM64_CONT_SHIFT | |
161 | int | |
162 | default 5 if ARM64_64K_PAGES | |
163 | default 7 if ARM64_16K_PAGES | |
164 | default 4 | |
165 | ||
8f0d3aa9 DC |
166 | config ARCH_MMAP_RND_BITS_MIN |
167 | default 14 if ARM64_64K_PAGES | |
168 | default 16 if ARM64_16K_PAGES | |
169 | default 18 | |
170 | ||
171 | # max bits determined by the following formula: | |
172 | # VA_BITS - PAGE_SHIFT - 3 | |
173 | config ARCH_MMAP_RND_BITS_MAX | |
174 | default 19 if ARM64_VA_BITS=36 | |
175 | default 24 if ARM64_VA_BITS=39 | |
176 | default 27 if ARM64_VA_BITS=42 | |
177 | default 30 if ARM64_VA_BITS=47 | |
178 | default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES | |
179 | default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES | |
180 | default 33 if ARM64_VA_BITS=48 | |
181 | default 14 if ARM64_64K_PAGES | |
182 | default 16 if ARM64_16K_PAGES | |
183 | default 18 | |
184 | ||
185 | config ARCH_MMAP_RND_COMPAT_BITS_MIN | |
186 | default 7 if ARM64_64K_PAGES | |
187 | default 9 if ARM64_16K_PAGES | |
188 | default 11 | |
189 | ||
190 | config ARCH_MMAP_RND_COMPAT_BITS_MAX | |
191 | default 16 | |
192 | ||
ce816fa8 | 193 | config NO_IOPORT_MAP |
d1e6dc91 | 194 | def_bool y if !PCI |
8c2c3df3 CM |
195 | |
196 | config STACKTRACE_SUPPORT | |
197 | def_bool y | |
198 | ||
bf0c4e04 JVS |
199 | config ILLEGAL_POINTER_VALUE |
200 | hex | |
201 | default 0xdead000000000000 | |
202 | ||
8c2c3df3 CM |
203 | config LOCKDEP_SUPPORT |
204 | def_bool y | |
205 | ||
206 | config TRACE_IRQFLAGS_SUPPORT | |
207 | def_bool y | |
208 | ||
c209f799 | 209 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
210 | def_bool y |
211 | ||
9fb7410f DM |
212 | config GENERIC_BUG |
213 | def_bool y | |
214 | depends on BUG | |
215 | ||
216 | config GENERIC_BUG_RELATIVE_POINTERS | |
217 | def_bool y | |
218 | depends on GENERIC_BUG | |
219 | ||
8c2c3df3 CM |
220 | config GENERIC_HWEIGHT |
221 | def_bool y | |
222 | ||
223 | config GENERIC_CSUM | |
224 | def_bool y | |
225 | ||
226 | config GENERIC_CALIBRATE_DELAY | |
227 | def_bool y | |
228 | ||
19e7640d | 229 | config ZONE_DMA |
8c2c3df3 CM |
230 | def_bool y |
231 | ||
e585513b | 232 | config HAVE_GENERIC_GUP |
29e56940 SC |
233 | def_bool y |
234 | ||
8c2c3df3 CM |
235 | config ARCH_DMA_ADDR_T_64BIT |
236 | def_bool y | |
237 | ||
238 | config NEED_DMA_MAP_STATE | |
239 | def_bool y | |
240 | ||
241 | config NEED_SG_DMA_LENGTH | |
242 | def_bool y | |
243 | ||
4b3dc967 WD |
244 | config SMP |
245 | def_bool y | |
246 | ||
8c2c3df3 CM |
247 | config SWIOTLB |
248 | def_bool y | |
249 | ||
250 | config IOMMU_HELPER | |
251 | def_bool SWIOTLB | |
252 | ||
4cfb3613 AB |
253 | config KERNEL_MODE_NEON |
254 | def_bool y | |
255 | ||
92cc15fc RH |
256 | config FIX_EARLYCON_MEM |
257 | def_bool y | |
258 | ||
9f25e6ad KS |
259 | config PGTABLE_LEVELS |
260 | int | |
21539939 | 261 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad KS |
262 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
263 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
264 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 | |
44eaacf1 SP |
265 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
266 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
9f25e6ad | 267 | |
9842ceae PA |
268 | config ARCH_SUPPORTS_UPROBES |
269 | def_bool y | |
270 | ||
8f360948 AB |
271 | config ARCH_PROC_KCORE_TEXT |
272 | def_bool y | |
273 | ||
8c2c3df3 CM |
274 | source "init/Kconfig" |
275 | ||
276 | source "kernel/Kconfig.freezer" | |
277 | ||
6a377491 | 278 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 CM |
279 | |
280 | menu "Bus support" | |
281 | ||
d1e6dc91 LD |
282 | config PCI |
283 | bool "PCI support" | |
284 | help | |
285 | This feature enables support for PCI bus system. If you say Y | |
286 | here, the kernel will include drivers and infrastructure code | |
287 | to support PCI bus devices. | |
288 | ||
289 | config PCI_DOMAINS | |
290 | def_bool PCI | |
291 | ||
292 | config PCI_DOMAINS_GENERIC | |
293 | def_bool PCI | |
294 | ||
295 | config PCI_SYSCALL | |
296 | def_bool PCI | |
297 | ||
298 | source "drivers/pci/Kconfig" | |
d1e6dc91 | 299 | |
8c2c3df3 CM |
300 | endmenu |
301 | ||
302 | menu "Kernel Features" | |
303 | ||
c0a01b84 AP |
304 | menu "ARM errata workarounds via the alternatives framework" |
305 | ||
306 | config ARM64_ERRATUM_826319 | |
307 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
308 | default y | |
309 | help | |
310 | This option adds an alternative code sequence to work around ARM | |
311 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
312 | AXI master interface and an L2 cache. | |
313 | ||
314 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
315 | and is unable to accept a certain write via this interface, it will | |
316 | not progress on read data presented on the read data channel and the | |
317 | system can deadlock. | |
318 | ||
319 | The workaround promotes data cache clean instructions to | |
320 | data cache clean-and-invalidate. | |
321 | Please note that this does not necessarily enable the workaround, | |
322 | as it depends on the alternative framework, which will only patch | |
323 | the kernel if an affected CPU is detected. | |
324 | ||
325 | If unsure, say Y. | |
326 | ||
327 | config ARM64_ERRATUM_827319 | |
328 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
329 | default y | |
330 | help | |
331 | This option adds an alternative code sequence to work around ARM | |
332 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
333 | master interface and an L2 cache. | |
334 | ||
335 | Under certain conditions this erratum can cause a clean line eviction | |
336 | to occur at the same time as another transaction to the same address | |
337 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
338 | interconnect reorders the two transactions. | |
339 | ||
340 | The workaround promotes data cache clean instructions to | |
341 | data cache clean-and-invalidate. | |
342 | Please note that this does not necessarily enable the workaround, | |
343 | as it depends on the alternative framework, which will only patch | |
344 | the kernel if an affected CPU is detected. | |
345 | ||
346 | If unsure, say Y. | |
347 | ||
348 | config ARM64_ERRATUM_824069 | |
349 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
350 | default y | |
351 | help | |
352 | This option adds an alternative code sequence to work around ARM | |
353 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
354 | to a coherent interconnect. | |
355 | ||
356 | If a Cortex-A53 processor is executing a store or prefetch for | |
357 | write instruction at the same time as a processor in another | |
358 | cluster is executing a cache maintenance operation to the same | |
359 | address, then this erratum might cause a clean cache line to be | |
360 | incorrectly marked as dirty. | |
361 | ||
362 | The workaround promotes data cache clean instructions to | |
363 | data cache clean-and-invalidate. | |
364 | Please note that this option does not necessarily enable the | |
365 | workaround, as it depends on the alternative framework, which will | |
366 | only patch the kernel if an affected CPU is detected. | |
367 | ||
368 | If unsure, say Y. | |
369 | ||
370 | config ARM64_ERRATUM_819472 | |
371 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
372 | default y | |
373 | help | |
374 | This option adds an alternative code sequence to work around ARM | |
375 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
376 | present when it is connected to a coherent interconnect. | |
377 | ||
378 | If the processor is executing a load and store exclusive sequence at | |
379 | the same time as a processor in another cluster is executing a cache | |
380 | maintenance operation to the same address, then this erratum might | |
381 | cause data corruption. | |
382 | ||
383 | The workaround promotes data cache clean instructions to | |
384 | data cache clean-and-invalidate. | |
385 | Please note that this does not necessarily enable the workaround, | |
386 | as it depends on the alternative framework, which will only patch | |
387 | the kernel if an affected CPU is detected. | |
388 | ||
389 | If unsure, say Y. | |
390 | ||
391 | config ARM64_ERRATUM_832075 | |
392 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
393 | default y | |
394 | help | |
395 | This option adds an alternative code sequence to work around ARM | |
396 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
397 | ||
398 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
399 | instructions to Write-Back memory are mixed with Device loads. | |
400 | ||
401 | The workaround is to promote device loads to use Load-Acquire | |
402 | semantics. | |
403 | Please note that this does not necessarily enable the workaround, | |
498cd5c3 MZ |
404 | as it depends on the alternative framework, which will only patch |
405 | the kernel if an affected CPU is detected. | |
406 | ||
407 | If unsure, say Y. | |
408 | ||
409 | config ARM64_ERRATUM_834220 | |
410 | bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" | |
411 | depends on KVM | |
412 | default y | |
413 | help | |
414 | This option adds an alternative code sequence to work around ARM | |
415 | erratum 834220 on Cortex-A57 parts up to r1p2. | |
416 | ||
417 | Affected Cortex-A57 parts might report a Stage 2 translation | |
418 | fault as the result of a Stage 1 fault for load crossing a | |
419 | page boundary when there is a permission or device memory | |
420 | alignment fault at Stage 1 and a translation fault at Stage 2. | |
421 | ||
422 | The workaround is to verify that the Stage 1 translation | |
423 | doesn't generate a fault before handling the Stage 2 fault. | |
424 | Please note that this does not necessarily enable the workaround, | |
c0a01b84 AP |
425 | as it depends on the alternative framework, which will only patch |
426 | the kernel if an affected CPU is detected. | |
427 | ||
428 | If unsure, say Y. | |
429 | ||
905e8c5d WD |
430 | config ARM64_ERRATUM_845719 |
431 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
432 | depends on COMPAT | |
433 | default y | |
434 | help | |
435 | This option adds an alternative code sequence to work around ARM | |
436 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
437 | ||
438 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
439 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
440 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
441 | might return incorrect data. | |
442 | ||
443 | The workaround is to write the contextidr_el1 register on exception | |
444 | return to a 32-bit task. | |
445 | Please note that this does not necessarily enable the workaround, | |
446 | as it depends on the alternative framework, which will only patch | |
447 | the kernel if an affected CPU is detected. | |
448 | ||
449 | If unsure, say Y. | |
450 | ||
df057cc7 WD |
451 | config ARM64_ERRATUM_843419 |
452 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
df057cc7 | 453 | default y |
6ffe9923 | 454 | select ARM64_MODULE_CMODEL_LARGE if MODULES |
df057cc7 | 455 | help |
6ffe9923 WD |
456 | This option links the kernel with '--fix-cortex-a53-843419' and |
457 | builds modules using the large memory model in order to avoid the use | |
458 | of the ADRP instruction, which can cause a subsequent memory access | |
459 | to use an incorrect address on Cortex-A53 parts up to r0p4. | |
df057cc7 WD |
460 | |
461 | If unsure, say Y. | |
462 | ||
94100970 RR |
463 | config CAVIUM_ERRATUM_22375 |
464 | bool "Cavium erratum 22375, 24313" | |
465 | default y | |
466 | help | |
467 | Enable workaround for erratum 22375, 24313. | |
468 | ||
469 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
470 | with small impact affecting only ITS table allocation. | |
471 | ||
472 | erratum 22375: only alloc 8MB table size | |
473 | erratum 24313: ignore memory access type | |
474 | ||
475 | The fixes are in ITS initialization and basically ignore memory access | |
476 | type and table size provided by the TYPER and BASER registers. | |
477 | ||
478 | If unsure, say Y. | |
479 | ||
fbf8f40e GK |
480 | config CAVIUM_ERRATUM_23144 |
481 | bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" | |
482 | depends on NUMA | |
483 | default y | |
484 | help | |
485 | ITS SYNC command hang for cross node io and collections/cpu mapping. | |
486 | ||
487 | If unsure, say Y. | |
488 | ||
6d4e11c5 RR |
489 | config CAVIUM_ERRATUM_23154 |
490 | bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" | |
491 | default y | |
492 | help | |
493 | The gicv3 of ThunderX requires a modified version for | |
494 | reading the IAR status to ensure data synchronization | |
495 | (access to icc_iar1_el1 is not sync'ed before and after). | |
496 | ||
497 | If unsure, say Y. | |
498 | ||
104a0c02 AP |
499 | config CAVIUM_ERRATUM_27456 |
500 | bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" | |
501 | default y | |
502 | help | |
503 | On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI | |
504 | instructions may cause the icache to become corrupted if it | |
505 | contains data for a non-current ASID. The fix is to | |
506 | invalidate the icache when changing the mm context. | |
507 | ||
508 | If unsure, say Y. | |
509 | ||
690a3415 DD |
510 | config CAVIUM_ERRATUM_30115 |
511 | bool "Cavium erratum 30115: Guest may disable interrupts in host" | |
512 | default y | |
513 | help | |
514 | On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through | |
515 | 1.2, and T83 Pass 1.0, KVM guest execution may disable | |
516 | interrupts in host. Trapping both GICv3 group-0 and group-1 | |
517 | accesses sidesteps the issue. | |
518 | ||
519 | If unsure, say Y. | |
520 | ||
38fd94b0 CC |
521 | config QCOM_FALKOR_ERRATUM_1003 |
522 | bool "Falkor E1003: Incorrect translation due to ASID change" | |
523 | default y | |
38fd94b0 CC |
524 | help |
525 | On Falkor v1, an incorrect ASID may be cached in the TLB when ASID | |
7aa99b55 WD |
526 | and BADDR are changed together in TTBRx_EL1. Since we keep the ASID |
527 | in TTBR1_EL1, this situation only occurs in the entry trampoline and | |
528 | then only for entries in the walk cache, since the leaf translation | |
529 | is unchanged. Work around the erratum by invalidating the walk cache | |
530 | entries for the trampoline before entering the kernel proper. | |
38fd94b0 | 531 | |
d9ff80f8 CC |
532 | config QCOM_FALKOR_ERRATUM_1009 |
533 | bool "Falkor E1009: Prematurely complete a DSB after a TLBI" | |
534 | default y | |
535 | help | |
536 | On Falkor v1, the CPU may prematurely complete a DSB following a | |
537 | TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation | |
538 | one more time to fix the issue. | |
539 | ||
540 | If unsure, say Y. | |
541 | ||
90922a2d SD |
542 | config QCOM_QDF2400_ERRATUM_0065 |
543 | bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" | |
544 | default y | |
545 | help | |
546 | On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports | |
547 | ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have | |
548 | been indicated as 16Bytes (0xf), not 8Bytes (0x7). | |
549 | ||
550 | If unsure, say Y. | |
551 | ||
5635c980 SD |
552 | config QCOM_FALKOR_ERRATUM_E1041 |
553 | bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" | |
554 | default y | |
555 | help | |
556 | Falkor CPU may speculatively fetch instructions from an improper | |
557 | memory location when MMU translation is changed from SCTLR_ELn[M]=1 | |
558 | to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. | |
559 | ||
560 | If unsure, say Y. | |
561 | ||
c0a01b84 AP |
562 | endmenu |
563 | ||
564 | ||
e41ceed0 JL |
565 | choice |
566 | prompt "Page size" | |
567 | default ARM64_4K_PAGES | |
568 | help | |
569 | Page size (translation granule) configuration. | |
570 | ||
571 | config ARM64_4K_PAGES | |
572 | bool "4KB" | |
573 | help | |
574 | This feature enables 4KB pages support. | |
575 | ||
44eaacf1 SP |
576 | config ARM64_16K_PAGES |
577 | bool "16KB" | |
578 | help | |
579 | The system will use 16KB pages support. AArch32 emulation | |
580 | requires applications compiled with 16K (or a multiple of 16K) | |
581 | aligned segments. | |
582 | ||
8c2c3df3 | 583 | config ARM64_64K_PAGES |
e41ceed0 | 584 | bool "64KB" |
8c2c3df3 CM |
585 | help |
586 | This feature enables 64KB pages support (4KB by default) | |
587 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
588 | look-up. AArch32 emulation requires applications compiled |
589 | with 64K aligned segments. | |
8c2c3df3 | 590 | |
e41ceed0 JL |
591 | endchoice |
592 | ||
593 | choice | |
594 | prompt "Virtual address space size" | |
595 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
44eaacf1 | 596 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
e41ceed0 JL |
597 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
598 | help | |
599 | Allows choosing one of multiple possible virtual address | |
600 | space sizes. The level of translation table is determined by | |
601 | a combination of page size and virtual address space size. | |
602 | ||
21539939 | 603 | config ARM64_VA_BITS_36 |
56a3f30e | 604 | bool "36-bit" if EXPERT |
21539939 SP |
605 | depends on ARM64_16K_PAGES |
606 | ||
e41ceed0 JL |
607 | config ARM64_VA_BITS_39 |
608 | bool "39-bit" | |
609 | depends on ARM64_4K_PAGES | |
610 | ||
611 | config ARM64_VA_BITS_42 | |
612 | bool "42-bit" | |
613 | depends on ARM64_64K_PAGES | |
614 | ||
44eaacf1 SP |
615 | config ARM64_VA_BITS_47 |
616 | bool "47-bit" | |
617 | depends on ARM64_16K_PAGES | |
618 | ||
c79b954b JL |
619 | config ARM64_VA_BITS_48 |
620 | bool "48-bit" | |
c79b954b | 621 | |
e41ceed0 JL |
622 | endchoice |
623 | ||
624 | config ARM64_VA_BITS | |
625 | int | |
21539939 | 626 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
627 | default 39 if ARM64_VA_BITS_39 |
628 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 629 | default 47 if ARM64_VA_BITS_47 |
c79b954b | 630 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 631 | |
a872013d WD |
632 | config CPU_BIG_ENDIAN |
633 | bool "Build big-endian kernel" | |
634 | help | |
635 | Say Y if you plan on running a kernel in big-endian mode. | |
636 | ||
f6e763b9 MB |
637 | config SCHED_MC |
638 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
639 | help |
640 | Multi-core scheduler support improves the CPU scheduler's decision | |
641 | making when dealing with multi-core CPU chips at a cost of slightly | |
642 | increased overhead in some places. If unsure say N here. | |
643 | ||
644 | config SCHED_SMT | |
645 | bool "SMT scheduler support" | |
f6e763b9 MB |
646 | help |
647 | Improves the CPU scheduler's decision making when dealing with | |
648 | MultiThreading at a cost of slightly increased overhead in some | |
649 | places. If unsure say N here. | |
650 | ||
8c2c3df3 | 651 | config NR_CPUS |
62aa9655 GK |
652 | int "Maximum number of CPUs (2-4096)" |
653 | range 2 4096 | |
15942853 | 654 | # These have to remain sorted largest to smallest |
e3672649 | 655 | default "64" |
8c2c3df3 | 656 | |
9327e2c6 MR |
657 | config HOTPLUG_CPU |
658 | bool "Support for hot-pluggable CPUs" | |
217d453d | 659 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
660 | help |
661 | Say Y here to experiment with turning CPUs off and on. CPUs | |
662 | can be controlled through /sys/devices/system/cpu. | |
663 | ||
1a2db300 GK |
664 | # Common NUMA Features |
665 | config NUMA | |
666 | bool "Numa Memory Allocation and Scheduler Support" | |
0c2a6cce KW |
667 | select ACPI_NUMA if ACPI |
668 | select OF_NUMA | |
1a2db300 GK |
669 | help |
670 | Enable NUMA (Non Uniform Memory Access) support. | |
671 | ||
672 | The kernel will try to allocate memory used by a CPU on the | |
673 | local memory of the CPU and add some more | |
674 | NUMA awareness to the kernel. | |
675 | ||
676 | config NODES_SHIFT | |
677 | int "Maximum NUMA Nodes (as a power of 2)" | |
678 | range 1 10 | |
679 | default "2" | |
680 | depends on NEED_MULTIPLE_NODES | |
681 | help | |
682 | Specify the maximum number of NUMA Nodes available on the target | |
683 | system. Increases memory reserved to accommodate various tables. | |
684 | ||
685 | config USE_PERCPU_NUMA_NODE_ID | |
686 | def_bool y | |
687 | depends on NUMA | |
688 | ||
7af3a0a9 ZL |
689 | config HAVE_SETUP_PER_CPU_AREA |
690 | def_bool y | |
691 | depends on NUMA | |
692 | ||
693 | config NEED_PER_CPU_EMBED_FIRST_CHUNK | |
694 | def_bool y | |
695 | depends on NUMA | |
696 | ||
6d526ee2 AB |
697 | config HOLES_IN_ZONE |
698 | def_bool y | |
699 | depends on NUMA | |
700 | ||
8c2c3df3 | 701 | source kernel/Kconfig.preempt |
f90df5e2 | 702 | source kernel/Kconfig.hz |
8c2c3df3 | 703 | |
83863f25 LA |
704 | config ARCH_SUPPORTS_DEBUG_PAGEALLOC |
705 | def_bool y | |
706 | ||
8c2c3df3 CM |
707 | config ARCH_HAS_HOLES_MEMORYMODEL |
708 | def_bool y if SPARSEMEM | |
709 | ||
710 | config ARCH_SPARSEMEM_ENABLE | |
711 | def_bool y | |
712 | select SPARSEMEM_VMEMMAP_ENABLE | |
713 | ||
714 | config ARCH_SPARSEMEM_DEFAULT | |
715 | def_bool ARCH_SPARSEMEM_ENABLE | |
716 | ||
717 | config ARCH_SELECT_MEMORY_MODEL | |
718 | def_bool ARCH_SPARSEMEM_ENABLE | |
719 | ||
720 | config HAVE_ARCH_PFN_VALID | |
721 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
722 | ||
723 | config HW_PERF_EVENTS | |
6475b2d8 MR |
724 | def_bool y |
725 | depends on ARM_PMU | |
8c2c3df3 | 726 | |
084bd298 SC |
727 | config SYS_SUPPORTS_HUGETLBFS |
728 | def_bool y | |
729 | ||
084bd298 | 730 | config ARCH_WANT_HUGE_PMD_SHARE |
21539939 | 731 | def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
084bd298 | 732 | |
a41dc0e8 CM |
733 | config ARCH_HAS_CACHE_LINE_SIZE |
734 | def_bool y | |
735 | ||
8c2c3df3 CM |
736 | source "mm/Kconfig" |
737 | ||
a1ae65b2 AT |
738 | config SECCOMP |
739 | bool "Enable seccomp to safely compute untrusted bytecode" | |
740 | ---help--- | |
741 | This kernel feature is useful for number crunching applications | |
742 | that may need to compute untrusted bytecode during their | |
743 | execution. By using pipes or other transports made available to | |
744 | the process as file descriptors supporting the read/write | |
745 | syscalls, it's possible to isolate those applications in | |
746 | their own address space using seccomp. Once seccomp is | |
747 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
748 | and the task is only allowed to execute a few safe syscalls | |
749 | defined by each seccomp mode. | |
750 | ||
dfd57bc3 SS |
751 | config PARAVIRT |
752 | bool "Enable paravirtualization code" | |
753 | help | |
754 | This changes the kernel so it can modify itself when it is run | |
755 | under a hypervisor, potentially improving performance significantly | |
756 | over full virtualization. | |
757 | ||
758 | config PARAVIRT_TIME_ACCOUNTING | |
759 | bool "Paravirtual steal time accounting" | |
760 | select PARAVIRT | |
761 | default n | |
762 | help | |
763 | Select this option to enable fine granularity task steal time | |
764 | accounting. Time spent executing other tasks in parallel with | |
765 | the current vCPU is discounted from the vCPU power. To account for | |
766 | that, there can be a small performance impact. | |
767 | ||
768 | If in doubt, say N here. | |
769 | ||
d28f6df1 GL |
770 | config KEXEC |
771 | depends on PM_SLEEP_SMP | |
772 | select KEXEC_CORE | |
773 | bool "kexec system call" | |
774 | ---help--- | |
775 | kexec is a system call that implements the ability to shutdown your | |
776 | current kernel, and to start another kernel. It is like a reboot | |
777 | but it is independent of the system firmware. And like a reboot | |
778 | you can start any kernel with it, not just Linux. | |
779 | ||
e62aaeac AT |
780 | config CRASH_DUMP |
781 | bool "Build kdump crash kernel" | |
782 | help | |
783 | Generate crash dump after being started by kexec. This should | |
784 | be normally only set in special crash dump kernels which are | |
785 | loaded in the main kernel with kexec-tools into a specially | |
786 | reserved region and then later executed after a crash by | |
787 | kdump/kexec. | |
788 | ||
789 | For more details see Documentation/kdump/kdump.txt | |
790 | ||
aa42aa13 SS |
791 | config XEN_DOM0 |
792 | def_bool y | |
793 | depends on XEN | |
794 | ||
795 | config XEN | |
c2ba1f7d | 796 | bool "Xen guest support on ARM64" |
aa42aa13 | 797 | depends on ARM64 && OF |
83862ccf | 798 | select SWIOTLB_XEN |
dfd57bc3 | 799 | select PARAVIRT |
aa42aa13 SS |
800 | help |
801 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
802 | ||
d03bb145 SC |
803 | config FORCE_MAX_ZONEORDER |
804 | int | |
805 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
e8c9456c | 806 | default "13" if (ARCH_THUNDER && ARM64_4K_PAGES) |
44eaacf1 | 807 | default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) |
d03bb145 | 808 | default "11" |
44eaacf1 SP |
809 | help |
810 | The kernel memory allocator divides physically contiguous memory | |
811 | blocks into "zones", where each zone is a power of two number of | |
812 | pages. This option selects the largest power of two that the kernel | |
813 | keeps in the memory allocator. If you need to allocate very large | |
814 | blocks of physically contiguous memory, then you may need to | |
815 | increase this value. | |
816 | ||
817 | This config option is actually maximum order plus one. For example, | |
818 | a value of 11 means that the largest free memory block is 2^10 pages. | |
819 | ||
820 | We make sure that we can allocate upto a HugePage size for each configuration. | |
821 | Hence we have : | |
822 | MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 | |
823 | ||
824 | However for 4K, we choose a higher default value, 11 as opposed to 10, giving us | |
825 | 4M allocations matching the default size used by generic code. | |
d03bb145 | 826 | |
1b907f46 WD |
827 | menuconfig ARMV8_DEPRECATED |
828 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
829 | depends on COMPAT | |
830 | help | |
831 | Legacy software support may require certain instructions | |
832 | that have been deprecated or obsoleted in the architecture. | |
833 | ||
834 | Enable this config to enable selective emulation of these | |
835 | features. | |
836 | ||
837 | If unsure, say Y | |
838 | ||
839 | if ARMV8_DEPRECATED | |
840 | ||
841 | config SWP_EMULATION | |
842 | bool "Emulate SWP/SWPB instructions" | |
843 | help | |
844 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
845 | they are always undefined. Say Y here to enable software | |
846 | emulation of these instructions for userspace using LDXR/STXR. | |
847 | ||
848 | In some older versions of glibc [<=2.8] SWP is used during futex | |
849 | trylock() operations with the assumption that the code will not | |
850 | be preempted. This invalid assumption may be more likely to fail | |
851 | with SWP emulation enabled, leading to deadlock of the user | |
852 | application. | |
853 | ||
854 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
855 | on an external transaction monitoring block called a global | |
856 | monitor to maintain update atomicity. If your system does not | |
857 | implement a global monitor, this option can cause programs that | |
858 | perform SWP operations to uncached memory to deadlock. | |
859 | ||
860 | If unsure, say Y | |
861 | ||
862 | config CP15_BARRIER_EMULATION | |
863 | bool "Emulate CP15 Barrier instructions" | |
864 | help | |
865 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
866 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
867 | strongly recommended to use the ISB, DSB, and DMB | |
868 | instructions instead. | |
869 | ||
870 | Say Y here to enable software emulation of these | |
871 | instructions for AArch32 userspace code. When this option is | |
872 | enabled, CP15 barrier usage is traced which can help | |
873 | identify software that needs updating. | |
874 | ||
875 | If unsure, say Y | |
876 | ||
2d888f48 SP |
877 | config SETEND_EMULATION |
878 | bool "Emulate SETEND instruction" | |
879 | help | |
880 | The SETEND instruction alters the data-endianness of the | |
881 | AArch32 EL0, and is deprecated in ARMv8. | |
882 | ||
883 | Say Y here to enable software emulation of the instruction | |
884 | for AArch32 userspace code. | |
885 | ||
886 | Note: All the cpus on the system must have mixed endian support at EL0 | |
887 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
888 | endian - is hotplugged in after this feature has been enabled, there could | |
889 | be unexpected results in the applications. | |
890 | ||
891 | If unsure, say Y | |
1b907f46 WD |
892 | endif |
893 | ||
ba42822a CM |
894 | config ARM64_SW_TTBR0_PAN |
895 | bool "Emulate Privileged Access Never using TTBR0_EL1 switching" | |
896 | help | |
897 | Enabling this option prevents the kernel from accessing | |
898 | user-space memory directly by pointing TTBR0_EL1 to a reserved | |
899 | zeroed area and reserved ASID. The user access routines | |
900 | restore the valid TTBR0_EL1 temporarily. | |
901 | ||
0e4a0709 WD |
902 | menu "ARMv8.1 architectural features" |
903 | ||
904 | config ARM64_HW_AFDBM | |
905 | bool "Support for hardware updates of the Access and Dirty page flags" | |
906 | default y | |
907 | help | |
908 | The ARMv8.1 architecture extensions introduce support for | |
909 | hardware updates of the access and dirty information in page | |
910 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
911 | capable processors, accesses to pages with PTE_AF cleared will | |
912 | set this bit instead of raising an access flag fault. | |
913 | Similarly, writes to read-only pages with the DBM bit set will | |
914 | clear the read-only bit (AP[2]) instead of raising a | |
915 | permission fault. | |
916 | ||
917 | Kernels built with this configuration option enabled continue | |
918 | to work on pre-ARMv8.1 hardware and the performance impact is | |
919 | minimal. If unsure, say Y. | |
920 | ||
921 | config ARM64_PAN | |
922 | bool "Enable support for Privileged Access Never (PAN)" | |
923 | default y | |
924 | help | |
925 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) | |
926 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
927 | memory directly. | |
928 | ||
929 | Choosing this option will cause any unprotected (not using | |
930 | copy_to_user et al) memory access to fail with a permission fault. | |
931 | ||
932 | The feature is detected at runtime, and will remain as a 'nop' | |
933 | instruction if the cpu does not implement the feature. | |
934 | ||
935 | config ARM64_LSE_ATOMICS | |
936 | bool "Atomic instructions" | |
937 | help | |
938 | As part of the Large System Extensions, ARMv8.1 introduces new | |
939 | atomic instructions that are designed specifically to scale in | |
940 | very large systems. | |
941 | ||
942 | Say Y here to make use of these instructions for the in-kernel | |
943 | atomic routines. This incurs a small overhead on CPUs that do | |
944 | not support these instructions and requires the kernel to be | |
945 | built with binutils >= 2.25. | |
946 | ||
1f364c8c MZ |
947 | config ARM64_VHE |
948 | bool "Enable support for Virtualization Host Extensions (VHE)" | |
949 | default y | |
950 | help | |
951 | Virtualization Host Extensions (VHE) allow the kernel to run | |
952 | directly at EL2 (instead of EL1) on processors that support | |
953 | it. This leads to better performance for KVM, as they reduce | |
954 | the cost of the world switch. | |
955 | ||
956 | Selecting this option allows the VHE feature to be detected | |
957 | at runtime, and does not affect processors that do not | |
958 | implement this feature. | |
959 | ||
0e4a0709 WD |
960 | endmenu |
961 | ||
f993318b WD |
962 | menu "ARMv8.2 architectural features" |
963 | ||
57f4959b JM |
964 | config ARM64_UAO |
965 | bool "Enable support for User Access Override (UAO)" | |
966 | default y | |
967 | help | |
968 | User Access Override (UAO; part of the ARMv8.2 Extensions) | |
969 | causes the 'unprivileged' variant of the load/store instructions to | |
970 | be overriden to be privileged. | |
971 | ||
972 | This option changes get_user() and friends to use the 'unprivileged' | |
973 | variant of the load/store instructions. This ensures that user-space | |
974 | really did have access to the supplied memory. When addr_limit is | |
975 | set to kernel memory the UAO bit will be set, allowing privileged | |
976 | access to kernel memory. | |
977 | ||
978 | Choosing this option will cause copy_to_user() et al to use user-space | |
979 | memory permissions. | |
980 | ||
981 | The feature is detected at runtime, the kernel will use the | |
982 | regular load/store instructions if the cpu does not implement the | |
983 | feature. | |
984 | ||
27119a3a RM |
985 | config ARM64_PMEM |
986 | bool "Enable support for persistent memory" | |
987 | select ARCH_HAS_PMEM_API | |
3a7a324e | 988 | select ARCH_HAS_UACCESS_FLUSHCACHE |
27119a3a RM |
989 | help |
990 | Say Y to enable support for the persistent memory API based on the | |
991 | ARMv8.2 DCPoP feature. | |
992 | ||
993 | The feature is detected at runtime, and the kernel will use DC CVAC | |
994 | operations if DC CVAP is not supported (following the behaviour of | |
995 | DC CVAP itself if the system does not define a point of persistence). | |
996 | ||
f993318b WD |
997 | endmenu |
998 | ||
fd045f6c AB |
999 | config ARM64_MODULE_CMODEL_LARGE |
1000 | bool | |
1001 | ||
1002 | config ARM64_MODULE_PLTS | |
1003 | bool | |
1004 | select ARM64_MODULE_CMODEL_LARGE | |
1005 | select HAVE_MOD_ARCH_SPECIFIC | |
1006 | ||
1e48ef7f AB |
1007 | config RELOCATABLE |
1008 | bool | |
1009 | help | |
1010 | This builds the kernel as a Position Independent Executable (PIE), | |
1011 | which retains all relocation metadata required to relocate the | |
1012 | kernel binary at runtime to a different virtual address than the | |
1013 | address it was linked at. | |
1014 | Since AArch64 uses the RELA relocation format, this requires a | |
1015 | relocation pass at runtime even if the kernel is loaded at the | |
1016 | same address it was linked at. | |
1017 | ||
f80fb3a3 AB |
1018 | config RANDOMIZE_BASE |
1019 | bool "Randomize the address of the kernel image" | |
b9c220b5 | 1020 | select ARM64_MODULE_PLTS if MODULES |
f80fb3a3 AB |
1021 | select RELOCATABLE |
1022 | help | |
1023 | Randomizes the virtual address at which the kernel image is | |
1024 | loaded, as a security feature that deters exploit attempts | |
1025 | relying on knowledge of the location of kernel internals. | |
1026 | ||
1027 | It is the bootloader's job to provide entropy, by passing a | |
1028 | random u64 value in /chosen/kaslr-seed at kernel entry. | |
1029 | ||
2b5fe07a AB |
1030 | When booting via the UEFI stub, it will invoke the firmware's |
1031 | EFI_RNG_PROTOCOL implementation (if available) to supply entropy | |
1032 | to the kernel proper. In addition, it will randomise the physical | |
1033 | location of the kernel Image as well. | |
1034 | ||
f80fb3a3 AB |
1035 | If unsure, say N. |
1036 | ||
1037 | config RANDOMIZE_MODULE_REGION_FULL | |
1038 | bool "Randomize the module region independently from the core kernel" | |
e71a4e1b | 1039 | depends on RANDOMIZE_BASE |
f80fb3a3 AB |
1040 | default y |
1041 | help | |
1042 | Randomizes the location of the module region without considering the | |
1043 | location of the core kernel. This way, it is impossible for modules | |
1044 | to leak information about the location of core kernel data structures | |
1045 | but it does imply that function calls between modules and the core | |
1046 | kernel will need to be resolved via veneers in the module PLT. | |
1047 | ||
1048 | When this option is not set, the module region will be randomized over | |
1049 | a limited range that contains the [_stext, _etext] interval of the | |
1050 | core kernel, so branch relocations are always in range. | |
1051 | ||
8c2c3df3 CM |
1052 | endmenu |
1053 | ||
1054 | menu "Boot options" | |
1055 | ||
5e89c55e LP |
1056 | config ARM64_ACPI_PARKING_PROTOCOL |
1057 | bool "Enable support for the ARM64 ACPI parking protocol" | |
1058 | depends on ACPI | |
1059 | help | |
1060 | Enable support for the ARM64 ACPI parking protocol. If disabled | |
1061 | the kernel will not allow booting through the ARM64 ACPI parking | |
1062 | protocol even if the corresponding data is present in the ACPI | |
1063 | MADT table. | |
1064 | ||
8c2c3df3 CM |
1065 | config CMDLINE |
1066 | string "Default kernel command string" | |
1067 | default "" | |
1068 | help | |
1069 | Provide a set of default command-line options at build time by | |
1070 | entering them here. As a minimum, you should specify the the | |
1071 | root device (e.g. root=/dev/nfs). | |
1072 | ||
1073 | config CMDLINE_FORCE | |
1074 | bool "Always use the default kernel command string" | |
1075 | help | |
1076 | Always use the default kernel command string, even if the boot | |
1077 | loader passes other arguments to the kernel. | |
1078 | This is useful if you cannot or don't want to change the | |
1079 | command-line options your boot loader passes to the kernel. | |
1080 | ||
f4f75ad5 AB |
1081 | config EFI_STUB |
1082 | bool | |
1083 | ||
f84d0275 MS |
1084 | config EFI |
1085 | bool "UEFI runtime support" | |
1086 | depends on OF && !CPU_BIG_ENDIAN | |
1087 | select LIBFDT | |
1088 | select UCS2_STRING | |
1089 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 1090 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
1091 | select EFI_STUB |
1092 | select EFI_ARMSTUB | |
f84d0275 MS |
1093 | default y |
1094 | help | |
1095 | This option provides support for runtime services provided | |
1096 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
1097 | clock, and platform reset). A UEFI stub is also provided to |
1098 | allow the kernel to be booted as an EFI application. This | |
1099 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 1100 | |
d1ae8c00 YL |
1101 | config DMI |
1102 | bool "Enable support for SMBIOS (DMI) tables" | |
1103 | depends on EFI | |
1104 | default y | |
1105 | help | |
1106 | This enables SMBIOS/DMI feature for systems. | |
1107 | ||
1108 | This option is only useful on systems that have UEFI firmware. | |
1109 | However, even with this option, the resultant kernel should | |
1110 | continue to boot on existing non-UEFI platforms. | |
1111 | ||
8c2c3df3 CM |
1112 | endmenu |
1113 | ||
1114 | menu "Userspace binary formats" | |
1115 | ||
1116 | source "fs/Kconfig.binfmt" | |
1117 | ||
1118 | config COMPAT | |
1119 | bool "Kernel support for 32-bit EL0" | |
755e70b7 | 1120 | depends on ARM64_4K_PAGES || EXPERT |
2e449048 | 1121 | select COMPAT_BINFMT_ELF if BINFMT_ELF |
af1839eb | 1122 | select HAVE_UID16 |
84b9e9b4 | 1123 | select OLD_SIGSUSPEND3 |
51682036 | 1124 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
1125 | help |
1126 | This option enables support for a 32-bit EL0 running under a 64-bit | |
1127 | kernel at EL1. AArch32-specific components such as system calls, | |
1128 | the user helper functions, VFP support and the ptrace interface are | |
1129 | handled appropriately by the kernel. | |
1130 | ||
44eaacf1 SP |
1131 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware |
1132 | that you will only be able to execute AArch32 binaries that were compiled | |
1133 | with page size aligned segments. | |
a8fcd8b1 | 1134 | |
8c2c3df3 CM |
1135 | If you want to execute 32-bit userspace applications, say Y. |
1136 | ||
1137 | config SYSVIPC_COMPAT | |
1138 | def_bool y | |
1139 | depends on COMPAT && SYSVIPC | |
1140 | ||
1141 | endmenu | |
1142 | ||
166936ba LP |
1143 | menu "Power management options" |
1144 | ||
1145 | source "kernel/power/Kconfig" | |
1146 | ||
82869ac5 JM |
1147 | config ARCH_HIBERNATION_POSSIBLE |
1148 | def_bool y | |
1149 | depends on CPU_PM | |
1150 | ||
1151 | config ARCH_HIBERNATION_HEADER | |
1152 | def_bool y | |
1153 | depends on HIBERNATION | |
1154 | ||
166936ba LP |
1155 | config ARCH_SUSPEND_POSSIBLE |
1156 | def_bool y | |
1157 | ||
166936ba LP |
1158 | endmenu |
1159 | ||
1307220d LP |
1160 | menu "CPU Power Management" |
1161 | ||
1162 | source "drivers/cpuidle/Kconfig" | |
1163 | ||
52e7e816 RH |
1164 | source "drivers/cpufreq/Kconfig" |
1165 | ||
1166 | endmenu | |
1167 | ||
8c2c3df3 CM |
1168 | source "net/Kconfig" |
1169 | ||
1170 | source "drivers/Kconfig" | |
1171 | ||
fef4fb4a LO |
1172 | source "ubuntu/Kconfig" |
1173 | ||
f84d0275 MS |
1174 | source "drivers/firmware/Kconfig" |
1175 | ||
b6a02173 GG |
1176 | source "drivers/acpi/Kconfig" |
1177 | ||
8c2c3df3 CM |
1178 | source "fs/Kconfig" |
1179 | ||
c3eb5b14 MZ |
1180 | source "arch/arm64/kvm/Kconfig" |
1181 | ||
8c2c3df3 CM |
1182 | source "arch/arm64/Kconfig.debug" |
1183 | ||
1184 | source "security/Kconfig" | |
1185 | ||
1186 | source "crypto/Kconfig" | |
2c98833a AB |
1187 | if CRYPTO |
1188 | source "arch/arm64/crypto/Kconfig" | |
1189 | endif | |
8c2c3df3 CM |
1190 | |
1191 | source "lib/Kconfig" |