[mirror_ubuntu-artful-kernel.git] / arch / arm64 / boot / dts / arm / juno-r2.dts

/*
 * ARM Ltd. Juno Platform
 *
 * Copyright (c) 2015 ARM Ltd.
 *
 * This file is licensed under a dual GPLv2 or BSD license.
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "ARM Juno development board (r2)";
	compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &soc_uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&A72_0>;
				};
				core1 {
					cpu = <&A72_1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&A53_0>;
				};
				core1 {
					cpu = <&A53_1>;
				};
				core2 {
					cpu = <&A53_2>;
				};
				core3 {
					cpu = <&A53_3>;
				};
			};
		};

		idle-states {
			entry-method = "arm,psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				local-timer-stop;
				entry-latency-us = <300>;
				exit-latency-us = <1200>;
				min-residency-us = <2000>;
			};

			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x1010000>;
				local-timer-stop;
				entry-latency-us = <400>;
				exit-latency-us = <1200>;
				min-residency-us = <2500>;
			};
		};

		A72_0: cpu@0 {
			compatible = "arm,cortex-a72","arm,armv8";
			reg = <0x0 0x0>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&A72_L2>;
			clocks = <&scpi_dvfs 0>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <1024>;
		};

		A72_1: cpu@1 {
			compatible = "arm,cortex-a72","arm,armv8";
			reg = <0x0 0x1>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&A72_L2>;
			clocks = <&scpi_dvfs 0>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <1024>;
		};

		A53_0: cpu@100 {
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x100>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <485>;
		};

		A53_1: cpu@101 {
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x101>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <485>;
		};

		A53_2: cpu@102 {
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x102>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <485>;
		};

		A53_3: cpu@103 {
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x0 0x103>;
			device_type = "cpu";
			enable-method = "psci";
			next-level-cache = <&A53_L2>;
			clocks = <&scpi_dvfs 1>;
			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
			capacity-dmips-mhz = <485>;
		};

		A72_L2: l2-cache0 {
			compatible = "cache";
		};

		A53_L2: l2-cache1 {
			compatible = "cache";
		};
	};

	pmu_a72 {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A72_0>,
				     <&A72_1>;
	};

	pmu_a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A53_0>,
				     <&A53_1>,
				     <&A53_2>,
				     <&A53_3>;
	};

	#include "juno-base.dtsi"
};

&memtimer {
	status = "okay";
};

&pcie_ctlr {
	status = "okay";
};

&etm0 {
	cpu = <&A72_0>;
};

&etm1 {
	cpu = <&A72_1>;
};

&etm2 {
	cpu = <&A53_0>;
};

&etm3 {
	cpu = <&A53_1>;
};

&etm4 {
	cpu = <&A53_2>;
};

&etm5 {
	cpu = <&A53_3>;
};

&big_cluster_thermal_zone {
	status = "okay";
};

&little_cluster_thermal_zone {
	status = "okay";
};

&gpu0_thermal_zone {
	status = "okay";
};

&gpu1_thermal_zone {
	status = "okay";
};
Commit	Line	Data
e6d7f6dc SH	1	/*
	2	* ARM Ltd. Juno Platform
	3	*
	4	* Copyright (c) 2015 ARM Ltd.
	5	*
	6	* This file is licensed under a dual GPLv2 or BSD license.
	7	*/
	8
	9	/dts-v1/;
	10
	11	#include <dt-bindings/interrupt-controller/arm-gic.h>
	12
	13	/ {
	14	model = "ARM Juno development board (r2)";
	15	compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
	16	interrupt-parent = <&gic>;
	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19
	20	aliases {
	21	serial0 = &soc_uart0;
	22	};
	23
	24	chosen {
	25	stdout-path = "serial0:115200n8";
	26	};
	27
	28	psci {
	29	compatible = "arm,psci-0.2";
	30	method = "smc";
	31	};
	32
	33	cpus {
	34	#address-cells = <2>;
	35	#size-cells = <0>;
	36
	37	cpu-map {
	38	cluster0 {
	39	core0 {
	40	cpu = <&A72_0>;
	41	};
	42	core1 {
	43	cpu = <&A72_1>;
	44	};
	45	};
	46
	47	cluster1 {
	48	core0 {
	49	cpu = <&A53_0>;
	50	};
	51	core1 {
	52	cpu = <&A53_1>;
	53	};
	54	core2 {
	55	cpu = <&A53_2>;
	56	};
	57	core3 {
	58	cpu = <&A53_3>;
	59	};
	60	};
	61	};
	62
	63	idle-states {
	64	entry-method = "arm,psci";
65
66	CPU_SLEEP_0: cpu-sleep-0 {
67	compatible = "arm,idle-state";
68	arm,psci-suspend-param = <0x0010000>;
69	local-timer-stop;
70	entry-latency-us = <300>;
71	exit-latency-us = <1200>;
72	min-residency-us = <2000>;
73	};
74
75	CLUSTER_SLEEP_0: cluster-sleep-0 {
76	compatible = "arm,idle-state";
77	arm,psci-suspend-param = <0x1010000>;
78	local-timer-stop;
909e481e	79	entry-latency-us = <400>;
e6d7f6dc SH	80	exit-latency-us = <1200>;
	81	min-residency-us = <2500>;
	82	};
	83	};
	84
	85	A72_0: cpu@0 {
	86	compatible = "arm,cortex-a72","arm,armv8";
	87	reg = <0x0 0x0>;
	88	device_type = "cpu";
	89	enable-method = "psci";
	90	next-level-cache = <&A72_L2>;
	91	clocks = <&scpi_dvfs 0>;
	92	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
c1ab65b2	93	capacity-dmips-mhz = <1024>;
e6d7f6dc SH	94	};
	95
	96	A72_1: cpu@1 {
	97	compatible = "arm,cortex-a72","arm,armv8";
	98	reg = <0x0 0x1>;
	99	device_type = "cpu";
	100	enable-method = "psci";
	101	next-level-cache = <&A72_L2>;
	102	clocks = <&scpi_dvfs 0>;
	103	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
c1ab65b2	104	capacity-dmips-mhz = <1024>;
e6d7f6dc SH	105	};
	106
	107	A53_0: cpu@100 {
	108	compatible = "arm,cortex-a53","arm,armv8";
	109	reg = <0x0 0x100>;
	110	device_type = "cpu";
	111	enable-method = "psci";
	112	next-level-cache = <&A53_L2>;
	113	clocks = <&scpi_dvfs 1>;
	114	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
c1ab65b2	115	capacity-dmips-mhz = <485>;
e6d7f6dc SH	116	};
	117
	118	A53_1: cpu@101 {
	119	compatible = "arm,cortex-a53","arm,armv8";
	120	reg = <0x0 0x101>;
	121	device_type = "cpu";
	122	enable-method = "psci";
	123	next-level-cache = <&A53_L2>;
	124	clocks = <&scpi_dvfs 1>;
	125	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
c1ab65b2	126	capacity-dmips-mhz = <485>;
e6d7f6dc SH	127	};
	128
	129	A53_2: cpu@102 {
	130	compatible = "arm,cortex-a53","arm,armv8";
	131	reg = <0x0 0x102>;
	132	device_type = "cpu";
	133	enable-method = "psci";
	134	next-level-cache = <&A53_L2>;
	135	clocks = <&scpi_dvfs 1>;
	136	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
c1ab65b2	137	capacity-dmips-mhz = <485>;
e6d7f6dc SH	138	};
	139
	140	A53_3: cpu@103 {
	141	compatible = "arm,cortex-a53","arm,armv8";
	142	reg = <0x0 0x103>;
	143	device_type = "cpu";
	144	enable-method = "psci";
	145	next-level-cache = <&A53_L2>;
	146	clocks = <&scpi_dvfs 1>;
	147	cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
c1ab65b2	148	capacity-dmips-mhz = <485>;
e6d7f6dc SH	149	};
	150
	151	A72_L2: l2-cache0 {
	152	compatible = "cache";
	153	};
	154
	155	A53_L2: l2-cache1 {
	156	compatible = "cache";
	157	};
	158	};
	159
	160	pmu_a72 {
	161	compatible = "arm,cortex-a72-pmu";
	162	interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
	163	<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
	164	interrupt-affinity = <&A72_0>,
	165	<&A72_1>;
	166	};
	167
	168	pmu_a53 {
	169	compatible = "arm,cortex-a53-pmu";
	170	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
	171	<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	172	<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
	173	<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	174	interrupt-affinity = <&A53_0>,
	175	<&A53_1>,
	176	<&A53_2>,
	177	<&A53_3>;
	178	};
	179
	180	#include "juno-base.dtsi"
	181	};
	182
	183	&memtimer {
	184	status = "okay";
	185	};
	186
	187	&pcie_ctlr {
	188	status = "okay";
	189	};
3e287cf6 SH	190
	191	&etm0 {
	192	cpu = <&A72_0>;
	193	};
	194
	195	&etm1 {
	196	cpu = <&A72_1>;
	197	};
	198
	199	&etm2 {
	200	cpu = <&A53_0>;
	201	};
	202
	203	&etm3 {
	204	cpu = <&A53_1>;
	205	};
	206
	207	&etm4 {
	208	cpu = <&A53_2>;
	209	};
	210
	211	&etm5 {
	212	cpu = <&A53_3>;
	213	};
f7b636a8 JM	214
	215	&big_cluster_thermal_zone {
	216	status = "okay";
	217	};
	218
	219	&little_cluster_thermal_zone {
	220	status = "okay";
	221	};
	222
	223	&gpu0_thermal_zone {
	224	status = "okay";
	225	};
	226
	227	&gpu1_thermal_zone {
	228	status = "okay";
	229	};