projects / mirror_ubuntu-hirsute-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 60378f1a VNKG |
1 | // SPDX-License-Identifier: BSD-3-Clause |
| 2 | /* | |
| 3 | * Copyright (c) 2020, The Linux Foundation. All rights reserved. | |
| 4 | */ | |
| 5 | ||
| 6 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| b7e2fba0 | 7 | #include <dt-bindings/clock/qcom,gcc-sm8250.h> |
| 0e6aa9db | 8 | #include <dt-bindings/clock/qcom,gpucc-sm8250.h> |
| 60378f1a | 9 | #include <dt-bindings/clock/qcom,rpmh.h> |
| 79a595bb | 10 | #include <dt-bindings/interconnect/qcom,osm-l3.h> |
| e5361e75 | 11 | #include <dt-bindings/mailbox/qcom-ipcc.h> |
| 087d537a | 12 | #include <dt-bindings/power/qcom-aoss-qmp.h> |
| b6f78e27 | 13 | #include <dt-bindings/power/qcom-rpmpd.h> |
| 60378f1a | 14 | #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
| bac12f25 | 15 | #include <dt-bindings/thermal/thermal.h> |
| 60378f1a VNKG |
16 | |
| 17 | / { | |
| 18 | interrupt-parent = <&intc>; | |
| 19 | ||
| 20 | #address-cells = <2>; | |
| 21 | #size-cells = <2>; | |
| 22 | ||
| e5813b15 DB |
23 | aliases { |
| 24 | i2c0 = &i2c0; | |
| 25 | i2c1 = &i2c1; | |
| 26 | i2c2 = &i2c2; | |
| 27 | i2c3 = &i2c3; | |
| 28 | i2c4 = &i2c4; | |
| 29 | i2c5 = &i2c5; | |
| 30 | i2c6 = &i2c6; | |
| 31 | i2c7 = &i2c7; | |
| 32 | i2c8 = &i2c8; | |
| 33 | i2c9 = &i2c9; | |
| 34 | i2c10 = &i2c10; | |
| 35 | i2c11 = &i2c11; | |
| 36 | i2c12 = &i2c12; | |
| 37 | i2c13 = &i2c13; | |
| 38 | i2c14 = &i2c14; | |
| 39 | i2c15 = &i2c15; | |
| 40 | i2c16 = &i2c16; | |
| 41 | i2c17 = &i2c17; | |
| 42 | i2c18 = &i2c18; | |
| 43 | i2c19 = &i2c19; | |
| 44 | spi0 = &spi0; | |
| 45 | spi1 = &spi1; | |
| 46 | spi2 = &spi2; | |
| 47 | spi3 = &spi3; | |
| 48 | spi4 = &spi4; | |
| 49 | spi5 = &spi5; | |
| 50 | spi6 = &spi6; | |
| 51 | spi7 = &spi7; | |
| 52 | spi8 = &spi8; | |
| 53 | spi9 = &spi9; | |
| 54 | spi10 = &spi10; | |
| 55 | spi11 = &spi11; | |
| 56 | spi12 = &spi12; | |
| 57 | spi13 = &spi13; | |
| 58 | spi14 = &spi14; | |
| 59 | spi15 = &spi15; | |
| 60 | spi16 = &spi16; | |
| 61 | spi17 = &spi17; | |
| 62 | spi18 = &spi18; | |
| 63 | spi19 = &spi19; | |
| 64 | }; | |
| 65 | ||
| 60378f1a VNKG |
66 | chosen { }; |
| 67 | ||
| 68 | clocks { | |
| 69 | xo_board: xo-board { | |
| 70 | compatible = "fixed-clock"; | |
| 71 | #clock-cells = <0>; | |
| 72 | clock-frequency = <38400000>; | |
| 73 | clock-output-names = "xo_board"; | |
| 74 | }; | |
| 75 | ||
| 76 | sleep_clk: sleep-clk { | |
| 77 | compatible = "fixed-clock"; | |
| 9ff8b059 | 78 | clock-frequency = <32768>; |
| 60378f1a VNKG |
79 | #clock-cells = <0>; |
| 80 | }; | |
| 81 | }; | |
| 82 | ||
| 83 | cpus { | |
| 84 | #address-cells = <2>; | |
| 85 | #size-cells = <0>; | |
| 86 | ||
| 87 | CPU0: cpu@0 { | |
| 88 | device_type = "cpu"; | |
| 89 | compatible = "qcom,kryo485"; | |
| 90 | reg = <0x0 0x0>; | |
| 91 | enable-method = "psci"; | |
| 92 | next-level-cache = <&L2_0>; | |
| 02ae4a0e | 93 | qcom,freq-domain = <&cpufreq_hw 0>; |
| bac12f25 | 94 | #cooling-cells = <2>; |
| 60378f1a VNKG |
95 | L2_0: l2-cache { |
| 96 | compatible = "cache"; | |
| 97 | next-level-cache = <&L3_0>; | |
| 98 | L3_0: l3-cache { | |
| 99 | compatible = "cache"; | |
| 100 | }; | |
| 101 | }; | |
| 102 | }; | |
| 103 | ||
| 104 | CPU1: cpu@100 { | |
| 105 | device_type = "cpu"; | |
| 106 | compatible = "qcom,kryo485"; | |
| 107 | reg = <0x0 0x100>; | |
| 108 | enable-method = "psci"; | |
| 109 | next-level-cache = <&L2_100>; | |
| 02ae4a0e | 110 | qcom,freq-domain = <&cpufreq_hw 0>; |
| bac12f25 | 111 | #cooling-cells = <2>; |
| 60378f1a VNKG |
112 | L2_100: l2-cache { |
| 113 | compatible = "cache"; | |
| 114 | next-level-cache = <&L3_0>; | |
| 115 | }; | |
| 116 | }; | |
| 117 | ||
| 118 | CPU2: cpu@200 { | |
| 119 | device_type = "cpu"; | |
| 120 | compatible = "qcom,kryo485"; | |
| 121 | reg = <0x0 0x200>; | |
| 122 | enable-method = "psci"; | |
| 123 | next-level-cache = <&L2_200>; | |
| 02ae4a0e | 124 | qcom,freq-domain = <&cpufreq_hw 0>; |
| bac12f25 | 125 | #cooling-cells = <2>; |
| 60378f1a VNKG |
126 | L2_200: l2-cache { |
| 127 | compatible = "cache"; | |
| 128 | next-level-cache = <&L3_0>; | |
| 129 | }; | |
| 130 | }; | |
| 131 | ||
| 132 | CPU3: cpu@300 { | |
| 133 | device_type = "cpu"; | |
| 134 | compatible = "qcom,kryo485"; | |
| 135 | reg = <0x0 0x300>; | |
| 136 | enable-method = "psci"; | |
| 137 | next-level-cache = <&L2_300>; | |
| 02ae4a0e | 138 | qcom,freq-domain = <&cpufreq_hw 0>; |
| bac12f25 | 139 | #cooling-cells = <2>; |
| 60378f1a VNKG |
140 | L2_300: l2-cache { |
| 141 | compatible = "cache"; | |
| 142 | next-level-cache = <&L3_0>; | |
| 143 | }; | |
| 144 | }; | |
| 145 | ||
| 146 | CPU4: cpu@400 { | |
| 147 | device_type = "cpu"; | |
| 148 | compatible = "qcom,kryo485"; | |
| 149 | reg = <0x0 0x400>; | |
| 150 | enable-method = "psci"; | |
| 151 | next-level-cache = <&L2_400>; | |
| 02ae4a0e | 152 | qcom,freq-domain = <&cpufreq_hw 1>; |
| bac12f25 | 153 | #cooling-cells = <2>; |
| 60378f1a VNKG |
154 | L2_400: l2-cache { |
| 155 | compatible = "cache"; | |
| 156 | next-level-cache = <&L3_0>; | |
| 157 | }; | |
| 158 | }; | |
| 159 | ||
| 160 | CPU5: cpu@500 { | |
| 161 | device_type = "cpu"; | |
| 162 | compatible = "qcom,kryo485"; | |
| 163 | reg = <0x0 0x500>; | |
| 164 | enable-method = "psci"; | |
| 165 | next-level-cache = <&L2_500>; | |
| 02ae4a0e | 166 | qcom,freq-domain = <&cpufreq_hw 1>; |
| bac12f25 | 167 | #cooling-cells = <2>; |
| 60378f1a VNKG |
168 | L2_500: l2-cache { |
| 169 | compatible = "cache"; | |
| 170 | next-level-cache = <&L3_0>; | |
| 171 | }; | |
| 172 | ||
| 173 | }; | |
| 174 | ||
| 175 | CPU6: cpu@600 { | |
| 176 | device_type = "cpu"; | |
| 177 | compatible = "qcom,kryo485"; | |
| 178 | reg = <0x0 0x600>; | |
| 179 | enable-method = "psci"; | |
| 180 | next-level-cache = <&L2_600>; | |
| 02ae4a0e | 181 | qcom,freq-domain = <&cpufreq_hw 1>; |
| bac12f25 | 182 | #cooling-cells = <2>; |
| 60378f1a VNKG |
183 | L2_600: l2-cache { |
| 184 | compatible = "cache"; | |
| 185 | next-level-cache = <&L3_0>; | |
| 186 | }; | |
| 187 | }; | |
| 188 | ||
| 189 | CPU7: cpu@700 { | |
| 190 | device_type = "cpu"; | |
| 191 | compatible = "qcom,kryo485"; | |
| 192 | reg = <0x0 0x700>; | |
| 193 | enable-method = "psci"; | |
| 194 | next-level-cache = <&L2_700>; | |
| 02ae4a0e | 195 | qcom,freq-domain = <&cpufreq_hw 2>; |
| bac12f25 | 196 | #cooling-cells = <2>; |
| 60378f1a VNKG |
197 | L2_700: l2-cache { |
| 198 | compatible = "cache"; | |
| 199 | next-level-cache = <&L3_0>; | |
| 200 | }; | |
| 201 | }; | |
| 202 | }; | |
| 203 | ||
| 204 | firmware { | |
| 205 | scm: scm { | |
| 206 | compatible = "qcom,scm"; | |
| 207 | #reset-cells = <1>; | |
| 208 | }; | |
| 209 | }; | |
| 210 | ||
| 60378f1a VNKG |
211 | memory@80000000 { |
| 212 | device_type = "memory"; | |
| 213 | /* We expect the bootloader to fill in the size */ | |
| 214 | reg = <0x0 0x80000000 0x0 0x0>; | |
| 215 | }; | |
| 216 | ||
| 217 | pmu { | |
| 218 | compatible = "arm,armv8-pmuv3"; | |
| 219 | interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 220 | }; | |
| 221 | ||
| 222 | psci { | |
| 223 | compatible = "arm,psci-1.0"; | |
| 224 | method = "smc"; | |
| 225 | }; | |
| 226 | ||
| 227 | reserved-memory { | |
| 228 | #address-cells = <2>; | |
| 229 | #size-cells = <2>; | |
| 230 | ranges; | |
| 231 | ||
| 232 | hyp_mem: memory@80000000 { | |
| 233 | reg = <0x0 0x80000000 0x0 0x600000>; | |
| 234 | no-map; | |
| 235 | }; | |
| 236 | ||
| 237 | xbl_aop_mem: memory@80700000 { | |
| 238 | reg = <0x0 0x80700000 0x0 0x160000>; | |
| 239 | no-map; | |
| 240 | }; | |
| 241 | ||
| 242 | cmd_db: memory@80860000 { | |
| 243 | compatible = "qcom,cmd-db"; | |
| 244 | reg = <0x0 0x80860000 0x0 0x20000>; | |
| 245 | no-map; | |
| 246 | }; | |
| 247 | ||
| 248 | smem_mem: memory@80900000 { | |
| 249 | reg = <0x0 0x80900000 0x0 0x200000>; | |
| 250 | no-map; | |
| 251 | }; | |
| 252 | ||
| 253 | removed_mem: memory@80b00000 { | |
| 254 | reg = <0x0 0x80b00000 0x0 0x5300000>; | |
| 255 | no-map; | |
| 256 | }; | |
| 257 | ||
| 258 | camera_mem: memory@86200000 { | |
| 259 | reg = <0x0 0x86200000 0x0 0x500000>; | |
| 260 | no-map; | |
| 261 | }; | |
| 262 | ||
| 263 | wlan_mem: memory@86700000 { | |
| 264 | reg = <0x0 0x86700000 0x0 0x100000>; | |
| 265 | no-map; | |
| 266 | }; | |
| 267 | ||
| 268 | ipa_fw_mem: memory@86800000 { | |
| 269 | reg = <0x0 0x86800000 0x0 0x10000>; | |
| 270 | no-map; | |
| 271 | }; | |
| 272 | ||
| 273 | ipa_gsi_mem: memory@86810000 { | |
| 274 | reg = <0x0 0x86810000 0x0 0xa000>; | |
| 275 | no-map; | |
| 276 | }; | |
| 277 | ||
| 278 | gpu_mem: memory@8681a000 { | |
| 279 | reg = <0x0 0x8681a000 0x0 0x2000>; | |
| 280 | no-map; | |
| 281 | }; | |
| 282 | ||
| 283 | npu_mem: memory@86900000 { | |
| 284 | reg = <0x0 0x86900000 0x0 0x500000>; | |
| 285 | no-map; | |
| 286 | }; | |
| 287 | ||
| 288 | video_mem: memory@86e00000 { | |
| 289 | reg = <0x0 0x86e00000 0x0 0x500000>; | |
| 290 | no-map; | |
| 291 | }; | |
| 292 | ||
| 293 | cvp_mem: memory@87300000 { | |
| 294 | reg = <0x0 0x87300000 0x0 0x500000>; | |
| 295 | no-map; | |
| 296 | }; | |
| 297 | ||
| 298 | cdsp_mem: memory@87800000 { | |
| 299 | reg = <0x0 0x87800000 0x0 0x1400000>; | |
| 300 | no-map; | |
| 301 | }; | |
| 302 | ||
| 303 | slpi_mem: memory@88c00000 { | |
| 304 | reg = <0x0 0x88c00000 0x0 0x1500000>; | |
| 305 | no-map; | |
| 306 | }; | |
| 307 | ||
| 308 | adsp_mem: memory@8a100000 { | |
| 309 | reg = <0x0 0x8a100000 0x0 0x1d00000>; | |
| 310 | no-map; | |
| 311 | }; | |
| 312 | ||
| 313 | spss_mem: memory@8be00000 { | |
| 314 | reg = <0x0 0x8be00000 0x0 0x100000>; | |
| 315 | no-map; | |
| 316 | }; | |
| 317 | ||
| 318 | cdsp_secure_heap: memory@8bf00000 { | |
| 319 | reg = <0x0 0x8bf00000 0x0 0x4600000>; | |
| 320 | no-map; | |
| 321 | }; | |
| 322 | }; | |
| 323 | ||
| 324 | smem: qcom,smem { | |
| 325 | compatible = "qcom,smem"; | |
| 326 | memory-region = <&smem_mem>; | |
| 327 | hwlocks = <&tcsr_mutex 3>; | |
| 328 | }; | |
| 329 | ||
| 8770a2a8 BA |
330 | smp2p-adsp { |
| 331 | compatible = "qcom,smp2p"; | |
| 332 | qcom,smem = <443>, <429>; | |
| 333 | interrupts-extended = <&ipcc IPCC_CLIENT_LPASS | |
| 334 | IPCC_MPROC_SIGNAL_SMP2P | |
| 335 | IRQ_TYPE_EDGE_RISING>; | |
| 336 | mboxes = <&ipcc IPCC_CLIENT_LPASS | |
| 337 | IPCC_MPROC_SIGNAL_SMP2P>; | |
| 338 | ||
| 339 | qcom,local-pid = <0>; | |
| 340 | qcom,remote-pid = <2>; | |
| 341 | ||
| 342 | smp2p_adsp_out: master-kernel { | |
| 343 | qcom,entry-name = "master-kernel"; | |
| 344 | #qcom,smem-state-cells = <1>; | |
| 345 | }; | |
| 346 | ||
| 347 | smp2p_adsp_in: slave-kernel { | |
| 348 | qcom,entry-name = "slave-kernel"; | |
| 349 | interrupt-controller; | |
| 350 | #interrupt-cells = <2>; | |
| 351 | }; | |
| 352 | }; | |
| 353 | ||
| 354 | smp2p-cdsp { | |
| 355 | compatible = "qcom,smp2p"; | |
| 356 | qcom,smem = <94>, <432>; | |
| 357 | interrupts-extended = <&ipcc IPCC_CLIENT_CDSP | |
| 358 | IPCC_MPROC_SIGNAL_SMP2P | |
| 359 | IRQ_TYPE_EDGE_RISING>; | |
| 360 | mboxes = <&ipcc IPCC_CLIENT_CDSP | |
| 361 | IPCC_MPROC_SIGNAL_SMP2P>; | |
| 362 | ||
| 363 | qcom,local-pid = <0>; | |
| 364 | qcom,remote-pid = <5>; | |
| 365 | ||
| 366 | smp2p_cdsp_out: master-kernel { | |
| 367 | qcom,entry-name = "master-kernel"; | |
| 368 | #qcom,smem-state-cells = <1>; | |
| 369 | }; | |
| 370 | ||
| 371 | smp2p_cdsp_in: slave-kernel { | |
| 372 | qcom,entry-name = "slave-kernel"; | |
| 373 | interrupt-controller; | |
| 374 | #interrupt-cells = <2>; | |
| 375 | }; | |
| 376 | }; | |
| 377 | ||
| 378 | smp2p-slpi { | |
| 379 | compatible = "qcom,smp2p"; | |
| 380 | qcom,smem = <481>, <430>; | |
| 381 | interrupts-extended = <&ipcc IPCC_CLIENT_SLPI | |
| 382 | IPCC_MPROC_SIGNAL_SMP2P | |
| 383 | IRQ_TYPE_EDGE_RISING>; | |
| 384 | mboxes = <&ipcc IPCC_CLIENT_SLPI | |
| 385 | IPCC_MPROC_SIGNAL_SMP2P>; | |
| 386 | ||
| 387 | qcom,local-pid = <0>; | |
| 388 | qcom,remote-pid = <3>; | |
| 389 | ||
| 390 | smp2p_slpi_out: master-kernel { | |
| 391 | qcom,entry-name = "master-kernel"; | |
| 392 | #qcom,smem-state-cells = <1>; | |
| 393 | }; | |
| 394 | ||
| 395 | smp2p_slpi_in: slave-kernel { | |
| 396 | qcom,entry-name = "slave-kernel"; | |
| 397 | interrupt-controller; | |
| 398 | #interrupt-cells = <2>; | |
| 399 | }; | |
| 400 | }; | |
| 401 | ||
| 60378f1a VNKG |
402 | soc: soc@0 { |
| 403 | #address-cells = <2>; | |
| 404 | #size-cells = <2>; | |
| 405 | ranges = <0 0 0 0 0x10 0>; | |
| 406 | dma-ranges = <0 0 0 0 0x10 0>; | |
| 407 | compatible = "simple-bus"; | |
| 408 | ||
| 409 | gcc: clock-controller@100000 { | |
| 410 | compatible = "qcom,gcc-sm8250"; | |
| 411 | reg = <0x0 0x00100000 0x0 0x1f0000>; | |
| 412 | #clock-cells = <1>; | |
| 413 | #reset-cells = <1>; | |
| 414 | #power-domain-cells = <1>; | |
| 76bd127e DB |
415 | clock-names = "bi_tcxo", |
| 416 | "bi_tcxo_ao", | |
| 417 | "sleep_clk"; | |
| 418 | clocks = <&rpmhcc RPMH_CXO_CLK>, | |
| 419 | <&rpmhcc RPMH_CXO_CLK_A>, | |
| 420 | <&sleep_clk>; | |
| 60378f1a VNKG |
421 | }; |
| 422 | ||
| e5361e75 BA |
423 | ipcc: mailbox@408000 { |
| 424 | compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; | |
| 425 | reg = <0 0x00408000 0 0x1000>; | |
| 426 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; | |
| 427 | interrupt-controller; | |
| 428 | #interrupt-cells = <3>; | |
| 429 | #mbox-cells = <2>; | |
| 430 | }; | |
| 431 | ||
| 01e869cc DB |
432 | qup_opp_table: qup-opp-table { |
| 433 | compatible = "operating-points-v2"; | |
| 434 | ||
| 435 | opp-50000000 { | |
| 436 | opp-hz = /bits/ 64 <50000000>; | |
| 437 | required-opps = <&rpmhpd_opp_min_svs>; | |
| 438 | }; | |
| 439 | ||
| 440 | opp-75000000 { | |
| 441 | opp-hz = /bits/ 64 <75000000>; | |
| 442 | required-opps = <&rpmhpd_opp_low_svs>; | |
| 443 | }; | |
| 444 | ||
| 445 | opp-120000000 { | |
| 446 | opp-hz = /bits/ 64 <120000000>; | |
| 447 | required-opps = <&rpmhpd_opp_svs>; | |
| 448 | }; | |
| 449 | }; | |
| 450 | ||
| e5813b15 DB |
451 | qupv3_id_2: geniqup@8c0000 { |
| 452 | compatible = "qcom,geni-se-qup"; | |
| 453 | reg = <0x0 0x008c0000 0x0 0x6000>; | |
| 454 | clock-names = "m-ahb", "s-ahb"; | |
| 455 | clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, | |
| 456 | <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; | |
| 457 | #address-cells = <2>; | |
| 458 | #size-cells = <2>; | |
| 459 | ranges; | |
| 460 | status = "disabled"; | |
| 461 | ||
| 462 | i2c14: i2c@880000 { | |
| 463 | compatible = "qcom,geni-i2c"; | |
| 464 | reg = <0 0x00880000 0 0x4000>; | |
| 465 | clock-names = "se"; | |
| 466 | clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; | |
| 467 | pinctrl-names = "default"; | |
| 468 | pinctrl-0 = <&qup_i2c14_default>; | |
| 469 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; | |
| 470 | #address-cells = <1>; | |
| 471 | #size-cells = <0>; | |
| 472 | status = "disabled"; | |
| 473 | }; | |
| 474 | ||
| 475 | spi14: spi@880000 { | |
| 476 | compatible = "qcom,geni-spi"; | |
| 477 | reg = <0 0x00880000 0 0x4000>; | |
| 478 | clock-names = "se"; | |
| 479 | clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; | |
| 480 | pinctrl-names = "default"; | |
| 481 | pinctrl-0 = <&qup_spi14_default>; | |
| 482 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; | |
| 483 | #address-cells = <1>; | |
| 484 | #size-cells = <0>; | |
| 01e869cc DB |
485 | power-domains = <&rpmhpd SM8250_CX>; |
| 486 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
487 | status = "disabled"; |
| 488 | }; | |
| 489 | ||
| 490 | i2c15: i2c@884000 { | |
| 491 | compatible = "qcom,geni-i2c"; | |
| 492 | reg = <0 0x00884000 0 0x4000>; | |
| 493 | clock-names = "se"; | |
| 494 | clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; | |
| 495 | pinctrl-names = "default"; | |
| 496 | pinctrl-0 = <&qup_i2c15_default>; | |
| 497 | interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; | |
| 498 | #address-cells = <1>; | |
| 499 | #size-cells = <0>; | |
| 500 | status = "disabled"; | |
| 501 | }; | |
| 502 | ||
| 503 | spi15: spi@884000 { | |
| 504 | compatible = "qcom,geni-spi"; | |
| 505 | reg = <0 0x00884000 0 0x4000>; | |
| 506 | clock-names = "se"; | |
| 507 | clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; | |
| 508 | pinctrl-names = "default"; | |
| 509 | pinctrl-0 = <&qup_spi15_default>; | |
| 510 | interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; | |
| 511 | #address-cells = <1>; | |
| 512 | #size-cells = <0>; | |
| 01e869cc DB |
513 | power-domains = <&rpmhpd SM8250_CX>; |
| 514 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
515 | status = "disabled"; |
| 516 | }; | |
| 517 | ||
| 518 | i2c16: i2c@888000 { | |
| 519 | compatible = "qcom,geni-i2c"; | |
| 520 | reg = <0 0x00888000 0 0x4000>; | |
| 521 | clock-names = "se"; | |
| 522 | clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; | |
| 523 | pinctrl-names = "default"; | |
| 524 | pinctrl-0 = <&qup_i2c16_default>; | |
| 525 | interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; | |
| 526 | #address-cells = <1>; | |
| 527 | #size-cells = <0>; | |
| 528 | status = "disabled"; | |
| 529 | }; | |
| 530 | ||
| 531 | spi16: spi@888000 { | |
| 532 | compatible = "qcom,geni-spi"; | |
| 533 | reg = <0 0x00888000 0 0x4000>; | |
| 534 | clock-names = "se"; | |
| 535 | clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; | |
| 536 | pinctrl-names = "default"; | |
| 537 | pinctrl-0 = <&qup_spi16_default>; | |
| 538 | interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; | |
| 539 | #address-cells = <1>; | |
| 540 | #size-cells = <0>; | |
| 01e869cc DB |
541 | power-domains = <&rpmhpd SM8250_CX>; |
| 542 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
543 | status = "disabled"; |
| 544 | }; | |
| 545 | ||
| 546 | i2c17: i2c@88c000 { | |
| 547 | compatible = "qcom,geni-i2c"; | |
| 548 | reg = <0 0x0088c000 0 0x4000>; | |
| 549 | clock-names = "se"; | |
| 550 | clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; | |
| 551 | pinctrl-names = "default"; | |
| 552 | pinctrl-0 = <&qup_i2c17_default>; | |
| 553 | interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; | |
| 554 | #address-cells = <1>; | |
| 555 | #size-cells = <0>; | |
| 556 | status = "disabled"; | |
| 557 | }; | |
| 558 | ||
| 559 | spi17: spi@88c000 { | |
| 560 | compatible = "qcom,geni-spi"; | |
| 561 | reg = <0 0x0088c000 0 0x4000>; | |
| 562 | clock-names = "se"; | |
| 563 | clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; | |
| 564 | pinctrl-names = "default"; | |
| 565 | pinctrl-0 = <&qup_spi17_default>; | |
| 566 | interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; | |
| 567 | #address-cells = <1>; | |
| 568 | #size-cells = <0>; | |
| 01e869cc DB |
569 | power-domains = <&rpmhpd SM8250_CX>; |
| 570 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
571 | status = "disabled"; |
| 572 | }; | |
| 573 | ||
| 08a9ae2d DB |
574 | uart17: serial@88c000 { |
| 575 | compatible = "qcom,geni-uart"; | |
| 576 | reg = <0 0x0088c000 0 0x4000>; | |
| 577 | clock-names = "se"; | |
| 578 | clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; | |
| 579 | pinctrl-names = "default"; | |
| 580 | pinctrl-0 = <&qup_uart17_default>; | |
| 581 | interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; | |
| 01e869cc DB |
582 | power-domains = <&rpmhpd SM8250_CX>; |
| 583 | operating-points-v2 = <&qup_opp_table>; | |
| 08a9ae2d DB |
584 | status = "disabled"; |
| 585 | }; | |
| 586 | ||
| e5813b15 DB |
587 | i2c18: i2c@890000 { |
| 588 | compatible = "qcom,geni-i2c"; | |
| 589 | reg = <0 0x00890000 0 0x4000>; | |
| 590 | clock-names = "se"; | |
| 591 | clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; | |
| 592 | pinctrl-names = "default"; | |
| 593 | pinctrl-0 = <&qup_i2c18_default>; | |
| 594 | interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; | |
| 595 | #address-cells = <1>; | |
| 596 | #size-cells = <0>; | |
| 597 | status = "disabled"; | |
| 598 | }; | |
| 599 | ||
| 600 | spi18: spi@890000 { | |
| 601 | compatible = "qcom,geni-spi"; | |
| 602 | reg = <0 0x00890000 0 0x4000>; | |
| 603 | clock-names = "se"; | |
| 604 | clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; | |
| 605 | pinctrl-names = "default"; | |
| 606 | pinctrl-0 = <&qup_spi18_default>; | |
| 607 | interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; | |
| 608 | #address-cells = <1>; | |
| 609 | #size-cells = <0>; | |
| 01e869cc DB |
610 | power-domains = <&rpmhpd SM8250_CX>; |
| 611 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
612 | status = "disabled"; |
| 613 | }; | |
| 614 | ||
| 08a9ae2d DB |
615 | uart18: serial@890000 { |
| 616 | compatible = "qcom,geni-uart"; | |
| 617 | reg = <0 0x00890000 0 0x4000>; | |
| 618 | clock-names = "se"; | |
| 619 | clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; | |
| 620 | pinctrl-names = "default"; | |
| 621 | pinctrl-0 = <&qup_uart18_default>; | |
| 622 | interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; | |
| 01e869cc DB |
623 | power-domains = <&rpmhpd SM8250_CX>; |
| 624 | operating-points-v2 = <&qup_opp_table>; | |
| 08a9ae2d DB |
625 | status = "disabled"; |
| 626 | }; | |
| 627 | ||
| e5813b15 DB |
628 | i2c19: i2c@894000 { |
| 629 | compatible = "qcom,geni-i2c"; | |
| 630 | reg = <0 0x00894000 0 0x4000>; | |
| 631 | clock-names = "se"; | |
| 632 | clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; | |
| 633 | pinctrl-names = "default"; | |
| 634 | pinctrl-0 = <&qup_i2c19_default>; | |
| 635 | interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; | |
| 636 | #address-cells = <1>; | |
| 637 | #size-cells = <0>; | |
| 638 | status = "disabled"; | |
| 639 | }; | |
| 640 | ||
| 641 | spi19: spi@894000 { | |
| 642 | compatible = "qcom,geni-spi"; | |
| 643 | reg = <0 0x00894000 0 0x4000>; | |
| 644 | clock-names = "se"; | |
| 645 | clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; | |
| 646 | pinctrl-names = "default"; | |
| 647 | pinctrl-0 = <&qup_spi19_default>; | |
| 648 | interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; | |
| 649 | #address-cells = <1>; | |
| 650 | #size-cells = <0>; | |
| 01e869cc DB |
651 | power-domains = <&rpmhpd SM8250_CX>; |
| 652 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
653 | status = "disabled"; |
| 654 | }; | |
| 655 | }; | |
| 656 | ||
| 657 | qupv3_id_0: geniqup@9c0000 { | |
| 658 | compatible = "qcom,geni-se-qup"; | |
| 659 | reg = <0x0 0x009c0000 0x0 0x6000>; | |
| 660 | clock-names = "m-ahb", "s-ahb"; | |
| 661 | clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, | |
| 662 | <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; | |
| 663 | #address-cells = <2>; | |
| 664 | #size-cells = <2>; | |
| 665 | ranges; | |
| 666 | status = "disabled"; | |
| 667 | ||
| 668 | i2c0: i2c@980000 { | |
| 669 | compatible = "qcom,geni-i2c"; | |
| 670 | reg = <0 0x00980000 0 0x4000>; | |
| 671 | clock-names = "se"; | |
| 672 | clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; | |
| 673 | pinctrl-names = "default"; | |
| 674 | pinctrl-0 = <&qup_i2c0_default>; | |
| 675 | interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; | |
| 676 | #address-cells = <1>; | |
| 677 | #size-cells = <0>; | |
| 678 | status = "disabled"; | |
| 679 | }; | |
| 680 | ||
| 681 | spi0: spi@980000 { | |
| 682 | compatible = "qcom,geni-spi"; | |
| 683 | reg = <0 0x00980000 0 0x4000>; | |
| 684 | clock-names = "se"; | |
| 685 | clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; | |
| 686 | pinctrl-names = "default"; | |
| 687 | pinctrl-0 = <&qup_spi0_default>; | |
| 688 | interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; | |
| 689 | #address-cells = <1>; | |
| 690 | #size-cells = <0>; | |
| 01e869cc DB |
691 | power-domains = <&rpmhpd SM8250_CX>; |
| 692 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
693 | status = "disabled"; |
| 694 | }; | |
| 695 | ||
| 696 | i2c1: i2c@984000 { | |
| 697 | compatible = "qcom,geni-i2c"; | |
| 698 | reg = <0 0x00984000 0 0x4000>; | |
| 699 | clock-names = "se"; | |
| 700 | clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; | |
| 701 | pinctrl-names = "default"; | |
| 702 | pinctrl-0 = <&qup_i2c1_default>; | |
| 703 | interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; | |
| 704 | #address-cells = <1>; | |
| 705 | #size-cells = <0>; | |
| 706 | status = "disabled"; | |
| 707 | }; | |
| 708 | ||
| 709 | spi1: spi@984000 { | |
| 710 | compatible = "qcom,geni-spi"; | |
| 711 | reg = <0 0x00984000 0 0x4000>; | |
| 712 | clock-names = "se"; | |
| 713 | clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; | |
| 714 | pinctrl-names = "default"; | |
| 715 | pinctrl-0 = <&qup_spi1_default>; | |
| 716 | interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; | |
| 717 | #address-cells = <1>; | |
| 718 | #size-cells = <0>; | |
| 01e869cc DB |
719 | power-domains = <&rpmhpd SM8250_CX>; |
| 720 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
721 | status = "disabled"; |
| 722 | }; | |
| 723 | ||
| 724 | i2c2: i2c@988000 { | |
| 725 | compatible = "qcom,geni-i2c"; | |
| 726 | reg = <0 0x00988000 0 0x4000>; | |
| 727 | clock-names = "se"; | |
| 728 | clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; | |
| 729 | pinctrl-names = "default"; | |
| 730 | pinctrl-0 = <&qup_i2c2_default>; | |
| 731 | interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; | |
| 732 | #address-cells = <1>; | |
| 733 | #size-cells = <0>; | |
| 734 | status = "disabled"; | |
| 735 | }; | |
| 736 | ||
| 737 | spi2: spi@988000 { | |
| 738 | compatible = "qcom,geni-spi"; | |
| 739 | reg = <0 0x00988000 0 0x4000>; | |
| 740 | clock-names = "se"; | |
| 741 | clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; | |
| 742 | pinctrl-names = "default"; | |
| 743 | pinctrl-0 = <&qup_spi2_default>; | |
| 744 | interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; | |
| 745 | #address-cells = <1>; | |
| 746 | #size-cells = <0>; | |
| 01e869cc DB |
747 | power-domains = <&rpmhpd SM8250_CX>; |
| 748 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
749 | status = "disabled"; |
| 750 | }; | |
| 751 | ||
| 08a9ae2d DB |
752 | uart2: serial@988000 { |
| 753 | compatible = "qcom,geni-debug-uart"; | |
| 754 | reg = <0 0x00988000 0 0x4000>; | |
| 755 | clock-names = "se"; | |
| 756 | clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; | |
| 757 | pinctrl-names = "default"; | |
| 758 | pinctrl-0 = <&qup_uart2_default>; | |
| 759 | interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; | |
| 01e869cc DB |
760 | power-domains = <&rpmhpd SM8250_CX>; |
| 761 | operating-points-v2 = <&qup_opp_table>; | |
| 08a9ae2d DB |
762 | status = "disabled"; |
| 763 | }; | |
| 764 | ||
| e5813b15 DB |
765 | i2c3: i2c@98c000 { |
| 766 | compatible = "qcom,geni-i2c"; | |
| 767 | reg = <0 0x0098c000 0 0x4000>; | |
| 768 | clock-names = "se"; | |
| 769 | clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; | |
| 770 | pinctrl-names = "default"; | |
| 771 | pinctrl-0 = <&qup_i2c3_default>; | |
| 772 | interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; | |
| 773 | #address-cells = <1>; | |
| 774 | #size-cells = <0>; | |
| 775 | status = "disabled"; | |
| 776 | }; | |
| 777 | ||
| 778 | spi3: spi@98c000 { | |
| 779 | compatible = "qcom,geni-spi"; | |
| 780 | reg = <0 0x0098c000 0 0x4000>; | |
| 781 | clock-names = "se"; | |
| 782 | clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; | |
| 783 | pinctrl-names = "default"; | |
| 784 | pinctrl-0 = <&qup_spi3_default>; | |
| 785 | interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; | |
| 786 | #address-cells = <1>; | |
| 787 | #size-cells = <0>; | |
| 01e869cc DB |
788 | power-domains = <&rpmhpd SM8250_CX>; |
| 789 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
790 | status = "disabled"; |
| 791 | }; | |
| 792 | ||
| 793 | i2c4: i2c@990000 { | |
| 794 | compatible = "qcom,geni-i2c"; | |
| 795 | reg = <0 0x00990000 0 0x4000>; | |
| 796 | clock-names = "se"; | |
| 797 | clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; | |
| 798 | pinctrl-names = "default"; | |
| 799 | pinctrl-0 = <&qup_i2c4_default>; | |
| 800 | interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; | |
| 801 | #address-cells = <1>; | |
| 802 | #size-cells = <0>; | |
| 803 | status = "disabled"; | |
| 804 | }; | |
| 805 | ||
| 806 | spi4: spi@990000 { | |
| 807 | compatible = "qcom,geni-spi"; | |
| 808 | reg = <0 0x00990000 0 0x4000>; | |
| 809 | clock-names = "se"; | |
| 810 | clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; | |
| 811 | pinctrl-names = "default"; | |
| 812 | pinctrl-0 = <&qup_spi4_default>; | |
| 813 | interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; | |
| 814 | #address-cells = <1>; | |
| 815 | #size-cells = <0>; | |
| 01e869cc DB |
816 | power-domains = <&rpmhpd SM8250_CX>; |
| 817 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
818 | status = "disabled"; |
| 819 | }; | |
| 820 | ||
| 821 | i2c5: i2c@994000 { | |
| 822 | compatible = "qcom,geni-i2c"; | |
| 823 | reg = <0 0x00994000 0 0x4000>; | |
| 824 | clock-names = "se"; | |
| 825 | clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; | |
| 826 | pinctrl-names = "default"; | |
| 827 | pinctrl-0 = <&qup_i2c5_default>; | |
| 828 | interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; | |
| 829 | #address-cells = <1>; | |
| 830 | #size-cells = <0>; | |
| 831 | status = "disabled"; | |
| 832 | }; | |
| 833 | ||
| 834 | spi5: spi@994000 { | |
| 835 | compatible = "qcom,geni-spi"; | |
| 836 | reg = <0 0x00994000 0 0x4000>; | |
| 837 | clock-names = "se"; | |
| 838 | clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; | |
| 839 | pinctrl-names = "default"; | |
| 840 | pinctrl-0 = <&qup_spi5_default>; | |
| 841 | interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; | |
| 842 | #address-cells = <1>; | |
| 843 | #size-cells = <0>; | |
| 01e869cc DB |
844 | power-domains = <&rpmhpd SM8250_CX>; |
| 845 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
846 | status = "disabled"; |
| 847 | }; | |
| 848 | ||
| 849 | i2c6: i2c@998000 { | |
| 850 | compatible = "qcom,geni-i2c"; | |
| 851 | reg = <0 0x00998000 0 0x4000>; | |
| 852 | clock-names = "se"; | |
| 853 | clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; | |
| 854 | pinctrl-names = "default"; | |
| 855 | pinctrl-0 = <&qup_i2c6_default>; | |
| 856 | interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; | |
| 857 | #address-cells = <1>; | |
| 858 | #size-cells = <0>; | |
| 859 | status = "disabled"; | |
| 860 | }; | |
| 861 | ||
| 862 | spi6: spi@998000 { | |
| 863 | compatible = "qcom,geni-spi"; | |
| 864 | reg = <0 0x00998000 0 0x4000>; | |
| 865 | clock-names = "se"; | |
| 866 | clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; | |
| 867 | pinctrl-names = "default"; | |
| 868 | pinctrl-0 = <&qup_spi6_default>; | |
| 869 | interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; | |
| 870 | #address-cells = <1>; | |
| 871 | #size-cells = <0>; | |
| 01e869cc DB |
872 | power-domains = <&rpmhpd SM8250_CX>; |
| 873 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
874 | status = "disabled"; |
| 875 | }; | |
| 876 | ||
| 08a9ae2d DB |
877 | uart6: serial@998000 { |
| 878 | compatible = "qcom,geni-uart"; | |
| 879 | reg = <0 0x00998000 0 0x4000>; | |
| 880 | clock-names = "se"; | |
| 881 | clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; | |
| 882 | pinctrl-names = "default"; | |
| 883 | pinctrl-0 = <&qup_uart6_default>; | |
| 884 | interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; | |
| 01e869cc DB |
885 | power-domains = <&rpmhpd SM8250_CX>; |
| 886 | operating-points-v2 = <&qup_opp_table>; | |
| 08a9ae2d DB |
887 | status = "disabled"; |
| 888 | }; | |
| 889 | ||
| e5813b15 DB |
890 | i2c7: i2c@99c000 { |
| 891 | compatible = "qcom,geni-i2c"; | |
| 892 | reg = <0 0x0099c000 0 0x4000>; | |
| 893 | clock-names = "se"; | |
| 894 | clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; | |
| 895 | pinctrl-names = "default"; | |
| 896 | pinctrl-0 = <&qup_i2c7_default>; | |
| 897 | interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; | |
| 898 | #address-cells = <1>; | |
| 899 | #size-cells = <0>; | |
| 900 | status = "disabled"; | |
| 901 | }; | |
| 902 | ||
| 903 | spi7: spi@99c000 { | |
| 904 | compatible = "qcom,geni-spi"; | |
| 905 | reg = <0 0x0099c000 0 0x4000>; | |
| 906 | clock-names = "se"; | |
| 907 | clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; | |
| 908 | pinctrl-names = "default"; | |
| 909 | pinctrl-0 = <&qup_spi7_default>; | |
| 910 | interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; | |
| 911 | #address-cells = <1>; | |
| 912 | #size-cells = <0>; | |
| 01e869cc DB |
913 | power-domains = <&rpmhpd SM8250_CX>; |
| 914 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
915 | status = "disabled"; |
| 916 | }; | |
| 917 | }; | |
| 918 | ||
| 60378f1a VNKG |
919 | qupv3_id_1: geniqup@ac0000 { |
| 920 | compatible = "qcom,geni-se-qup"; | |
| 921 | reg = <0x0 0x00ac0000 0x0 0x6000>; | |
| 922 | clock-names = "m-ahb", "s-ahb"; | |
| fe3dfc25 JM |
923 | clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 924 | <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; | |
| 60378f1a VNKG |
925 | #address-cells = <2>; |
| 926 | #size-cells = <2>; | |
| 927 | ranges; | |
| 928 | status = "disabled"; | |
| 929 | ||
| e5813b15 DB |
930 | i2c8: i2c@a80000 { |
| 931 | compatible = "qcom,geni-i2c"; | |
| 932 | reg = <0 0x00a80000 0 0x4000>; | |
| 933 | clock-names = "se"; | |
| 934 | clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; | |
| 935 | pinctrl-names = "default"; | |
| 936 | pinctrl-0 = <&qup_i2c8_default>; | |
| 937 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; | |
| 938 | #address-cells = <1>; | |
| 939 | #size-cells = <0>; | |
| 940 | status = "disabled"; | |
| 941 | }; | |
| 942 | ||
| 943 | spi8: spi@a80000 { | |
| 944 | compatible = "qcom,geni-spi"; | |
| 945 | reg = <0 0x00a80000 0 0x4000>; | |
| 946 | clock-names = "se"; | |
| 947 | clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; | |
| 948 | pinctrl-names = "default"; | |
| 949 | pinctrl-0 = <&qup_spi8_default>; | |
| 950 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; | |
| 951 | #address-cells = <1>; | |
| 952 | #size-cells = <0>; | |
| 01e869cc DB |
953 | power-domains = <&rpmhpd SM8250_CX>; |
| 954 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
955 | status = "disabled"; |
| 956 | }; | |
| 957 | ||
| 958 | i2c9: i2c@a84000 { | |
| 959 | compatible = "qcom,geni-i2c"; | |
| 960 | reg = <0 0x00a84000 0 0x4000>; | |
| 961 | clock-names = "se"; | |
| 962 | clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; | |
| 963 | pinctrl-names = "default"; | |
| 964 | pinctrl-0 = <&qup_i2c9_default>; | |
| 965 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
| 966 | #address-cells = <1>; | |
| 967 | #size-cells = <0>; | |
| 968 | status = "disabled"; | |
| 969 | }; | |
| 970 | ||
| 971 | spi9: spi@a84000 { | |
| 972 | compatible = "qcom,geni-spi"; | |
| 973 | reg = <0 0x00a84000 0 0x4000>; | |
| 974 | clock-names = "se"; | |
| 975 | clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; | |
| 976 | pinctrl-names = "default"; | |
| 977 | pinctrl-0 = <&qup_spi9_default>; | |
| 978 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
| 979 | #address-cells = <1>; | |
| 980 | #size-cells = <0>; | |
| 01e869cc DB |
981 | power-domains = <&rpmhpd SM8250_CX>; |
| 982 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
983 | status = "disabled"; |
| 984 | }; | |
| 985 | ||
| 986 | i2c10: i2c@a88000 { | |
| 987 | compatible = "qcom,geni-i2c"; | |
| 988 | reg = <0 0x00a88000 0 0x4000>; | |
| 989 | clock-names = "se"; | |
| 990 | clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; | |
| 991 | pinctrl-names = "default"; | |
| 992 | pinctrl-0 = <&qup_i2c10_default>; | |
| 993 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | |
| 994 | #address-cells = <1>; | |
| 995 | #size-cells = <0>; | |
| 996 | status = "disabled"; | |
| 997 | }; | |
| 998 | ||
| 999 | spi10: spi@a88000 { | |
| 1000 | compatible = "qcom,geni-spi"; | |
| 1001 | reg = <0 0x00a88000 0 0x4000>; | |
| 1002 | clock-names = "se"; | |
| 1003 | clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; | |
| 1004 | pinctrl-names = "default"; | |
| 1005 | pinctrl-0 = <&qup_spi10_default>; | |
| 1006 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | |
| 1007 | #address-cells = <1>; | |
| 1008 | #size-cells = <0>; | |
| 01e869cc DB |
1009 | power-domains = <&rpmhpd SM8250_CX>; |
| 1010 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
1011 | status = "disabled"; |
| 1012 | }; | |
| 1013 | ||
| 1014 | i2c11: i2c@a8c000 { | |
| 1015 | compatible = "qcom,geni-i2c"; | |
| 1016 | reg = <0 0x00a8c000 0 0x4000>; | |
| 1017 | clock-names = "se"; | |
| 1018 | clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; | |
| 1019 | pinctrl-names = "default"; | |
| 1020 | pinctrl-0 = <&qup_i2c11_default>; | |
| 1021 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; | |
| 1022 | #address-cells = <1>; | |
| 1023 | #size-cells = <0>; | |
| 1024 | status = "disabled"; | |
| 1025 | }; | |
| 1026 | ||
| 1027 | spi11: spi@a8c000 { | |
| 1028 | compatible = "qcom,geni-spi"; | |
| 1029 | reg = <0 0x00a8c000 0 0x4000>; | |
| 1030 | clock-names = "se"; | |
| 1031 | clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; | |
| 1032 | pinctrl-names = "default"; | |
| 1033 | pinctrl-0 = <&qup_spi11_default>; | |
| 1034 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; | |
| 1035 | #address-cells = <1>; | |
| 1036 | #size-cells = <0>; | |
| 01e869cc DB |
1037 | power-domains = <&rpmhpd SM8250_CX>; |
| 1038 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
1039 | status = "disabled"; |
| 1040 | }; | |
| 1041 | ||
| 1042 | i2c12: i2c@a90000 { | |
| 1043 | compatible = "qcom,geni-i2c"; | |
| 1044 | reg = <0 0x00a90000 0 0x4000>; | |
| 1045 | clock-names = "se"; | |
| 1046 | clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; | |
| 1047 | pinctrl-names = "default"; | |
| 1048 | pinctrl-0 = <&qup_i2c12_default>; | |
| 1049 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; | |
| 1050 | #address-cells = <1>; | |
| 1051 | #size-cells = <0>; | |
| 1052 | status = "disabled"; | |
| 1053 | }; | |
| 1054 | ||
| 1055 | spi12: spi@a90000 { | |
| 1056 | compatible = "qcom,geni-spi"; | |
| 1057 | reg = <0 0x00a90000 0 0x4000>; | |
| 1058 | clock-names = "se"; | |
| 1059 | clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; | |
| 1060 | pinctrl-names = "default"; | |
| 1061 | pinctrl-0 = <&qup_spi12_default>; | |
| 1062 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; | |
| 1063 | #address-cells = <1>; | |
| 1064 | #size-cells = <0>; | |
| 01e869cc DB |
1065 | power-domains = <&rpmhpd SM8250_CX>; |
| 1066 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
1067 | status = "disabled"; |
| 1068 | }; | |
| 1069 | ||
| bb1dfb4d | 1070 | uart12: serial@a90000 { |
| 60378f1a VNKG |
1071 | compatible = "qcom,geni-debug-uart"; |
| 1072 | reg = <0x0 0x00a90000 0x0 0x4000>; | |
| 1073 | clock-names = "se"; | |
| fe3dfc25 | 1074 | clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| bb1dfb4d MS |
1075 | pinctrl-names = "default"; |
| 1076 | pinctrl-0 = <&qup_uart12_default>; | |
| 60378f1a | 1077 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| 01e869cc DB |
1078 | power-domains = <&rpmhpd SM8250_CX>; |
| 1079 | operating-points-v2 = <&qup_opp_table>; | |
| 60378f1a VNKG |
1080 | status = "disabled"; |
| 1081 | }; | |
| e5813b15 DB |
1082 | |
| 1083 | i2c13: i2c@a94000 { | |
| 1084 | compatible = "qcom,geni-i2c"; | |
| 1085 | reg = <0 0x00a94000 0 0x4000>; | |
| 1086 | clock-names = "se"; | |
| 1087 | clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; | |
| 1088 | pinctrl-names = "default"; | |
| 1089 | pinctrl-0 = <&qup_i2c13_default>; | |
| 1090 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
| 1091 | #address-cells = <1>; | |
| 1092 | #size-cells = <0>; | |
| 1093 | status = "disabled"; | |
| 1094 | }; | |
| 1095 | ||
| 1096 | spi13: spi@a94000 { | |
| 1097 | compatible = "qcom,geni-spi"; | |
| 1098 | reg = <0 0x00a94000 0 0x4000>; | |
| 1099 | clock-names = "se"; | |
| 1100 | clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; | |
| 1101 | pinctrl-names = "default"; | |
| 1102 | pinctrl-0 = <&qup_spi13_default>; | |
| 1103 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
| 1104 | #address-cells = <1>; | |
| 1105 | #size-cells = <0>; | |
| 01e869cc DB |
1106 | power-domains = <&rpmhpd SM8250_CX>; |
| 1107 | operating-points-v2 = <&qup_opp_table>; | |
| e5813b15 DB |
1108 | status = "disabled"; |
| 1109 | }; | |
| 60378f1a VNKG |
1110 | }; |
| 1111 | ||
| e7e41a20 JM |
1112 | config_noc: interconnect@1500000 { |
| 1113 | compatible = "qcom,sm8250-config-noc"; | |
| 1114 | reg = <0 0x01500000 0 0xa580>; | |
| 1115 | #interconnect-cells = <1>; | |
| 1116 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1117 | }; | |
| 1118 | ||
| 1119 | system_noc: interconnect@1620000 { | |
| 1120 | compatible = "qcom,sm8250-system-noc"; | |
| 1121 | reg = <0 0x01620000 0 0x1c200>; | |
| 1122 | #interconnect-cells = <1>; | |
| 1123 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1124 | }; | |
| 1125 | ||
| 1126 | mc_virt: interconnect@163d000 { | |
| 1127 | compatible = "qcom,sm8250-mc-virt"; | |
| 1128 | reg = <0 0x0163d000 0 0x1000>; | |
| 1129 | #interconnect-cells = <1>; | |
| 1130 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1131 | }; | |
| 1132 | ||
| 1133 | aggre1_noc: interconnect@16e0000 { | |
| 1134 | compatible = "qcom,sm8250-aggre1-noc"; | |
| 1135 | reg = <0 0x016e0000 0 0x1f180>; | |
| 1136 | #interconnect-cells = <1>; | |
| 1137 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1138 | }; | |
| 1139 | ||
| 1140 | aggre2_noc: interconnect@1700000 { | |
| 1141 | compatible = "qcom,sm8250-aggre2-noc"; | |
| 1142 | reg = <0 0x01700000 0 0x33000>; | |
| 1143 | #interconnect-cells = <1>; | |
| 1144 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1145 | }; | |
| 1146 | ||
| 1147 | compute_noc: interconnect@1733000 { | |
| 1148 | compatible = "qcom,sm8250-compute-noc"; | |
| 1149 | reg = <0 0x01733000 0 0xa180>; | |
| 1150 | #interconnect-cells = <1>; | |
| 1151 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1152 | }; | |
| 1153 | ||
| 1154 | mmss_noc: interconnect@1740000 { | |
| 1155 | compatible = "qcom,sm8250-mmss-noc"; | |
| 1156 | reg = <0 0x01740000 0 0x1f080>; | |
| 1157 | #interconnect-cells = <1>; | |
| 1158 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1159 | }; | |
| 1160 | ||
| 6b9afd8f | 1161 | ufs_mem_hc: ufshc@1d84000 { |
| b7e2fba0 BD |
1162 | compatible = "qcom,sm8250-ufshc", "qcom,ufshc", |
| 1163 | "jedec,ufs-2.0"; | |
| 1164 | reg = <0 0x01d84000 0 0x3000>; | |
| 1165 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; | |
| 1166 | phys = <&ufs_mem_phy_lanes>; | |
| 1167 | phy-names = "ufsphy"; | |
| 1168 | lanes-per-direction = <2>; | |
| 1169 | #reset-cells = <1>; | |
| 1170 | resets = <&gcc GCC_UFS_PHY_BCR>; | |
| 1171 | reset-names = "rst"; | |
| 1172 | ||
| 1173 | power-domains = <&gcc UFS_PHY_GDSC>; | |
| 1174 | ||
| a89441fc JM |
1175 | iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; |
| 1176 | ||
| b7e2fba0 BD |
1177 | clock-names = |
| 1178 | "core_clk", | |
| 1179 | "bus_aggr_clk", | |
| 1180 | "iface_clk", | |
| 1181 | "core_clk_unipro", | |
| 1182 | "ref_clk", | |
| 1183 | "tx_lane0_sync_clk", | |
| 1184 | "rx_lane0_sync_clk", | |
| 1185 | "rx_lane1_sync_clk"; | |
| 1186 | clocks = | |
| 1187 | <&gcc GCC_UFS_PHY_AXI_CLK>, | |
| 1188 | <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, | |
| 1189 | <&gcc GCC_UFS_PHY_AHB_CLK>, | |
| 1190 | <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, | |
| 1191 | <&rpmhcc RPMH_CXO_CLK>, | |
| 1192 | <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, | |
| 1193 | <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, | |
| 1194 | <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; | |
| 1195 | freq-table-hz = | |
| 1196 | <37500000 300000000>, | |
| 1197 | <0 0>, | |
| 1198 | <0 0>, | |
| 1199 | <37500000 300000000>, | |
| 1200 | <0 0>, | |
| 1201 | <0 0>, | |
| 1202 | <0 0>, | |
| 1203 | <0 0>; | |
| 1204 | ||
| 1205 | status = "disabled"; | |
| 1206 | }; | |
| 1207 | ||
| 1208 | ufs_mem_phy: phy@1d87000 { | |
| 1209 | compatible = "qcom,sm8250-qmp-ufs-phy"; | |
| 1210 | reg = <0 0x01d87000 0 0x1c0>; | |
| 1211 | #address-cells = <2>; | |
| 1212 | #size-cells = <2>; | |
| 1213 | ranges; | |
| 1214 | clock-names = "ref", | |
| 1215 | "ref_aux"; | |
| 1216 | clocks = <&rpmhcc RPMH_CXO_CLK>, | |
| 1217 | <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; | |
| 1218 | ||
| 1219 | resets = <&ufs_mem_hc 0>; | |
| 1220 | reset-names = "ufsphy"; | |
| 1221 | status = "disabled"; | |
| 1222 | ||
| 1223 | ufs_mem_phy_lanes: lanes@1d87400 { | |
| 1224 | reg = <0 0x01d87400 0 0x108>, | |
| 1225 | <0 0x01d87600 0 0x1e0>, | |
| 1226 | <0 0x01d87c00 0 0x1dc>, | |
| 1227 | <0 0x01d87800 0 0x108>, | |
| 1228 | <0 0x01d87a00 0 0x1e0>; | |
| 1229 | #phy-cells = <0>; | |
| 1230 | }; | |
| 1231 | }; | |
| 1232 | ||
| e7e41a20 JM |
1233 | ipa_virt: interconnect@1e00000 { |
| 1234 | compatible = "qcom,sm8250-ipa-virt"; | |
| 1235 | reg = <0 0x01e00000 0 0x1000>; | |
| 1236 | #interconnect-cells = <1>; | |
| 1237 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1238 | }; | |
| 1239 | ||
| dff0f49c BA |
1240 | tcsr_mutex: hwlock@1f40000 { |
| 1241 | compatible = "qcom,tcsr-mutex"; | |
| b9ec8cbc | 1242 | reg = <0x0 0x01f40000 0x0 0x40000>; |
| dff0f49c | 1243 | #hwlock-cells = <1>; |
| 60378f1a VNKG |
1244 | }; |
| 1245 | ||
| 04a3605b JM |
1246 | gpu: gpu@3d00000 { |
| 1247 | /* | |
| 1248 | * note: the amd,imageon compatible makes it possible | |
| 1249 | * to use the drm/msm driver without the display node, | |
| 1250 | * make sure to remove it when display node is added | |
| 1251 | */ | |
| 1252 | compatible = "qcom,adreno-650.2", | |
| 1253 | "qcom,adreno", | |
| 1254 | "amd,imageon"; | |
| 1255 | #stream-id-cells = <16>; | |
| 1256 | ||
| 1257 | reg = <0 0x03d00000 0 0x40000>; | |
| 1258 | reg-names = "kgsl_3d0_reg_memory"; | |
| 1259 | ||
| 1260 | interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; | |
| 1261 | ||
| 1262 | iommus = <&adreno_smmu 0 0x401>; | |
| 1263 | ||
| 1264 | operating-points-v2 = <&gpu_opp_table>; | |
| 1265 | ||
| 1266 | qcom,gmu = <&gmu>; | |
| 1267 | ||
| 1268 | zap-shader { | |
| 1269 | memory-region = <&gpu_mem>; | |
| 1270 | }; | |
| 1271 | ||
| 1272 | /* note: downstream checks gpu binning for 670 Mhz */ | |
| 1273 | gpu_opp_table: opp-table { | |
| 1274 | compatible = "operating-points-v2"; | |
| 1275 | ||
| 1276 | opp-670000000 { | |
| 1277 | opp-hz = /bits/ 64 <670000000>; | |
| 1278 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; | |
| 1279 | }; | |
| 1280 | ||
| 1281 | opp-587000000 { | |
| 1282 | opp-hz = /bits/ 64 <587000000>; | |
| 1283 | opp-level = <RPMH_REGULATOR_LEVEL_NOM>; | |
| 1284 | }; | |
| 1285 | ||
| 1286 | opp-525000000 { | |
| 1287 | opp-hz = /bits/ 64 <525000000>; | |
| 1288 | opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; | |
| 1289 | }; | |
| 1290 | ||
| 1291 | opp-490000000 { | |
| 1292 | opp-hz = /bits/ 64 <490000000>; | |
| 1293 | opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; | |
| 1294 | }; | |
| 1295 | ||
| 1296 | opp-441600000 { | |
| 1297 | opp-hz = /bits/ 64 <441600000>; | |
| 1298 | opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; | |
| 1299 | }; | |
| 1300 | ||
| 1301 | opp-400000000 { | |
| 1302 | opp-hz = /bits/ 64 <400000000>; | |
| 1303 | opp-level = <RPMH_REGULATOR_LEVEL_SVS>; | |
| 1304 | }; | |
| 1305 | ||
| 1306 | opp-305000000 { | |
| 1307 | opp-hz = /bits/ 64 <305000000>; | |
| 1308 | opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; | |
| 1309 | }; | |
| 1310 | }; | |
| 1311 | }; | |
| 1312 | ||
| 1313 | gmu: gmu@3d6a000 { | |
| 1314 | compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; | |
| 1315 | ||
| 1316 | reg = <0 0x03d6a000 0 0x30000>, | |
| 1317 | <0 0x3de0000 0 0x10000>, | |
| 1318 | <0 0xb290000 0 0x10000>, | |
| 1319 | <0 0xb490000 0 0x10000>; | |
| 1320 | reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; | |
| 1321 | ||
| 1322 | interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, | |
| 1323 | <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; | |
| 1324 | interrupt-names = "hfi", "gmu"; | |
| 1325 | ||
| 0e6aa9db JM |
1326 | clocks = <&gpucc GPU_CC_AHB_CLK>, |
| 1327 | <&gpucc GPU_CC_CX_GMU_CLK>, | |
| 1328 | <&gpucc GPU_CC_CXO_CLK>, | |
| 04a3605b JM |
1329 | <&gcc GCC_DDRSS_GPU_AXI_CLK>, |
| 1330 | <&gcc GCC_GPU_MEMNOC_GFX_CLK>; | |
| 1331 | clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; | |
| 1332 | ||
| 0e6aa9db JM |
1333 | power-domains = <&gpucc GPU_CX_GDSC>, |
| 1334 | <&gpucc GPU_GX_GDSC>; | |
| 04a3605b JM |
1335 | power-domain-names = "cx", "gx"; |
| 1336 | ||
| 1337 | iommus = <&adreno_smmu 5 0x400>; | |
| 1338 | ||
| 1339 | operating-points-v2 = <&gmu_opp_table>; | |
| 1340 | ||
| 1341 | gmu_opp_table: opp-table { | |
| 1342 | compatible = "operating-points-v2"; | |
| 1343 | ||
| 1344 | opp-200000000 { | |
| 1345 | opp-hz = /bits/ 64 <200000000>; | |
| 1346 | opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; | |
| 1347 | }; | |
| 1348 | }; | |
| 1349 | }; | |
| 1350 | ||
| 1351 | gpucc: clock-controller@3d90000 { | |
| 1352 | compatible = "qcom,sm8250-gpucc"; | |
| 1353 | reg = <0 0x03d90000 0 0x9000>; | |
| 1354 | clocks = <&rpmhcc RPMH_CXO_CLK>, | |
| 1355 | <&gcc GCC_GPU_GPLL0_CLK_SRC>, | |
| 1356 | <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; | |
| 1357 | clock-names = "bi_tcxo", | |
| 1358 | "gcc_gpu_gpll0_clk_src", | |
| 1359 | "gcc_gpu_gpll0_div_clk_src"; | |
| 1360 | #clock-cells = <1>; | |
| 1361 | #reset-cells = <1>; | |
| 1362 | #power-domain-cells = <1>; | |
| 1363 | }; | |
| 1364 | ||
| 1365 | adreno_smmu: iommu@3da0000 { | |
| 1366 | compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; | |
| 1367 | reg = <0 0x03da0000 0 0x10000>; | |
| 1368 | #iommu-cells = <2>; | |
| 1369 | #global-interrupts = <2>; | |
| 1370 | interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, | |
| 1371 | <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, | |
| 1372 | <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, | |
| 1373 | <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, | |
| 1374 | <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, | |
| 1375 | <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, | |
| 1376 | <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, | |
| 1377 | <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, | |
| 1378 | <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, | |
| 1379 | <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; | |
| 0e6aa9db | 1380 | clocks = <&gpucc GPU_CC_AHB_CLK>, |
| 04a3605b JM |
1381 | <&gcc GCC_GPU_MEMNOC_GFX_CLK>, |
| 1382 | <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; | |
| 1383 | clock-names = "ahb", "bus", "iface"; | |
| 1384 | ||
| 0e6aa9db | 1385 | power-domains = <&gpucc GPU_CX_GDSC>; |
| 04a3605b JM |
1386 | }; |
| 1387 | ||
| 23a89037 BA |
1388 | slpi: remoteproc@5c00000 { |
| 1389 | compatible = "qcom,sm8250-slpi-pas"; | |
| 1390 | reg = <0 0x05c00000 0 0x4000>; | |
| 1391 | ||
| 1392 | interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, | |
| 1393 | <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, | |
| 1394 | <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, | |
| 1395 | <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, | |
| 1396 | <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; | |
| 1397 | interrupt-names = "wdog", "fatal", "ready", | |
| 1398 | "handover", "stop-ack"; | |
| 1399 | ||
| 1400 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 1401 | clock-names = "xo"; | |
| 1402 | ||
| 1403 | power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, | |
| 1404 | <&rpmhpd SM8250_LCX>, | |
| 1405 | <&rpmhpd SM8250_LMX>; | |
| 1406 | power-domain-names = "load_state", "lcx", "lmx"; | |
| 1407 | ||
| 1408 | memory-region = <&slpi_mem>; | |
| 1409 | ||
| 1410 | qcom,smem-states = <&smp2p_slpi_out 0>; | |
| 1411 | qcom,smem-state-names = "stop"; | |
| 1412 | ||
| 1413 | status = "disabled"; | |
| 1414 | ||
| 1415 | glink-edge { | |
| 1416 | interrupts-extended = <&ipcc IPCC_CLIENT_SLPI | |
| 1417 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
| 1418 | IRQ_TYPE_EDGE_RISING>; | |
| 1419 | mboxes = <&ipcc IPCC_CLIENT_SLPI | |
| 1420 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 1421 | ||
| 1422 | label = "lpass"; | |
| 1423 | qcom,remote-pid = <3>; | |
| 1424 | }; | |
| 1425 | }; | |
| 1426 | ||
| 1427 | cdsp: remoteproc@8300000 { | |
| 1428 | compatible = "qcom,sm8250-cdsp-pas"; | |
| 1429 | reg = <0 0x08300000 0 0x10000>; | |
| 1430 | ||
| 1431 | interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, | |
| 1432 | <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, | |
| 1433 | <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, | |
| 1434 | <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, | |
| 1435 | <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; | |
| 1436 | interrupt-names = "wdog", "fatal", "ready", | |
| 1437 | "handover", "stop-ack"; | |
| 1438 | ||
| 1439 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 1440 | clock-names = "xo"; | |
| 1441 | ||
| 1442 | power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, | |
| 1443 | <&rpmhpd SM8250_CX>; | |
| 1444 | power-domain-names = "load_state", "cx"; | |
| 1445 | ||
| 1446 | memory-region = <&cdsp_mem>; | |
| 1447 | ||
| 1448 | qcom,smem-states = <&smp2p_cdsp_out 0>; | |
| 1449 | qcom,smem-state-names = "stop"; | |
| 1450 | ||
| 1451 | status = "disabled"; | |
| 1452 | ||
| 1453 | glink-edge { | |
| 1454 | interrupts-extended = <&ipcc IPCC_CLIENT_CDSP | |
| 1455 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
| 1456 | IRQ_TYPE_EDGE_RISING>; | |
| 1457 | mboxes = <&ipcc IPCC_CLIENT_CDSP | |
| 1458 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 1459 | ||
| 1460 | label = "lpass"; | |
| 1461 | qcom,remote-pid = <5>; | |
| 1462 | }; | |
| 1463 | }; | |
| 1464 | ||
| e7e41a20 JM |
1465 | dc_noc: interconnect@90c0000 { |
| 1466 | compatible = "qcom,sm8250-dc-noc"; | |
| 1467 | reg = <0 0x090c0000 0 0x4200>; | |
| 1468 | #interconnect-cells = <1>; | |
| 1469 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1470 | }; | |
| 1471 | ||
| 1472 | gem_noc: interconnect@9100000 { | |
| 1473 | compatible = "qcom,sm8250-gem-noc"; | |
| 1474 | reg = <0 0x09100000 0 0xb4000>; | |
| 1475 | #interconnect-cells = <1>; | |
| 1476 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1477 | }; | |
| 1478 | ||
| 1479 | npu_noc: interconnect@9990000 { | |
| 1480 | compatible = "qcom,sm8250-npu-noc"; | |
| 1481 | reg = <0 0x09990000 0 0x1600>; | |
| 1482 | #interconnect-cells = <1>; | |
| 1483 | qcom,bcm-voters = <&apps_bcm_voter>; | |
| 1484 | }; | |
| 1485 | ||
| 60378f1a | 1486 | pdc: interrupt-controller@b220000 { |
| 24003196 BA |
1487 | compatible = "qcom,sm8250-pdc", "qcom,pdc"; |
| 1488 | reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; | |
| 60378f1a VNKG |
1489 | qcom,pdc-ranges = <0 480 94>, <94 609 31>, |
| 1490 | <125 63 1>, <126 716 12>; | |
| 1491 | #interrupt-cells = <2>; | |
| 1492 | interrupt-parent = <&intc>; | |
| 1493 | interrupt-controller; | |
| 1494 | }; | |
| 1495 | ||
| bac12f25 AK |
1496 | tsens0: thermal-sensor@c263000 { |
| 1497 | compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; | |
| 1498 | reg = <0 0x0c263000 0 0x1ff>, /* TM */ | |
| 1499 | <0 0x0c222000 0 0x1ff>; /* SROT */ | |
| 1500 | #qcom,sensors = <16>; | |
| 1501 | interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, | |
| 1502 | <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; | |
| 1503 | interrupt-names = "uplow", "critical"; | |
| 1504 | #thermal-sensor-cells = <1>; | |
| 1505 | }; | |
| 1506 | ||
| 1507 | tsens1: thermal-sensor@c265000 { | |
| 1508 | compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; | |
| 1509 | reg = <0 0x0c265000 0 0x1ff>, /* TM */ | |
| 1510 | <0 0x0c223000 0 0x1ff>; /* SROT */ | |
| 1511 | #qcom,sensors = <9>; | |
| 1512 | interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, | |
| 1513 | <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; | |
| 1514 | interrupt-names = "uplow", "critical"; | |
| 1515 | #thermal-sensor-cells = <1>; | |
| 1516 | }; | |
| 1517 | ||
| 087d537a BA |
1518 | aoss_qmp: qmp@c300000 { |
| 1519 | compatible = "qcom,sm8250-aoss-qmp"; | |
| 1520 | reg = <0 0x0c300000 0 0x100000>; | |
| 1521 | interrupts-extended = <&ipcc IPCC_CLIENT_AOP | |
| 1522 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
| 1523 | IRQ_TYPE_EDGE_RISING>; | |
| 1524 | mboxes = <&ipcc IPCC_CLIENT_AOP | |
| 1525 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 1526 | ||
| 1527 | #clock-cells = <0>; | |
| 1528 | #power-domain-cells = <1>; | |
| 1529 | }; | |
| 1530 | ||
| bccc7dd2 | 1531 | spmi_bus: spmi@c440000 { |
| 60378f1a VNKG |
1532 | compatible = "qcom,spmi-pmic-arb"; |
| 1533 | reg = <0x0 0x0c440000 0x0 0x0001100>, | |
| 1534 | <0x0 0x0c600000 0x0 0x2000000>, | |
| 1535 | <0x0 0x0e600000 0x0 0x0100000>, | |
| 1536 | <0x0 0x0e700000 0x0 0x00a0000>, | |
| 1537 | <0x0 0x0c40a000 0x0 0x0026000>; | |
| 1538 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; | |
| 1539 | interrupt-names = "periph_irq"; | |
| 1540 | interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; | |
| 1541 | qcom,ee = <0>; | |
| 1542 | qcom,channel = <0>; | |
| 1543 | #address-cells = <2>; | |
| 1544 | #size-cells = <0>; | |
| 1545 | interrupt-controller; | |
| 1546 | #interrupt-cells = <4>; | |
| 1547 | }; | |
| 1548 | ||
| 16951b49 BA |
1549 | tlmm: pinctrl@f100000 { |
| 1550 | compatible = "qcom,sm8250-pinctrl"; | |
| 1551 | reg = <0 0x0f100000 0 0x300000>, | |
| 1552 | <0 0x0f500000 0 0x300000>, | |
| 1553 | <0 0x0f900000 0 0x300000>; | |
| 1554 | reg-names = "west", "south", "north"; | |
| 1555 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
| 1556 | gpio-controller; | |
| 1557 | #gpio-cells = <2>; | |
| 1558 | interrupt-controller; | |
| 1559 | #interrupt-cells = <2>; | |
| 1560 | gpio-ranges = <&tlmm 0 0 180>; | |
| 1561 | wakeup-parent = <&pdc>; | |
| e5813b15 DB |
1562 | |
| 1563 | qup_i2c0_default: qup-i2c0-default { | |
| 1564 | mux { | |
| 1565 | pins = "gpio28", "gpio29"; | |
| 1566 | function = "qup0"; | |
| 1567 | }; | |
| 1568 | ||
| 1569 | config { | |
| 1570 | pins = "gpio28", "gpio29"; | |
| 1571 | drive-strength = <2>; | |
| 1572 | bias-disable; | |
| 1573 | }; | |
| 1574 | }; | |
| 1575 | ||
| 1576 | qup_i2c1_default: qup-i2c1-default { | |
| 1577 | pinmux { | |
| 1578 | pins = "gpio4", "gpio5"; | |
| 1579 | function = "qup1"; | |
| 1580 | }; | |
| 1581 | ||
| 1582 | config { | |
| 1583 | pins = "gpio4", "gpio5"; | |
| 1584 | drive-strength = <2>; | |
| 1585 | bias-disable; | |
| 1586 | }; | |
| 1587 | }; | |
| 1588 | ||
| 1589 | qup_i2c2_default: qup-i2c2-default { | |
| 1590 | mux { | |
| 1591 | pins = "gpio115", "gpio116"; | |
| 1592 | function = "qup2"; | |
| 1593 | }; | |
| 1594 | ||
| 1595 | config { | |
| 1596 | pins = "gpio115", "gpio116"; | |
| 1597 | drive-strength = <2>; | |
| 1598 | bias-disable; | |
| 1599 | }; | |
| 1600 | }; | |
| 1601 | ||
| 1602 | qup_i2c3_default: qup-i2c3-default { | |
| 1603 | mux { | |
| 1604 | pins = "gpio119", "gpio120"; | |
| 1605 | function = "qup3"; | |
| 1606 | }; | |
| 1607 | ||
| 1608 | config { | |
| 1609 | pins = "gpio119", "gpio120"; | |
| 1610 | drive-strength = <2>; | |
| 1611 | bias-disable; | |
| 1612 | }; | |
| 1613 | }; | |
| 1614 | ||
| 1615 | qup_i2c4_default: qup-i2c4-default { | |
| 1616 | mux { | |
| 1617 | pins = "gpio8", "gpio9"; | |
| 1618 | function = "qup4"; | |
| 1619 | }; | |
| 1620 | ||
| 1621 | config { | |
| 1622 | pins = "gpio8", "gpio9"; | |
| 1623 | drive-strength = <2>; | |
| 1624 | bias-disable; | |
| 1625 | }; | |
| 1626 | }; | |
| 1627 | ||
| 1628 | qup_i2c5_default: qup-i2c5-default { | |
| 1629 | mux { | |
| 1630 | pins = "gpio12", "gpio13"; | |
| 1631 | function = "qup5"; | |
| 1632 | }; | |
| 1633 | ||
| 1634 | config { | |
| 1635 | pins = "gpio12", "gpio13"; | |
| 1636 | drive-strength = <2>; | |
| 1637 | bias-disable; | |
| 1638 | }; | |
| 1639 | }; | |
| 1640 | ||
| 1641 | qup_i2c6_default: qup-i2c6-default { | |
| 1642 | mux { | |
| 1643 | pins = "gpio16", "gpio17"; | |
| 1644 | function = "qup6"; | |
| 1645 | }; | |
| 1646 | ||
| 1647 | config { | |
| 1648 | pins = "gpio16", "gpio17"; | |
| 1649 | drive-strength = <2>; | |
| 1650 | bias-disable; | |
| 1651 | }; | |
| 1652 | }; | |
| 1653 | ||
| 1654 | qup_i2c7_default: qup-i2c7-default { | |
| 1655 | mux { | |
| 1656 | pins = "gpio20", "gpio21"; | |
| 1657 | function = "qup7"; | |
| 1658 | }; | |
| 1659 | ||
| 1660 | config { | |
| 1661 | pins = "gpio20", "gpio21"; | |
| 1662 | drive-strength = <2>; | |
| 1663 | bias-disable; | |
| 1664 | }; | |
| 1665 | }; | |
| 1666 | ||
| 1667 | qup_i2c8_default: qup-i2c8-default { | |
| 1668 | mux { | |
| 1669 | pins = "gpio24", "gpio25"; | |
| 1670 | function = "qup8"; | |
| 1671 | }; | |
| 1672 | ||
| 1673 | config { | |
| 1674 | pins = "gpio24", "gpio25"; | |
| 1675 | drive-strength = <2>; | |
| 1676 | bias-disable; | |
| 1677 | }; | |
| 1678 | }; | |
| 1679 | ||
| 1680 | qup_i2c9_default: qup-i2c9-default { | |
| 1681 | mux { | |
| 1682 | pins = "gpio125", "gpio126"; | |
| 1683 | function = "qup9"; | |
| 1684 | }; | |
| 1685 | ||
| 1686 | config { | |
| 1687 | pins = "gpio125", "gpio126"; | |
| 1688 | drive-strength = <2>; | |
| 1689 | bias-disable; | |
| 1690 | }; | |
| 1691 | }; | |
| 1692 | ||
| 1693 | qup_i2c10_default: qup-i2c10-default { | |
| 1694 | mux { | |
| 1695 | pins = "gpio129", "gpio130"; | |
| 1696 | function = "qup10"; | |
| 1697 | }; | |
| 1698 | ||
| 1699 | config { | |
| 1700 | pins = "gpio129", "gpio130"; | |
| 1701 | drive-strength = <2>; | |
| 1702 | bias-disable; | |
| 1703 | }; | |
| 1704 | }; | |
| 1705 | ||
| 1706 | qup_i2c11_default: qup-i2c11-default { | |
| 1707 | mux { | |
| 1708 | pins = "gpio60", "gpio61"; | |
| 1709 | function = "qup11"; | |
| 1710 | }; | |
| 1711 | ||
| 1712 | config { | |
| 1713 | pins = "gpio60", "gpio61"; | |
| 1714 | drive-strength = <2>; | |
| 1715 | bias-disable; | |
| 1716 | }; | |
| 1717 | }; | |
| 1718 | ||
| 1719 | qup_i2c12_default: qup-i2c12-default { | |
| 1720 | mux { | |
| 1721 | pins = "gpio32", "gpio33"; | |
| 1722 | function = "qup12"; | |
| 1723 | }; | |
| 1724 | ||
| 1725 | config { | |
| 1726 | pins = "gpio32", "gpio33"; | |
| 1727 | drive-strength = <2>; | |
| 1728 | bias-disable; | |
| 1729 | }; | |
| 1730 | }; | |
| 1731 | ||
| 1732 | qup_i2c13_default: qup-i2c13-default { | |
| 1733 | mux { | |
| 1734 | pins = "gpio36", "gpio37"; | |
| 1735 | function = "qup13"; | |
| 1736 | }; | |
| 1737 | ||
| 1738 | config { | |
| 1739 | pins = "gpio36", "gpio37"; | |
| 1740 | drive-strength = <2>; | |
| 1741 | bias-disable; | |
| 1742 | }; | |
| 1743 | }; | |
| 1744 | ||
| 1745 | qup_i2c14_default: qup-i2c14-default { | |
| 1746 | mux { | |
| 1747 | pins = "gpio40", "gpio41"; | |
| 1748 | function = "qup14"; | |
| 1749 | }; | |
| 1750 | ||
| 1751 | config { | |
| 1752 | pins = "gpio40", "gpio41"; | |
| 1753 | drive-strength = <2>; | |
| 1754 | bias-disable; | |
| 1755 | }; | |
| 1756 | }; | |
| 1757 | ||
| 1758 | qup_i2c15_default: qup-i2c15-default { | |
| 1759 | mux { | |
| 1760 | pins = "gpio44", "gpio45"; | |
| 1761 | function = "qup15"; | |
| 1762 | }; | |
| 1763 | ||
| 1764 | config { | |
| 1765 | pins = "gpio44", "gpio45"; | |
| 1766 | drive-strength = <2>; | |
| 1767 | bias-disable; | |
| 1768 | }; | |
| 1769 | }; | |
| 1770 | ||
| 1771 | qup_i2c16_default: qup-i2c16-default { | |
| 1772 | mux { | |
| 1773 | pins = "gpio48", "gpio49"; | |
| 1774 | function = "qup16"; | |
| 1775 | }; | |
| 1776 | ||
| 1777 | config { | |
| 1778 | pins = "gpio48", "gpio49"; | |
| 1779 | drive-strength = <2>; | |
| 1780 | bias-disable; | |
| 1781 | }; | |
| 1782 | }; | |
| 1783 | ||
| 1784 | qup_i2c17_default: qup-i2c17-default { | |
| 1785 | mux { | |
| 1786 | pins = "gpio52", "gpio53"; | |
| 1787 | function = "qup17"; | |
| 1788 | }; | |
| 1789 | ||
| 1790 | config { | |
| 1791 | pins = "gpio52", "gpio53"; | |
| 1792 | drive-strength = <2>; | |
| 1793 | bias-disable; | |
| 1794 | }; | |
| 1795 | }; | |
| 1796 | ||
| 1797 | qup_i2c18_default: qup-i2c18-default { | |
| 1798 | mux { | |
| 1799 | pins = "gpio56", "gpio57"; | |
| 1800 | function = "qup18"; | |
| 1801 | }; | |
| 1802 | ||
| 1803 | config { | |
| 1804 | pins = "gpio56", "gpio57"; | |
| 1805 | drive-strength = <2>; | |
| 1806 | bias-disable; | |
| 1807 | }; | |
| 1808 | }; | |
| 1809 | ||
| 1810 | qup_i2c19_default: qup-i2c19-default { | |
| 1811 | mux { | |
| 1812 | pins = "gpio0", "gpio1"; | |
| 1813 | function = "qup19"; | |
| 1814 | }; | |
| 1815 | ||
| 1816 | config { | |
| 1817 | pins = "gpio0", "gpio1"; | |
| 1818 | drive-strength = <2>; | |
| 1819 | bias-disable; | |
| 1820 | }; | |
| 1821 | }; | |
| 1822 | ||
| 1823 | qup_spi0_default: qup-spi0-default { | |
| 1824 | mux { | |
| 1825 | pins = "gpio28", "gpio29", | |
| 1826 | "gpio30", "gpio31"; | |
| 1827 | function = "qup0"; | |
| 1828 | }; | |
| 1829 | ||
| 1830 | config { | |
| 1831 | pins = "gpio28", "gpio29", | |
| 1832 | "gpio30", "gpio31"; | |
| 1833 | drive-strength = <6>; | |
| 1834 | bias-disable; | |
| 1835 | }; | |
| 1836 | }; | |
| 1837 | ||
| 1838 | qup_spi1_default: qup-spi1-default { | |
| 1839 | mux { | |
| 1840 | pins = "gpio4", "gpio5", | |
| 1841 | "gpio6", "gpio7"; | |
| 1842 | function = "qup1"; | |
| 1843 | }; | |
| 1844 | ||
| 1845 | config { | |
| 1846 | pins = "gpio4", "gpio5", | |
| 1847 | "gpio6", "gpio7"; | |
| 1848 | drive-strength = <6>; | |
| 1849 | bias-disable; | |
| 1850 | }; | |
| 1851 | }; | |
| 1852 | ||
| 1853 | qup_spi2_default: qup-spi2-default { | |
| 1854 | mux { | |
| 1855 | pins = "gpio115", "gpio116", | |
| 1856 | "gpio117", "gpio118"; | |
| 1857 | function = "qup2"; | |
| 1858 | }; | |
| 1859 | ||
| 1860 | config { | |
| 1861 | pins = "gpio115", "gpio116", | |
| 1862 | "gpio117", "gpio118"; | |
| 1863 | drive-strength = <6>; | |
| 1864 | bias-disable; | |
| 1865 | }; | |
| 1866 | }; | |
| 1867 | ||
| 1868 | qup_spi3_default: qup-spi3-default { | |
| 1869 | mux { | |
| 1870 | pins = "gpio119", "gpio120", | |
| 1871 | "gpio121", "gpio122"; | |
| 1872 | function = "qup3"; | |
| 1873 | }; | |
| 1874 | ||
| 1875 | config { | |
| 1876 | pins = "gpio119", "gpio120", | |
| 1877 | "gpio121", "gpio122"; | |
| 1878 | drive-strength = <6>; | |
| 1879 | bias-disable; | |
| 1880 | }; | |
| 1881 | }; | |
| 1882 | ||
| 1883 | qup_spi4_default: qup-spi4-default { | |
| 1884 | mux { | |
| 1885 | pins = "gpio8", "gpio9", | |
| 1886 | "gpio10", "gpio11"; | |
| 1887 | function = "qup4"; | |
| 1888 | }; | |
| 1889 | ||
| 1890 | config { | |
| 1891 | pins = "gpio8", "gpio9", | |
| 1892 | "gpio10", "gpio11"; | |
| 1893 | drive-strength = <6>; | |
| 1894 | bias-disable; | |
| 1895 | }; | |
| 1896 | }; | |
| 1897 | ||
| 1898 | qup_spi5_default: qup-spi5-default { | |
| 1899 | mux { | |
| 1900 | pins = "gpio12", "gpio13", | |
| 1901 | "gpio14", "gpio15"; | |
| 1902 | function = "qup5"; | |
| 1903 | }; | |
| 1904 | ||
| 1905 | config { | |
| 1906 | pins = "gpio12", "gpio13", | |
| 1907 | "gpio14", "gpio15"; | |
| 1908 | drive-strength = <6>; | |
| 1909 | bias-disable; | |
| 1910 | }; | |
| 1911 | }; | |
| 1912 | ||
| 1913 | qup_spi6_default: qup-spi6-default { | |
| 1914 | mux { | |
| 1915 | pins = "gpio16", "gpio17", | |
| 1916 | "gpio18", "gpio19"; | |
| 1917 | function = "qup6"; | |
| 1918 | }; | |
| 1919 | ||
| 1920 | config { | |
| 1921 | pins = "gpio16", "gpio17", | |
| 1922 | "gpio18", "gpio19"; | |
| 1923 | drive-strength = <6>; | |
| 1924 | bias-disable; | |
| 1925 | }; | |
| 1926 | }; | |
| 1927 | ||
| 1928 | qup_spi7_default: qup-spi7-default { | |
| 1929 | mux { | |
| 1930 | pins = "gpio20", "gpio21", | |
| 1931 | "gpio22", "gpio23"; | |
| 1932 | function = "qup7"; | |
| 1933 | }; | |
| 1934 | ||
| 1935 | config { | |
| 1936 | pins = "gpio20", "gpio21", | |
| 1937 | "gpio22", "gpio23"; | |
| 1938 | drive-strength = <6>; | |
| 1939 | bias-disable; | |
| 1940 | }; | |
| 1941 | }; | |
| 1942 | ||
| 1943 | qup_spi8_default: qup-spi8-default { | |
| 1944 | mux { | |
| 1945 | pins = "gpio24", "gpio25", | |
| 1946 | "gpio26", "gpio27"; | |
| 1947 | function = "qup8"; | |
| 1948 | }; | |
| 1949 | ||
| 1950 | config { | |
| 1951 | pins = "gpio24", "gpio25", | |
| 1952 | "gpio26", "gpio27"; | |
| 1953 | drive-strength = <6>; | |
| 1954 | bias-disable; | |
| 1955 | }; | |
| 1956 | }; | |
| 1957 | ||
| 1958 | qup_spi9_default: qup-spi9-default { | |
| 1959 | mux { | |
| 1960 | pins = "gpio125", "gpio126", | |
| 1961 | "gpio127", "gpio128"; | |
| 1962 | function = "qup9"; | |
| 1963 | }; | |
| 1964 | ||
| 1965 | config { | |
| 1966 | pins = "gpio125", "gpio126", | |
| 1967 | "gpio127", "gpio128"; | |
| 1968 | drive-strength = <6>; | |
| 1969 | bias-disable; | |
| 1970 | }; | |
| 1971 | }; | |
| 1972 | ||
| 1973 | qup_spi10_default: qup-spi10-default { | |
| 1974 | mux { | |
| 1975 | pins = "gpio129", "gpio130", | |
| 1976 | "gpio131", "gpio132"; | |
| 1977 | function = "qup10"; | |
| 1978 | }; | |
| 1979 | ||
| 1980 | config { | |
| 1981 | pins = "gpio129", "gpio130", | |
| 1982 | "gpio131", "gpio132"; | |
| 1983 | drive-strength = <6>; | |
| 1984 | bias-disable; | |
| 1985 | }; | |
| 1986 | }; | |
| 1987 | ||
| 1988 | qup_spi11_default: qup-spi11-default { | |
| 1989 | mux { | |
| 1990 | pins = "gpio60", "gpio61", | |
| 1991 | "gpio62", "gpio63"; | |
| 1992 | function = "qup11"; | |
| 1993 | }; | |
| 1994 | ||
| 1995 | config { | |
| 1996 | pins = "gpio60", "gpio61", | |
| 1997 | "gpio62", "gpio63"; | |
| 1998 | drive-strength = <6>; | |
| 1999 | bias-disable; | |
| 2000 | }; | |
| 2001 | }; | |
| 2002 | ||
| 2003 | qup_spi12_default: qup-spi12-default { | |
| 2004 | mux { | |
| 2005 | pins = "gpio32", "gpio33", | |
| 2006 | "gpio34", "gpio35"; | |
| 2007 | function = "qup12"; | |
| 2008 | }; | |
| 2009 | ||
| 2010 | config { | |
| 2011 | pins = "gpio32", "gpio33", | |
| 2012 | "gpio34", "gpio35"; | |
| 2013 | drive-strength = <6>; | |
| 2014 | bias-disable; | |
| 2015 | }; | |
| 2016 | }; | |
| 2017 | ||
| 2018 | qup_spi13_default: qup-spi13-default { | |
| 2019 | mux { | |
| 2020 | pins = "gpio36", "gpio37", | |
| 2021 | "gpio38", "gpio39"; | |
| 2022 | function = "qup13"; | |
| 2023 | }; | |
| 2024 | ||
| 2025 | config { | |
| 2026 | pins = "gpio36", "gpio37", | |
| 2027 | "gpio38", "gpio39"; | |
| 2028 | drive-strength = <6>; | |
| 2029 | bias-disable; | |
| 2030 | }; | |
| 2031 | }; | |
| 2032 | ||
| 2033 | qup_spi14_default: qup-spi14-default { | |
| 2034 | mux { | |
| 2035 | pins = "gpio40", "gpio41", | |
| 2036 | "gpio42", "gpio43"; | |
| 2037 | function = "qup14"; | |
| 2038 | }; | |
| 2039 | ||
| 2040 | config { | |
| 2041 | pins = "gpio40", "gpio41", | |
| 2042 | "gpio42", "gpio43"; | |
| 2043 | drive-strength = <6>; | |
| 2044 | bias-disable; | |
| 2045 | }; | |
| 2046 | }; | |
| 2047 | ||
| 2048 | qup_spi15_default: qup-spi15-default { | |
| 2049 | mux { | |
| 2050 | pins = "gpio44", "gpio45", | |
| 2051 | "gpio46", "gpio47"; | |
| 2052 | function = "qup15"; | |
| 2053 | }; | |
| 2054 | ||
| 2055 | config { | |
| 2056 | pins = "gpio44", "gpio45", | |
| 2057 | "gpio46", "gpio47"; | |
| 2058 | drive-strength = <6>; | |
| 2059 | bias-disable; | |
| 2060 | }; | |
| 2061 | }; | |
| 2062 | ||
| 2063 | qup_spi16_default: qup-spi16-default { | |
| 2064 | mux { | |
| 2065 | pins = "gpio48", "gpio49", | |
| 2066 | "gpio50", "gpio51"; | |
| 2067 | function = "qup16"; | |
| 2068 | }; | |
| 2069 | ||
| 2070 | config { | |
| 2071 | pins = "gpio48", "gpio49", | |
| 2072 | "gpio50", "gpio51"; | |
| 2073 | drive-strength = <6>; | |
| 2074 | bias-disable; | |
| 2075 | }; | |
| 2076 | }; | |
| 2077 | ||
| 2078 | qup_spi17_default: qup-spi17-default { | |
| 2079 | mux { | |
| 2080 | pins = "gpio52", "gpio53", | |
| 2081 | "gpio54", "gpio55"; | |
| 2082 | function = "qup17"; | |
| 2083 | }; | |
| 2084 | ||
| 2085 | config { | |
| 2086 | pins = "gpio52", "gpio53", | |
| 2087 | "gpio54", "gpio55"; | |
| 2088 | drive-strength = <6>; | |
| 2089 | bias-disable; | |
| 2090 | }; | |
| 2091 | }; | |
| 2092 | ||
| 2093 | qup_spi18_default: qup-spi18-default { | |
| 2094 | mux { | |
| 2095 | pins = "gpio56", "gpio57", | |
| 2096 | "gpio58", "gpio59"; | |
| 2097 | function = "qup18"; | |
| 2098 | }; | |
| 2099 | ||
| 2100 | config { | |
| 2101 | pins = "gpio56", "gpio57", | |
| 2102 | "gpio58", "gpio59"; | |
| 2103 | drive-strength = <6>; | |
| 2104 | bias-disable; | |
| 2105 | }; | |
| 2106 | }; | |
| 2107 | ||
| 2108 | qup_spi19_default: qup-spi19-default { | |
| 2109 | mux { | |
| 2110 | pins = "gpio0", "gpio1", | |
| 2111 | "gpio2", "gpio3"; | |
| 2112 | function = "qup19"; | |
| 2113 | }; | |
| 2114 | ||
| 2115 | config { | |
| 2116 | pins = "gpio0", "gpio1", | |
| 2117 | "gpio2", "gpio3"; | |
| 2118 | drive-strength = <6>; | |
| 2119 | bias-disable; | |
| 2120 | }; | |
| 2121 | }; | |
| bb1dfb4d | 2122 | |
| 08a9ae2d DB |
2123 | qup_uart2_default: qup-uart2-default { |
| 2124 | mux { | |
| 2125 | pins = "gpio117", "gpio118"; | |
| 2126 | function = "qup2"; | |
| 2127 | }; | |
| 2128 | }; | |
| 2129 | ||
| 2130 | qup_uart6_default: qup-uart6-default { | |
| 2131 | mux { | |
| 2132 | pins = "gpio16", "gpio17", | |
| 2133 | "gpio18", "gpio19"; | |
| 2134 | function = "qup6"; | |
| 2135 | }; | |
| 2136 | }; | |
| 2137 | ||
| bb1dfb4d MS |
2138 | qup_uart12_default: qup-uart12-default { |
| 2139 | mux { | |
| 2140 | pins = "gpio34", "gpio35"; | |
| 2141 | function = "qup12"; | |
| 2142 | }; | |
| 2143 | }; | |
| 08a9ae2d DB |
2144 | |
| 2145 | qup_uart17_default: qup-uart17-default { | |
| 2146 | mux { | |
| 2147 | pins = "gpio52", "gpio53", | |
| 2148 | "gpio54", "gpio55"; | |
| 2149 | function = "qup17"; | |
| 2150 | }; | |
| 2151 | }; | |
| 2152 | ||
| 2153 | qup_uart18_default: qup-uart18-default { | |
| 2154 | mux { | |
| 2155 | pins = "gpio58", "gpio59"; | |
| 2156 | function = "qup18"; | |
| 2157 | }; | |
| 2158 | }; | |
| 16951b49 BA |
2159 | }; |
| 2160 | ||
| a89441fc JM |
2161 | apps_smmu: iommu@15000000 { |
| 2162 | compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; | |
| 2163 | reg = <0 0x15000000 0 0x100000>; | |
| 2164 | #iommu-cells = <2>; | |
| 2165 | #global-interrupts = <2>; | |
| 2166 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, | |
| 2167 | <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, | |
| 2168 | <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, | |
| 2169 | <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, | |
| 2170 | <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, | |
| 2171 | <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, | |
| 2172 | <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, | |
| 2173 | <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, | |
| 2174 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, | |
| 2175 | <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, | |
| 2176 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
| 2177 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
| 2178 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
| 2179 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
| 2180 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
| 2181 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
| 2182 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
| 2183 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
| 2184 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
| 2185 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
| 2186 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
| 2187 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
| 2188 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 2189 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
| 2190 | <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, | |
| 2191 | <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, | |
| 2192 | <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, | |
| 2193 | <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, | |
| 2194 | <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, | |
| 2195 | <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, | |
| 2196 | <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, | |
| 2197 | <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, | |
| 2198 | <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, | |
| 2199 | <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, | |
| 2200 | <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, | |
| 2201 | <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, | |
| 2202 | <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, | |
| 2203 | <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, | |
| 2204 | <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, | |
| 2205 | <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, | |
| 2206 | <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, | |
| 2207 | <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, | |
| 2208 | <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, | |
| 2209 | <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, | |
| 2210 | <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, | |
| 2211 | <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, | |
| 2212 | <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, | |
| 2213 | <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, | |
| 2214 | <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, | |
| 2215 | <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, | |
| 2216 | <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, | |
| 2217 | <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, | |
| 2218 | <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, | |
| 2219 | <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, | |
| 2220 | <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, | |
| 2221 | <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
| 2222 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, | |
| 2223 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
| 2224 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, | |
| 2225 | <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, | |
| 2226 | <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, | |
| 2227 | <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, | |
| 2228 | <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, | |
| 2229 | <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, | |
| 2230 | <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, | |
| 2231 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, | |
| 2232 | <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, | |
| 2233 | <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, | |
| 2234 | <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, | |
| 2235 | <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, | |
| 2236 | <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, | |
| 2237 | <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, | |
| 2238 | <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, | |
| 2239 | <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, | |
| 2240 | <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, | |
| 2241 | <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, | |
| 2242 | <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, | |
| 2243 | <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, | |
| 2244 | <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, | |
| 2245 | <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, | |
| 2246 | <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, | |
| 2247 | <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, | |
| 2248 | <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, | |
| 2249 | <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, | |
| 2250 | <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, | |
| 2251 | <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, | |
| 2252 | <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, | |
| 2253 | <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, | |
| 2254 | <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, | |
| 2255 | <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, | |
| 2256 | <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, | |
| 2257 | <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, | |
| 2258 | <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, | |
| 2259 | <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, | |
| 2260 | <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, | |
| 2261 | <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, | |
| 2262 | <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, | |
| 2263 | <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; | |
| 2264 | }; | |
| 2265 | ||
| 23a89037 BA |
2266 | adsp: remoteproc@17300000 { |
| 2267 | compatible = "qcom,sm8250-adsp-pas"; | |
| 2268 | reg = <0 0x17300000 0 0x100>; | |
| 2269 | ||
| 2270 | interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, | |
| 2271 | <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, | |
| 2272 | <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, | |
| 2273 | <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, | |
| 2274 | <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; | |
| 2275 | interrupt-names = "wdog", "fatal", "ready", | |
| 2276 | "handover", "stop-ack"; | |
| 2277 | ||
| 2278 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
| 2279 | clock-names = "xo"; | |
| 2280 | ||
| 2281 | power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, | |
| 2282 | <&rpmhpd SM8250_LCX>, | |
| 2283 | <&rpmhpd SM8250_LMX>; | |
| 2284 | power-domain-names = "load_state", "lcx", "lmx"; | |
| 2285 | ||
| 2286 | memory-region = <&adsp_mem>; | |
| 2287 | ||
| 2288 | qcom,smem-states = <&smp2p_adsp_out 0>; | |
| 2289 | qcom,smem-state-names = "stop"; | |
| 2290 | ||
| 2291 | status = "disabled"; | |
| 2292 | ||
| 2293 | glink-edge { | |
| 2294 | interrupts-extended = <&ipcc IPCC_CLIENT_LPASS | |
| 2295 | IPCC_MPROC_SIGNAL_GLINK_QMP | |
| 2296 | IRQ_TYPE_EDGE_RISING>; | |
| 2297 | mboxes = <&ipcc IPCC_CLIENT_LPASS | |
| 2298 | IPCC_MPROC_SIGNAL_GLINK_QMP>; | |
| 2299 | ||
| 2300 | label = "lpass"; | |
| 2301 | qcom,remote-pid = <2>; | |
| 2302 | }; | |
| 2303 | }; | |
| 2304 | ||
| b9ec8cbc JM |
2305 | intc: interrupt-controller@17a00000 { |
| 2306 | compatible = "arm,gic-v3"; | |
| 2307 | #interrupt-cells = <3>; | |
| 2308 | interrupt-controller; | |
| 2309 | reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ | |
| 2310 | <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ | |
| 2311 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 2312 | }; | |
| 2313 | ||
| e0d9acce DB |
2314 | watchdog@17c10000 { |
| 2315 | compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; | |
| 2316 | reg = <0 0x17c10000 0 0x1000>; | |
| 2317 | clocks = <&sleep_clk>; | |
| 2318 | }; | |
| 2319 | ||
| b9ec8cbc JM |
2320 | timer@17c20000 { |
| 2321 | #address-cells = <2>; | |
| 2322 | #size-cells = <2>; | |
| 2323 | ranges; | |
| 2324 | compatible = "arm,armv7-timer-mem"; | |
| 2325 | reg = <0x0 0x17c20000 0x0 0x1000>; | |
| 2326 | clock-frequency = <19200000>; | |
| 2327 | ||
| 2328 | frame@17c21000 { | |
| 2329 | frame-number = <0>; | |
| 2330 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
| 2331 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
| 2332 | reg = <0x0 0x17c21000 0x0 0x1000>, | |
| 2333 | <0x0 0x17c22000 0x0 0x1000>; | |
| 2334 | }; | |
| 2335 | ||
| 2336 | frame@17c23000 { | |
| 2337 | frame-number = <1>; | |
| 2338 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 2339 | reg = <0x0 0x17c23000 0x0 0x1000>; | |
| 2340 | status = "disabled"; | |
| 2341 | }; | |
| 2342 | ||
| 2343 | frame@17c25000 { | |
| 2344 | frame-number = <2>; | |
| 2345 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 2346 | reg = <0x0 0x17c25000 0x0 0x1000>; | |
| 2347 | status = "disabled"; | |
| 2348 | }; | |
| 2349 | ||
| 2350 | frame@17c27000 { | |
| 2351 | frame-number = <3>; | |
| 2352 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 2353 | reg = <0x0 0x17c27000 0x0 0x1000>; | |
| 2354 | status = "disabled"; | |
| 2355 | }; | |
| 2356 | ||
| 2357 | frame@17c29000 { | |
| 2358 | frame-number = <4>; | |
| 2359 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
| 2360 | reg = <0x0 0x17c29000 0x0 0x1000>; | |
| 2361 | status = "disabled"; | |
| 2362 | }; | |
| 2363 | ||
| 2364 | frame@17c2b000 { | |
| 2365 | frame-number = <5>; | |
| 2366 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
| 2367 | reg = <0x0 0x17c2b000 0x0 0x1000>; | |
| 2368 | status = "disabled"; | |
| 2369 | }; | |
| 2370 | ||
| 2371 | frame@17c2d000 { | |
| 2372 | frame-number = <6>; | |
| 2373 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
| 2374 | reg = <0x0 0x17c2d000 0x0 0x1000>; | |
| 2375 | status = "disabled"; | |
| 2376 | }; | |
| 2377 | }; | |
| 2378 | ||
| 60378f1a VNKG |
2379 | apps_rsc: rsc@18200000 { |
| 2380 | label = "apps_rsc"; | |
| 2381 | compatible = "qcom,rpmh-rsc"; | |
| 2382 | reg = <0x0 0x18200000 0x0 0x10000>, | |
| 2383 | <0x0 0x18210000 0x0 0x10000>, | |
| 2384 | <0x0 0x18220000 0x0 0x10000>; | |
| 2385 | reg-names = "drv-0", "drv-1", "drv-2"; | |
| 2386 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
| 2387 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, | |
| 2388 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
| 2389 | qcom,tcs-offset = <0xd00>; | |
| 2390 | qcom,drv-id = <2>; | |
| 2391 | qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, | |
| 2392 | <WAKE_TCS 3>, <CONTROL_TCS 1>; | |
| 2393 | ||
| 2394 | rpmhcc: clock-controller { | |
| 2395 | compatible = "qcom,sm8250-rpmh-clk"; | |
| 2396 | #clock-cells = <1>; | |
| 2397 | clock-names = "xo"; | |
| 2398 | clocks = <&xo_board>; | |
| 2399 | }; | |
| b6f78e27 BA |
2400 | |
| 2401 | rpmhpd: power-controller { | |
| 2402 | compatible = "qcom,sm8250-rpmhpd"; | |
| 2403 | #power-domain-cells = <1>; | |
| 2404 | operating-points-v2 = <&rpmhpd_opp_table>; | |
| 2405 | ||
| 2406 | rpmhpd_opp_table: opp-table { | |
| 2407 | compatible = "operating-points-v2"; | |
| 2408 | ||
| 2409 | rpmhpd_opp_ret: opp1 { | |
| 2410 | opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; | |
| 2411 | }; | |
| 2412 | ||
| 2413 | rpmhpd_opp_min_svs: opp2 { | |
| 2414 | opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; | |
| 2415 | }; | |
| 2416 | ||
| 2417 | rpmhpd_opp_low_svs: opp3 { | |
| 2418 | opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; | |
| 2419 | }; | |
| 2420 | ||
| 2421 | rpmhpd_opp_svs: opp4 { | |
| 2422 | opp-level = <RPMH_REGULATOR_LEVEL_SVS>; | |
| 2423 | }; | |
| 2424 | ||
| 2425 | rpmhpd_opp_svs_l1: opp5 { | |
| 2426 | opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; | |
| 2427 | }; | |
| 2428 | ||
| 2429 | rpmhpd_opp_nom: opp6 { | |
| 2430 | opp-level = <RPMH_REGULATOR_LEVEL_NOM>; | |
| 2431 | }; | |
| 2432 | ||
| 2433 | rpmhpd_opp_nom_l1: opp7 { | |
| 2434 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; | |
| 2435 | }; | |
| 2436 | ||
| 2437 | rpmhpd_opp_nom_l2: opp8 { | |
| 2438 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; | |
| 2439 | }; | |
| 2440 | ||
| 2441 | rpmhpd_opp_turbo: opp9 { | |
| 2442 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; | |
| 2443 | }; | |
| 2444 | ||
| 2445 | rpmhpd_opp_turbo_l1: opp10 { | |
| 2446 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; | |
| 2447 | }; | |
| 2448 | }; | |
| 2449 | }; | |
| e7e41a20 JM |
2450 | |
| 2451 | apps_bcm_voter: bcm_voter { | |
| 2452 | compatible = "qcom,bcm-voter"; | |
| 2453 | }; | |
| 60378f1a | 2454 | }; |
| 79a595bb SS |
2455 | |
| 2456 | epss_l3: interconnect@18591000 { | |
| 2457 | compatible = "qcom,sm8250-epss-l3"; | |
| 2458 | reg = <0 0x18590000 0 0x1000>; | |
| 2459 | ||
| 2460 | clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; | |
| 2461 | clock-names = "xo", "alternate"; | |
| 2462 | ||
| 2463 | #interconnect-cells = <1>; | |
| 2464 | }; | |
| 02ae4a0e BA |
2465 | |
| 2466 | cpufreq_hw: cpufreq@18591000 { | |
| 2467 | compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; | |
| 2468 | reg = <0 0x18591000 0 0x1000>, | |
| 2469 | <0 0x18592000 0 0x1000>, | |
| 2470 | <0 0x18593000 0 0x1000>; | |
| 2471 | reg-names = "freq-domain0", "freq-domain1", | |
| 2472 | "freq-domain2"; | |
| 2473 | ||
| 2474 | clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; | |
| 2475 | clock-names = "xo", "alternate"; | |
| 2476 | ||
| 2477 | #freq-domain-cells = <1>; | |
| 2478 | }; | |
| 60378f1a VNKG |
2479 | }; |
| 2480 | ||
| 2481 | timer { | |
| 2482 | compatible = "arm,armv8-timer"; | |
| 2483 | interrupts = <GIC_PPI 13 | |
| 2484 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| 2485 | <GIC_PPI 14 | |
| 2486 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| 2487 | <GIC_PPI 11 | |
| 2488 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, | |
| 2489 | <GIC_PPI 12 | |
| 2490 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; | |
| 2491 | }; | |
| bac12f25 AK |
2492 | |
| 2493 | thermal-zones { | |
| 2494 | cpu0-thermal { | |
| 2495 | polling-delay-passive = <250>; | |
| 2496 | polling-delay = <1000>; | |
| 2497 | ||
| 2498 | thermal-sensors = <&tsens0 1>; | |
| 2499 | ||
| 2500 | trips { | |
| 2501 | cpu0_alert0: trip-point0 { | |
| 2502 | temperature = <90000>; | |
| 2503 | hysteresis = <2000>; | |
| 2504 | type = "passive"; | |
| 2505 | }; | |
| 2506 | ||
| 2507 | cpu0_alert1: trip-point1 { | |
| 2508 | temperature = <95000>; | |
| 2509 | hysteresis = <2000>; | |
| 2510 | type = "passive"; | |
| 2511 | }; | |
| 2512 | ||
| 2513 | cpu0_crit: cpu_crit { | |
| 2514 | temperature = <110000>; | |
| 2515 | hysteresis = <1000>; | |
| 2516 | type = "critical"; | |
| 2517 | }; | |
| 2518 | }; | |
| 2519 | ||
| 2520 | cooling-maps { | |
| 2521 | map0 { | |
| 2522 | trip = <&cpu0_alert0>; | |
| 2523 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2524 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2525 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2526 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2527 | }; | |
| 2528 | map1 { | |
| 2529 | trip = <&cpu0_alert1>; | |
| 2530 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2531 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2532 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2533 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2534 | }; | |
| 2535 | }; | |
| 2536 | }; | |
| 2537 | ||
| 2538 | cpu1-thermal { | |
| 2539 | polling-delay-passive = <250>; | |
| 2540 | polling-delay = <1000>; | |
| 2541 | ||
| 2542 | thermal-sensors = <&tsens0 2>; | |
| 2543 | ||
| 2544 | trips { | |
| 2545 | cpu1_alert0: trip-point0 { | |
| 2546 | temperature = <90000>; | |
| 2547 | hysteresis = <2000>; | |
| 2548 | type = "passive"; | |
| 2549 | }; | |
| 2550 | ||
| 2551 | cpu1_alert1: trip-point1 { | |
| 2552 | temperature = <95000>; | |
| 2553 | hysteresis = <2000>; | |
| 2554 | type = "passive"; | |
| 2555 | }; | |
| 2556 | ||
| 2557 | cpu1_crit: cpu_crit { | |
| 2558 | temperature = <110000>; | |
| 2559 | hysteresis = <1000>; | |
| 2560 | type = "critical"; | |
| 2561 | }; | |
| 2562 | }; | |
| 2563 | ||
| 2564 | cooling-maps { | |
| 2565 | map0 { | |
| 2566 | trip = <&cpu1_alert0>; | |
| 2567 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2568 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2569 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2570 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2571 | }; | |
| 2572 | map1 { | |
| 2573 | trip = <&cpu1_alert1>; | |
| 2574 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2575 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2576 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2577 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2578 | }; | |
| 2579 | }; | |
| 2580 | }; | |
| 2581 | ||
| 2582 | cpu2-thermal { | |
| 2583 | polling-delay-passive = <250>; | |
| 2584 | polling-delay = <1000>; | |
| 2585 | ||
| 2586 | thermal-sensors = <&tsens0 3>; | |
| 2587 | ||
| 2588 | trips { | |
| 2589 | cpu2_alert0: trip-point0 { | |
| 2590 | temperature = <90000>; | |
| 2591 | hysteresis = <2000>; | |
| 2592 | type = "passive"; | |
| 2593 | }; | |
| 2594 | ||
| 2595 | cpu2_alert1: trip-point1 { | |
| 2596 | temperature = <95000>; | |
| 2597 | hysteresis = <2000>; | |
| 2598 | type = "passive"; | |
| 2599 | }; | |
| 2600 | ||
| 2601 | cpu2_crit: cpu_crit { | |
| 2602 | temperature = <110000>; | |
| 2603 | hysteresis = <1000>; | |
| 2604 | type = "critical"; | |
| 2605 | }; | |
| 2606 | }; | |
| 2607 | ||
| 2608 | cooling-maps { | |
| 2609 | map0 { | |
| 2610 | trip = <&cpu2_alert0>; | |
| 2611 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2612 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2613 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2614 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2615 | }; | |
| 2616 | map1 { | |
| 2617 | trip = <&cpu2_alert1>; | |
| 2618 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2619 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2620 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2621 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2622 | }; | |
| 2623 | }; | |
| 2624 | }; | |
| 2625 | ||
| 2626 | cpu3-thermal { | |
| 2627 | polling-delay-passive = <250>; | |
| 2628 | polling-delay = <1000>; | |
| 2629 | ||
| 2630 | thermal-sensors = <&tsens0 4>; | |
| 2631 | ||
| 2632 | trips { | |
| 2633 | cpu3_alert0: trip-point0 { | |
| 2634 | temperature = <90000>; | |
| 2635 | hysteresis = <2000>; | |
| 2636 | type = "passive"; | |
| 2637 | }; | |
| 2638 | ||
| 2639 | cpu3_alert1: trip-point1 { | |
| 2640 | temperature = <95000>; | |
| 2641 | hysteresis = <2000>; | |
| 2642 | type = "passive"; | |
| 2643 | }; | |
| 2644 | ||
| 2645 | cpu3_crit: cpu_crit { | |
| 2646 | temperature = <110000>; | |
| 2647 | hysteresis = <1000>; | |
| 2648 | type = "critical"; | |
| 2649 | }; | |
| 2650 | }; | |
| 2651 | ||
| 2652 | cooling-maps { | |
| 2653 | map0 { | |
| 2654 | trip = <&cpu3_alert0>; | |
| 2655 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2656 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2657 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2658 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2659 | }; | |
| 2660 | map1 { | |
| 2661 | trip = <&cpu3_alert1>; | |
| 2662 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2663 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2664 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2665 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2666 | }; | |
| 2667 | }; | |
| 2668 | }; | |
| 2669 | ||
| 2670 | cpu4-top-thermal { | |
| 2671 | polling-delay-passive = <250>; | |
| 2672 | polling-delay = <1000>; | |
| 2673 | ||
| 2674 | thermal-sensors = <&tsens0 7>; | |
| 2675 | ||
| 2676 | trips { | |
| 2677 | cpu4_top_alert0: trip-point0 { | |
| 2678 | temperature = <90000>; | |
| 2679 | hysteresis = <2000>; | |
| 2680 | type = "passive"; | |
| 2681 | }; | |
| 2682 | ||
| 2683 | cpu4_top_alert1: trip-point1 { | |
| 2684 | temperature = <95000>; | |
| 2685 | hysteresis = <2000>; | |
| 2686 | type = "passive"; | |
| 2687 | }; | |
| 2688 | ||
| 2689 | cpu4_top_crit: cpu_crit { | |
| 2690 | temperature = <110000>; | |
| 2691 | hysteresis = <1000>; | |
| 2692 | type = "critical"; | |
| 2693 | }; | |
| 2694 | }; | |
| 2695 | ||
| 2696 | cooling-maps { | |
| 2697 | map0 { | |
| 2698 | trip = <&cpu4_top_alert0>; | |
| 2699 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2700 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2701 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2702 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2703 | }; | |
| 2704 | map1 { | |
| 2705 | trip = <&cpu4_top_alert1>; | |
| 2706 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2707 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2708 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2709 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2710 | }; | |
| 2711 | }; | |
| 2712 | }; | |
| 2713 | ||
| 2714 | cpu5-top-thermal { | |
| 2715 | polling-delay-passive = <250>; | |
| 2716 | polling-delay = <1000>; | |
| 2717 | ||
| 2718 | thermal-sensors = <&tsens0 8>; | |
| 2719 | ||
| 2720 | trips { | |
| 2721 | cpu5_top_alert0: trip-point0 { | |
| 2722 | temperature = <90000>; | |
| 2723 | hysteresis = <2000>; | |
| 2724 | type = "passive"; | |
| 2725 | }; | |
| 2726 | ||
| 2727 | cpu5_top_alert1: trip-point1 { | |
| 2728 | temperature = <95000>; | |
| 2729 | hysteresis = <2000>; | |
| 2730 | type = "passive"; | |
| 2731 | }; | |
| 2732 | ||
| 2733 | cpu5_top_crit: cpu_crit { | |
| 2734 | temperature = <110000>; | |
| 2735 | hysteresis = <1000>; | |
| 2736 | type = "critical"; | |
| 2737 | }; | |
| 2738 | }; | |
| 2739 | ||
| 2740 | cooling-maps { | |
| 2741 | map0 { | |
| 2742 | trip = <&cpu5_top_alert0>; | |
| 2743 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2744 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2745 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2746 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2747 | }; | |
| 2748 | map1 { | |
| 2749 | trip = <&cpu5_top_alert1>; | |
| 2750 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2751 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2752 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2753 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2754 | }; | |
| 2755 | }; | |
| 2756 | }; | |
| 2757 | ||
| 2758 | cpu6-top-thermal { | |
| 2759 | polling-delay-passive = <250>; | |
| 2760 | polling-delay = <1000>; | |
| 2761 | ||
| 2762 | thermal-sensors = <&tsens0 9>; | |
| 2763 | ||
| 2764 | trips { | |
| 2765 | cpu6_top_alert0: trip-point0 { | |
| 2766 | temperature = <90000>; | |
| 2767 | hysteresis = <2000>; | |
| 2768 | type = "passive"; | |
| 2769 | }; | |
| 2770 | ||
| 2771 | cpu6_top_alert1: trip-point1 { | |
| 2772 | temperature = <95000>; | |
| 2773 | hysteresis = <2000>; | |
| 2774 | type = "passive"; | |
| 2775 | }; | |
| 2776 | ||
| 2777 | cpu6_top_crit: cpu_crit { | |
| 2778 | temperature = <110000>; | |
| 2779 | hysteresis = <1000>; | |
| 2780 | type = "critical"; | |
| 2781 | }; | |
| 2782 | }; | |
| 2783 | ||
| 2784 | cooling-maps { | |
| 2785 | map0 { | |
| 2786 | trip = <&cpu6_top_alert0>; | |
| 2787 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2788 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2789 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2790 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2791 | }; | |
| 2792 | map1 { | |
| 2793 | trip = <&cpu6_top_alert1>; | |
| 2794 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2795 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2796 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2797 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2798 | }; | |
| 2799 | }; | |
| 2800 | }; | |
| 2801 | ||
| 2802 | cpu7-top-thermal { | |
| 2803 | polling-delay-passive = <250>; | |
| 2804 | polling-delay = <1000>; | |
| 2805 | ||
| 2806 | thermal-sensors = <&tsens0 10>; | |
| 2807 | ||
| 2808 | trips { | |
| 2809 | cpu7_top_alert0: trip-point0 { | |
| 2810 | temperature = <90000>; | |
| 2811 | hysteresis = <2000>; | |
| 2812 | type = "passive"; | |
| 2813 | }; | |
| 2814 | ||
| 2815 | cpu7_top_alert1: trip-point1 { | |
| 2816 | temperature = <95000>; | |
| 2817 | hysteresis = <2000>; | |
| 2818 | type = "passive"; | |
| 2819 | }; | |
| 2820 | ||
| 2821 | cpu7_top_crit: cpu_crit { | |
| 2822 | temperature = <110000>; | |
| 2823 | hysteresis = <1000>; | |
| 2824 | type = "critical"; | |
| 2825 | }; | |
| 2826 | }; | |
| 2827 | ||
| 2828 | cooling-maps { | |
| 2829 | map0 { | |
| 2830 | trip = <&cpu7_top_alert0>; | |
| 2831 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2832 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2833 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2834 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2835 | }; | |
| 2836 | map1 { | |
| 2837 | trip = <&cpu7_top_alert1>; | |
| 2838 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2839 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2840 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2841 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2842 | }; | |
| 2843 | }; | |
| 2844 | }; | |
| 2845 | ||
| 2846 | cpu4-bottom-thermal { | |
| 2847 | polling-delay-passive = <250>; | |
| 2848 | polling-delay = <1000>; | |
| 2849 | ||
| 2850 | thermal-sensors = <&tsens0 11>; | |
| 2851 | ||
| 2852 | trips { | |
| 2853 | cpu4_bottom_alert0: trip-point0 { | |
| 2854 | temperature = <90000>; | |
| 2855 | hysteresis = <2000>; | |
| 2856 | type = "passive"; | |
| 2857 | }; | |
| 2858 | ||
| 2859 | cpu4_bottom_alert1: trip-point1 { | |
| 2860 | temperature = <95000>; | |
| 2861 | hysteresis = <2000>; | |
| 2862 | type = "passive"; | |
| 2863 | }; | |
| 2864 | ||
| 2865 | cpu4_bottom_crit: cpu_crit { | |
| 2866 | temperature = <110000>; | |
| 2867 | hysteresis = <1000>; | |
| 2868 | type = "critical"; | |
| 2869 | }; | |
| 2870 | }; | |
| 2871 | ||
| 2872 | cooling-maps { | |
| 2873 | map0 { | |
| 2874 | trip = <&cpu4_bottom_alert0>; | |
| 2875 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2876 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2877 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2878 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2879 | }; | |
| 2880 | map1 { | |
| 2881 | trip = <&cpu4_bottom_alert1>; | |
| 2882 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2883 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2884 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2885 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2886 | }; | |
| 2887 | }; | |
| 2888 | }; | |
| 2889 | ||
| 2890 | cpu5-bottom-thermal { | |
| 2891 | polling-delay-passive = <250>; | |
| 2892 | polling-delay = <1000>; | |
| 2893 | ||
| 2894 | thermal-sensors = <&tsens0 12>; | |
| 2895 | ||
| 2896 | trips { | |
| 2897 | cpu5_bottom_alert0: trip-point0 { | |
| 2898 | temperature = <90000>; | |
| 2899 | hysteresis = <2000>; | |
| 2900 | type = "passive"; | |
| 2901 | }; | |
| 2902 | ||
| 2903 | cpu5_bottom_alert1: trip-point1 { | |
| 2904 | temperature = <95000>; | |
| 2905 | hysteresis = <2000>; | |
| 2906 | type = "passive"; | |
| 2907 | }; | |
| 2908 | ||
| 2909 | cpu5_bottom_crit: cpu_crit { | |
| 2910 | temperature = <110000>; | |
| 2911 | hysteresis = <1000>; | |
| 2912 | type = "critical"; | |
| 2913 | }; | |
| 2914 | }; | |
| 2915 | ||
| 2916 | cooling-maps { | |
| 2917 | map0 { | |
| 2918 | trip = <&cpu5_bottom_alert0>; | |
| 2919 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2920 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2921 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2922 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2923 | }; | |
| 2924 | map1 { | |
| 2925 | trip = <&cpu5_bottom_alert1>; | |
| 2926 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2927 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2928 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2929 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2930 | }; | |
| 2931 | }; | |
| 2932 | }; | |
| 2933 | ||
| 2934 | cpu6-bottom-thermal { | |
| 2935 | polling-delay-passive = <250>; | |
| 2936 | polling-delay = <1000>; | |
| 2937 | ||
| 2938 | thermal-sensors = <&tsens0 13>; | |
| 2939 | ||
| 2940 | trips { | |
| 2941 | cpu6_bottom_alert0: trip-point0 { | |
| 2942 | temperature = <90000>; | |
| 2943 | hysteresis = <2000>; | |
| 2944 | type = "passive"; | |
| 2945 | }; | |
| 2946 | ||
| 2947 | cpu6_bottom_alert1: trip-point1 { | |
| 2948 | temperature = <95000>; | |
| 2949 | hysteresis = <2000>; | |
| 2950 | type = "passive"; | |
| 2951 | }; | |
| 2952 | ||
| 2953 | cpu6_bottom_crit: cpu_crit { | |
| 2954 | temperature = <110000>; | |
| 2955 | hysteresis = <1000>; | |
| 2956 | type = "critical"; | |
| 2957 | }; | |
| 2958 | }; | |
| 2959 | ||
| 2960 | cooling-maps { | |
| 2961 | map0 { | |
| 2962 | trip = <&cpu6_bottom_alert0>; | |
| 2963 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2964 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2965 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2966 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2967 | }; | |
| 2968 | map1 { | |
| 2969 | trip = <&cpu6_bottom_alert1>; | |
| 2970 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2971 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2972 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 2973 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 2974 | }; | |
| 2975 | }; | |
| 2976 | }; | |
| 2977 | ||
| 2978 | cpu7-bottom-thermal { | |
| 2979 | polling-delay-passive = <250>; | |
| 2980 | polling-delay = <1000>; | |
| 2981 | ||
| 2982 | thermal-sensors = <&tsens0 14>; | |
| 2983 | ||
| 2984 | trips { | |
| 2985 | cpu7_bottom_alert0: trip-point0 { | |
| 2986 | temperature = <90000>; | |
| 2987 | hysteresis = <2000>; | |
| 2988 | type = "passive"; | |
| 2989 | }; | |
| 2990 | ||
| 2991 | cpu7_bottom_alert1: trip-point1 { | |
| 2992 | temperature = <95000>; | |
| 2993 | hysteresis = <2000>; | |
| 2994 | type = "passive"; | |
| 2995 | }; | |
| 2996 | ||
| 2997 | cpu7_bottom_crit: cpu_crit { | |
| 2998 | temperature = <110000>; | |
| 2999 | hysteresis = <1000>; | |
| 3000 | type = "critical"; | |
| 3001 | }; | |
| 3002 | }; | |
| 3003 | ||
| 3004 | cooling-maps { | |
| 3005 | map0 { | |
| 3006 | trip = <&cpu7_bottom_alert0>; | |
| 3007 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 3008 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 3009 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 3010 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 3011 | }; | |
| 3012 | map1 { | |
| 3013 | trip = <&cpu7_bottom_alert1>; | |
| 3014 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 3015 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 3016 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
| 3017 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 3018 | }; | |
| 3019 | }; | |
| 3020 | }; | |
| 3021 | ||
| 3022 | aoss0-thermal { | |
| 3023 | polling-delay-passive = <250>; | |
| 3024 | polling-delay = <1000>; | |
| 3025 | ||
| 3026 | thermal-sensors = <&tsens0 0>; | |
| 3027 | ||
| 3028 | trips { | |
| 3029 | aoss0_alert0: trip-point0 { | |
| 3030 | temperature = <90000>; | |
| 3031 | hysteresis = <2000>; | |
| 3032 | type = "hot"; | |
| 3033 | }; | |
| 3034 | }; | |
| 3035 | }; | |
| 3036 | ||
| 3037 | cluster0-thermal { | |
| 3038 | polling-delay-passive = <250>; | |
| 3039 | polling-delay = <1000>; | |
| 3040 | ||
| 3041 | thermal-sensors = <&tsens0 5>; | |
| 3042 | ||
| 3043 | trips { | |
| 3044 | cluster0_alert0: trip-point0 { | |
| 3045 | temperature = <90000>; | |
| 3046 | hysteresis = <2000>; | |
| 3047 | type = "hot"; | |
| 3048 | }; | |
| 3049 | cluster0_crit: cluster0_crit { | |
| 3050 | temperature = <110000>; | |
| 3051 | hysteresis = <2000>; | |
| 3052 | type = "critical"; | |
| 3053 | }; | |
| 3054 | }; | |
| 3055 | }; | |
| 3056 | ||
| 3057 | cluster1-thermal { | |
| 3058 | polling-delay-passive = <250>; | |
| 3059 | polling-delay = <1000>; | |
| 3060 | ||
| 3061 | thermal-sensors = <&tsens0 6>; | |
| 3062 | ||
| 3063 | trips { | |
| 3064 | cluster1_alert0: trip-point0 { | |
| 3065 | temperature = <90000>; | |
| 3066 | hysteresis = <2000>; | |
| 3067 | type = "hot"; | |
| 3068 | }; | |
| 3069 | cluster1_crit: cluster1_crit { | |
| 3070 | temperature = <110000>; | |
| 3071 | hysteresis = <2000>; | |
| 3072 | type = "critical"; | |
| 3073 | }; | |
| 3074 | }; | |
| 3075 | }; | |
| 3076 | ||
| 3077 | gpu-thermal-top { | |
| 3078 | polling-delay-passive = <250>; | |
| 3079 | polling-delay = <1000>; | |
| 3080 | ||
| 3081 | thermal-sensors = <&tsens0 15>; | |
| 3082 | ||
| 3083 | trips { | |
| 3084 | gpu1_alert0: trip-point0 { | |
| 3085 | temperature = <90000>; | |
| 3086 | hysteresis = <2000>; | |
| 3087 | type = "hot"; | |
| 3088 | }; | |
| 3089 | }; | |
| 3090 | }; | |
| 3091 | ||
| 3092 | aoss1-thermal { | |
| 3093 | polling-delay-passive = <250>; | |
| 3094 | polling-delay = <1000>; | |
| 3095 | ||
| 3096 | thermal-sensors = <&tsens1 0>; | |
| 3097 | ||
| 3098 | trips { | |
| 3099 | aoss1_alert0: trip-point0 { | |
| 3100 | temperature = <90000>; | |
| 3101 | hysteresis = <2000>; | |
| 3102 | type = "hot"; | |
| 3103 | }; | |
| 3104 | }; | |
| 3105 | }; | |
| 3106 | ||
| 3107 | wlan-thermal { | |
| 3108 | polling-delay-passive = <250>; | |
| 3109 | polling-delay = <1000>; | |
| 3110 | ||
| 3111 | thermal-sensors = <&tsens1 1>; | |
| 3112 | ||
| 3113 | trips { | |
| 3114 | wlan_alert0: trip-point0 { | |
| 3115 | temperature = <90000>; | |
| 3116 | hysteresis = <2000>; | |
| 3117 | type = "hot"; | |
| 3118 | }; | |
| 3119 | }; | |
| 3120 | }; | |
| 3121 | ||
| 3122 | video-thermal { | |
| 3123 | polling-delay-passive = <250>; | |
| 3124 | polling-delay = <1000>; | |
| 3125 | ||
| 3126 | thermal-sensors = <&tsens1 2>; | |
| 3127 | ||
| 3128 | trips { | |
| 3129 | video_alert0: trip-point0 { | |
| 3130 | temperature = <90000>; | |
| 3131 | hysteresis = <2000>; | |
| 3132 | type = "hot"; | |
| 3133 | }; | |
| 3134 | }; | |
| 3135 | }; | |
| 3136 | ||
| 3137 | mem-thermal { | |
| 3138 | polling-delay-passive = <250>; | |
| 3139 | polling-delay = <1000>; | |
| 3140 | ||
| 3141 | thermal-sensors = <&tsens1 3>; | |
| 3142 | ||
| 3143 | trips { | |
| 3144 | mem_alert0: trip-point0 { | |
| 3145 | temperature = <90000>; | |
| 3146 | hysteresis = <2000>; | |
| 3147 | type = "hot"; | |
| 3148 | }; | |
| 3149 | }; | |
| 3150 | }; | |
| 3151 | ||
| 3152 | q6-hvx-thermal { | |
| 3153 | polling-delay-passive = <250>; | |
| 3154 | polling-delay = <1000>; | |
| 3155 | ||
| 3156 | thermal-sensors = <&tsens1 4>; | |
| 3157 | ||
| 3158 | trips { | |
| 3159 | q6_hvx_alert0: trip-point0 { | |
| 3160 | temperature = <90000>; | |
| 3161 | hysteresis = <2000>; | |
| 3162 | type = "hot"; | |
| 3163 | }; | |
| 3164 | }; | |
| 3165 | }; | |
| 3166 | ||
| 3167 | camera-thermal { | |
| 3168 | polling-delay-passive = <250>; | |
| 3169 | polling-delay = <1000>; | |
| 3170 | ||
| 3171 | thermal-sensors = <&tsens1 5>; | |
| 3172 | ||
| 3173 | trips { | |
| 3174 | camera_alert0: trip-point0 { | |
| 3175 | temperature = <90000>; | |
| 3176 | hysteresis = <2000>; | |
| 3177 | type = "hot"; | |
| 3178 | }; | |
| 3179 | }; | |
| 3180 | }; | |
| 3181 | ||
| 3182 | compute-thermal { | |
| 3183 | polling-delay-passive = <250>; | |
| 3184 | polling-delay = <1000>; | |
| 3185 | ||
| 3186 | thermal-sensors = <&tsens1 6>; | |
| 3187 | ||
| 3188 | trips { | |
| 3189 | compute_alert0: trip-point0 { | |
| 3190 | temperature = <90000>; | |
| 3191 | hysteresis = <2000>; | |
| 3192 | type = "hot"; | |
| 3193 | }; | |
| 3194 | }; | |
| 3195 | }; | |
| 3196 | ||
| 3197 | npu-thermal { | |
| 3198 | polling-delay-passive = <250>; | |
| 3199 | polling-delay = <1000>; | |
| 3200 | ||
| 3201 | thermal-sensors = <&tsens1 7>; | |
| 3202 | ||
| 3203 | trips { | |
| 3204 | npu_alert0: trip-point0 { | |
| 3205 | temperature = <90000>; | |
| 3206 | hysteresis = <2000>; | |
| 3207 | type = "hot"; | |
| 3208 | }; | |
| 3209 | }; | |
| 3210 | }; | |
| 3211 | ||
| 3212 | gpu-thermal-bottom { | |
| 3213 | polling-delay-passive = <250>; | |
| 3214 | polling-delay = <1000>; | |
| 3215 | ||
| 3216 | thermal-sensors = <&tsens1 8>; | |
| 3217 | ||
| 3218 | trips { | |
| 3219 | gpu2_alert0: trip-point0 { | |
| 3220 | temperature = <90000>; | |
| 3221 | hysteresis = <2000>; | |
| 3222 | type = "hot"; | |
| 3223 | }; | |
| 3224 | }; | |
| 3225 | }; | |
| 3226 | }; | |
| 60378f1a | 3227 | }; |