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26a7e06d SH |
1 | /* |
2 | * Device Tree Source for the r8a7795 SoC | |
3 | * | |
4 | * Copyright (C) 2015 Renesas Electronics Corp. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
49af46b4 | 11 | #include <dt-bindings/clock/r8a7795-cpg-mssr.h> |
26a7e06d SH |
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
13 | ||
14 | / { | |
15 | compatible = "renesas,r8a7795"; | |
16 | #address-cells = <2>; | |
17 | #size-cells = <2>; | |
18 | ||
19 | cpus { | |
20 | #address-cells = <1>; | |
21 | #size-cells = <0>; | |
22 | ||
23 | /* 1 core only at this point */ | |
24 | a57_0: cpu@0 { | |
25 | compatible = "arm,cortex-a57", "arm,armv8"; | |
26 | reg = <0x0>; | |
27 | device_type = "cpu"; | |
28 | }; | |
29 | }; | |
30 | ||
31 | extal_clk: extal { | |
32 | compatible = "fixed-clock"; | |
33 | #clock-cells = <0>; | |
34 | /* This value must be overridden by the board */ | |
35 | clock-frequency = <0>; | |
36 | }; | |
37 | ||
38 | extalr_clk: extalr { | |
39 | compatible = "fixed-clock"; | |
40 | #clock-cells = <0>; | |
41 | /* This value must be overridden by the board */ | |
42 | clock-frequency = <0>; | |
43 | }; | |
44 | ||
45 | soc { | |
46 | compatible = "simple-bus"; | |
47 | interrupt-parent = <&gic>; | |
48 | #address-cells = <2>; | |
49 | #size-cells = <2>; | |
50 | ranges; | |
51 | ||
52 | gic: interrupt-controller@0xf1010000 { | |
53 | compatible = "arm,gic-400"; | |
54 | #interrupt-cells = <3>; | |
55 | #address-cells = <0>; | |
56 | interrupt-controller; | |
57 | reg = <0x0 0xf1010000 0 0x1000>, | |
58 | <0x0 0xf1020000 0 0x2000>; | |
59 | interrupts = <GIC_PPI 9 | |
60 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; | |
61 | }; | |
62 | ||
7b08623a TK |
63 | gpio0: gpio@e6050000 { |
64 | compatible = "renesas,gpio-r8a7795", | |
65 | "renesas,gpio-rcar"; | |
66 | reg = <0 0xe6050000 0 0x50>; | |
67 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
68 | #gpio-cells = <2>; | |
69 | gpio-controller; | |
70 | gpio-ranges = <&pfc 0 0 16>; | |
71 | #interrupt-cells = <2>; | |
72 | interrupt-controller; | |
73 | clocks = <&cpg CPG_MOD 912>; | |
74 | power-domains = <&cpg>; | |
75 | }; | |
76 | ||
77 | gpio1: gpio@e6051000 { | |
78 | compatible = "renesas,gpio-r8a7795", | |
79 | "renesas,gpio-rcar"; | |
80 | reg = <0 0xe6051000 0 0x50>; | |
81 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
82 | #gpio-cells = <2>; | |
83 | gpio-controller; | |
84 | gpio-ranges = <&pfc 0 32 28>; | |
85 | #interrupt-cells = <2>; | |
86 | interrupt-controller; | |
87 | clocks = <&cpg CPG_MOD 911>; | |
88 | power-domains = <&cpg>; | |
89 | }; | |
90 | ||
91 | gpio2: gpio@e6052000 { | |
92 | compatible = "renesas,gpio-r8a7795", | |
93 | "renesas,gpio-rcar"; | |
94 | reg = <0 0xe6052000 0 0x50>; | |
95 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
96 | #gpio-cells = <2>; | |
97 | gpio-controller; | |
98 | gpio-ranges = <&pfc 0 64 15>; | |
99 | #interrupt-cells = <2>; | |
100 | interrupt-controller; | |
101 | clocks = <&cpg CPG_MOD 910>; | |
102 | power-domains = <&cpg>; | |
103 | }; | |
104 | ||
105 | gpio3: gpio@e6053000 { | |
106 | compatible = "renesas,gpio-r8a7795", | |
107 | "renesas,gpio-rcar"; | |
108 | reg = <0 0xe6053000 0 0x50>; | |
109 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
110 | #gpio-cells = <2>; | |
111 | gpio-controller; | |
112 | gpio-ranges = <&pfc 0 96 16>; | |
113 | #interrupt-cells = <2>; | |
114 | interrupt-controller; | |
115 | clocks = <&cpg CPG_MOD 909>; | |
116 | power-domains = <&cpg>; | |
117 | }; | |
118 | ||
119 | gpio4: gpio@e6054000 { | |
120 | compatible = "renesas,gpio-r8a7795", | |
121 | "renesas,gpio-rcar"; | |
122 | reg = <0 0xe6054000 0 0x50>; | |
123 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
124 | #gpio-cells = <2>; | |
125 | gpio-controller; | |
126 | gpio-ranges = <&pfc 0 128 18>; | |
127 | #interrupt-cells = <2>; | |
128 | interrupt-controller; | |
129 | clocks = <&cpg CPG_MOD 908>; | |
130 | power-domains = <&cpg>; | |
131 | }; | |
132 | ||
133 | gpio5: gpio@e6055000 { | |
134 | compatible = "renesas,gpio-r8a7795", | |
135 | "renesas,gpio-rcar"; | |
136 | reg = <0 0xe6055000 0 0x50>; | |
137 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
138 | #gpio-cells = <2>; | |
139 | gpio-controller; | |
140 | gpio-ranges = <&pfc 0 160 26>; | |
141 | #interrupt-cells = <2>; | |
142 | interrupt-controller; | |
143 | clocks = <&cpg CPG_MOD 907>; | |
144 | power-domains = <&cpg>; | |
145 | }; | |
146 | ||
147 | gpio6: gpio@e6055400 { | |
148 | compatible = "renesas,gpio-r8a7795", | |
149 | "renesas,gpio-rcar"; | |
150 | reg = <0 0xe6055400 0 0x50>; | |
151 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
152 | #gpio-cells = <2>; | |
153 | gpio-controller; | |
154 | gpio-ranges = <&pfc 0 192 32>; | |
155 | #interrupt-cells = <2>; | |
156 | interrupt-controller; | |
157 | clocks = <&cpg CPG_MOD 906>; | |
158 | power-domains = <&cpg>; | |
159 | }; | |
160 | ||
161 | gpio7: gpio@e6055800 { | |
162 | compatible = "renesas,gpio-r8a7795", | |
163 | "renesas,gpio-rcar"; | |
164 | reg = <0 0xe6055800 0 0x50>; | |
165 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
166 | #gpio-cells = <2>; | |
167 | gpio-controller; | |
168 | gpio-ranges = <&pfc 0 224 4>; | |
169 | #interrupt-cells = <2>; | |
170 | interrupt-controller; | |
171 | clocks = <&cpg CPG_MOD 905>; | |
172 | power-domains = <&cpg>; | |
173 | }; | |
174 | ||
26a7e06d SH |
175 | timer { |
176 | compatible = "arm,armv8-timer"; | |
177 | interrupts = <GIC_PPI 13 | |
178 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
179 | <GIC_PPI 14 | |
180 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
181 | <GIC_PPI 11 | |
182 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
183 | <GIC_PPI 10 | |
184 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; | |
185 | }; | |
186 | ||
187 | cpg: clock-controller@e6150000 { | |
188 | compatible = "renesas,r8a7795-cpg-mssr"; | |
189 | reg = <0 0xe6150000 0 0x1000>; | |
190 | clocks = <&extal_clk>, <&extalr_clk>; | |
191 | clock-names = "extal", "extalr"; | |
192 | #clock-cells = <2>; | |
193 | #power-domain-cells = <0>; | |
194 | }; | |
d9202126 | 195 | |
9241844a KM |
196 | pfc: pfc@e6060000 { |
197 | compatible = "renesas,pfc-r8a7795"; | |
198 | reg = <0 0xe6060000 0 0x50c>; | |
199 | }; | |
200 | ||
d9202126 GU |
201 | dmac0: dma-controller@e6700000 { |
202 | /* Empty node for now */ | |
203 | }; | |
204 | ||
205 | dmac1: dma-controller@e7300000 { | |
206 | /* Empty node for now */ | |
207 | }; | |
208 | ||
209 | dmac2: dma-controller@e7310000 { | |
210 | /* Empty node for now */ | |
211 | }; | |
49af46b4 GU |
212 | |
213 | scif0: serial@e6e60000 { | |
214 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
215 | reg = <0 0xe6e60000 0 64>; | |
216 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
217 | clocks = <&cpg CPG_MOD 207>; | |
218 | clock-names = "sci_ick"; | |
219 | dmas = <&dmac1 0x51>, <&dmac1 0x50>; | |
220 | dma-names = "tx", "rx"; | |
221 | power-domains = <&cpg>; | |
222 | status = "disabled"; | |
223 | }; | |
224 | ||
225 | scif1: serial@e6e68000 { | |
226 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
227 | reg = <0 0xe6e68000 0 64>; | |
228 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | |
229 | clocks = <&cpg CPG_MOD 206>; | |
230 | clock-names = "sci_ick"; | |
231 | dmas = <&dmac1 0x53>, <&dmac1 0x52>; | |
232 | dma-names = "tx", "rx"; | |
233 | power-domains = <&cpg>; | |
234 | status = "disabled"; | |
235 | }; | |
236 | ||
237 | scif2: serial@e6e88000 { | |
238 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
239 | reg = <0 0xe6e88000 0 64>; | |
240 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
241 | clocks = <&cpg CPG_MOD 310>; | |
242 | clock-names = "sci_ick"; | |
243 | dmas = <&dmac1 0x13>, <&dmac1 0x12>; | |
244 | dma-names = "tx", "rx"; | |
245 | power-domains = <&cpg>; | |
246 | status = "disabled"; | |
247 | }; | |
248 | ||
249 | scif3: serial@e6c50000 { | |
250 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
251 | reg = <0 0xe6c50000 0 64>; | |
252 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
253 | clocks = <&cpg CPG_MOD 204>; | |
254 | clock-names = "sci_ick"; | |
255 | dmas = <&dmac0 0x57>, <&dmac0 0x56>; | |
256 | dma-names = "tx", "rx"; | |
257 | power-domains = <&cpg>; | |
258 | status = "disabled"; | |
259 | }; | |
260 | ||
261 | scif4: serial@e6c40000 { | |
262 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
263 | reg = <0 0xe6c40000 0 64>; | |
264 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
265 | clocks = <&cpg CPG_MOD 203>; | |
266 | clock-names = "sci_ick"; | |
267 | dmas = <&dmac0 0x59>, <&dmac0 0x58>; | |
268 | dma-names = "tx", "rx"; | |
269 | power-domains = <&cpg>; | |
270 | status = "disabled"; | |
271 | }; | |
272 | ||
273 | scif5: serial@e6f30000 { | |
274 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
275 | reg = <0 0xe6f30000 0 64>; | |
276 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
277 | clocks = <&cpg CPG_MOD 202>; | |
278 | clock-names = "sci_ick"; | |
279 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; | |
280 | dma-names = "tx", "rx"; | |
281 | power-domains = <&cpg>; | |
282 | status = "disabled"; | |
283 | }; | |
26a7e06d SH |
284 | }; |
285 | }; |